Merge gblack@m5.eecs.umich.edu:/bk/multiarch

[gem5.git] / dev / pciconfigall.cc

diff --git a/dev/pciconfigall.cc b/dev/pciconfigall.cc
index b2bff6cb644e5b8fcda16650125f36223f6e4ef4..d55084fa58e2e907777a261d32e794079b20d2e8 100644 (file)
--- a/dev/pciconfigall.cc
+++ b/dev/pciconfigall.cc
@@ -47,19 +47,20 @@
 #include "sim/system.hh"
 
 using namespace std;
+using namespace TheISA;
 
 PciConfigAll::PciConfigAll(const string &name,
                            Addr a, MemoryController *mmu,
-                           HierParams *hier, Bus *bus, Tick pio_latency)
+                           HierParams *hier, Bus *pio_bus, Tick pio_latency)
     : PioDevice(name, NULL), addr(a)
 {
     mmu->add_child(this, RangeSize(addr, size));
 
-    if (bus) {
-        pioInterface = newPioInterface(name + ".pio", hier, bus, this,
+    if (pio_bus) {
+        pioInterface = newPioInterface(name + ".pio", hier, pio_bus, this,
                                       &PciConfigAll::cacheAccess);
         pioInterface->addAddrRange(RangeSize(addr, size));
-        pioLatency = pio_latency * bus->clockRate;
+        pioLatency = pio_latency * pio_bus->clockRate;
     }
 
     // Make all the pointers to devices null
@@ -112,16 +113,16 @@ PciConfigAll::read(MemReqPtr &req, uint8_t *data)
         switch (req->size) {
            // case sizeof(uint64_t):
            //     *(uint64_t*)data = 0xFFFFFFFFFFFFFFFF;
-           //     return No_Fault;
+           //     return NoFault;
             case sizeof(uint32_t):
                 *(uint32_t*)data = 0xFFFFFFFF;
-                return No_Fault;
+                return NoFault;
             case sizeof(uint16_t):
                 *(uint16_t*)data = 0xFFFF;
-                return No_Fault;
+                return NoFault;
             case sizeof(uint8_t):
                 *(uint8_t*)data = 0xFF;
-                return No_Fault;
+                return NoFault;
             default:
                 panic("invalid access size(?) for PCI configspace!\n");
         }
@@ -131,7 +132,7 @@ PciConfigAll::read(MemReqPtr &req, uint8_t *data)
             case sizeof(uint16_t):
             case sizeof(uint8_t):
                 devices[device][func]->readConfig(reg, req->size, data);
-                return No_Fault;
+                return NoFault;
             default:
                 panic("invalid access size(?) for PCI configspace!\n");
         }
@@ -140,7 +141,7 @@ PciConfigAll::read(MemReqPtr &req, uint8_t *data)
     DPRINTFN("PCI Configspace  ERROR: read  daddr=%#x size=%d\n",
              daddr, req->size);
 
-    return No_Fault;
+    return NoFault;
 }
 
 Fault
@@ -164,7 +165,7 @@ PciConfigAll::write(MemReqPtr &req, const uint8_t *data)
 
     devices[device][func]->writeConfig(reg, req->size, data);
 
-    return No_Fault;
+    return NoFault;
 }
 
 void
@@ -200,7 +201,7 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(PciConfigAll)
     SimObjectParam<MemoryController *> mmu;
     Param<Addr> addr;
     Param<Addr> mask;
-    SimObjectParam<Bus*> io_bus;
+    SimObjectParam<Bus*> pio_bus;
     Param<Tick> pio_latency;
     SimObjectParam<HierParams *> hier;
 
@@ -211,7 +212,7 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(PciConfigAll)
     INIT_PARAM(mmu, "Memory Controller"),
     INIT_PARAM(addr, "Device Address"),
     INIT_PARAM(mask, "Address Mask"),
-    INIT_PARAM_DFLT(io_bus, "The IO Bus to attach to", NULL),
+    INIT_PARAM_DFLT(pio_bus, "The IO Bus to attach to", NULL),
     INIT_PARAM_DFLT(pio_latency, "Programmed IO latency in bus cycles", 1),
     INIT_PARAM_DFLT(hier, "Hierarchy global variables", &defaultHierParams)
 
@@ -219,7 +220,7 @@ END_INIT_SIM_OBJECT_PARAMS(PciConfigAll)
 
 CREATE_SIM_OBJECT(PciConfigAll)
 {
-    return new PciConfigAll(getInstanceName(), addr, mmu, hier, io_bus,
+    return new PciConfigAll(getInstanceName(), addr, mmu, hier, pio_bus,
                             pio_latency);
 }