/*
- * Copyright (c) 2003 The Regents of The University of Michigan
+ * Copyright (c) 2004 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
#ifndef __PCICONFIGALL_HH__
#define __PCICONFIGALL_HH__
-#include "mem/functional_mem/functional_memory.hh"
#include "dev/pcireg.h"
+#include "base/range.hh"
+#include "dev/io_device.hh"
+
static const uint32_t MAX_PCI_DEV = 32;
static const uint32_t MAX_PCI_FUNC = 8;
* space and passes the requests on to TsunamiPCIDev devices as
* appropriate.
*/
-class PciConfigAll : public FunctionalMemory
+class PciConfigAll : public PioDevice
{
private:
Addr addr;
* @param name name of the object
* @param a base address of the write
* @param mmu the memory controller
+ * @param hier object to store parameters universal the device hierarchy
+ * @param bus The bus that this device is attached to
*/
- PciConfigAll(const std::string &name, Addr a, MemoryController *mmu);
+ PciConfigAll(const std::string &name, Addr a, MemoryController *mmu,
+ HierParams *hier, Bus *bus, Tick pio_latency);
/**
virtual Fault write(MemReqPtr &req, const uint8_t *data);
+ /**
+ * Start up function to check if more than one person is using an interrupt line
+ * and print a warning if such a case exists
+ */
+ virtual void startup();
+
/**
* Serialize this object to the given output stream.
* @param os The stream to serialize to.
*/
virtual void unserialize(Checkpoint *cp, const std::string §ion);
+ /**
+ * Return how long this access will take.
+ * @param req the memory request to calcuate
+ * @return Tick when the request is done
+ */
+ Tick cacheAccess(MemReqPtr &req);
+
};
#endif // __PCICONFIGALL_HH__