Support NNPC and branch instructions ... Outputs to decoder.cc correctly

[gem5.git] / dev / pcidev.cc

diff --git a/dev/pcidev.cc b/dev/pcidev.cc
index 04a38151e1f5257af93c234c0f06ed58a9b391ca..c469e716aeb04d73221d1916537be1e57257647d 100644 (file)
--- a/dev/pcidev.cc
+++ b/dev/pcidev.cc
@@ -70,6 +70,62 @@ PciDev::PciDev(Params *p)
         p->configSpace->registerDevice(p->deviceNum, p->functionNum, this);
 }
 
+Fault *
+PciDev::read(MemReqPtr &req, uint8_t *data)
+{ return NoFault; }
+
+Fault *
+PciDev::write(MemReqPtr &req, const uint8_t *data)
+{ return NoFault; }
+
+Fault *
+PciDev::readBar0(MemReqPtr &req, Addr daddr, uint8_t *data)
+{ panic("not implemented"); }
+
+Fault *
+PciDev::readBar1(MemReqPtr &req, Addr daddr, uint8_t *data)
+{ panic("not implemented"); }
+
+Fault *
+PciDev::readBar2(MemReqPtr &req, Addr daddr, uint8_t *data)
+{ panic("not implemented"); }
+
+Fault *
+PciDev::readBar3(MemReqPtr &req, Addr daddr, uint8_t *data)
+{ panic("not implemented"); }
+
+Fault *
+PciDev::readBar4(MemReqPtr &req, Addr daddr, uint8_t *data)
+{ panic("not implemented"); }
+
+Fault *
+PciDev::readBar5(MemReqPtr &req, Addr daddr, uint8_t *data)
+{ panic("not implemented"); }
+
+Fault *
+PciDev::writeBar0(MemReqPtr &req, Addr daddr, const uint8_t *data)
+{ panic("not implemented"); }
+
+Fault *
+PciDev::writeBar1(MemReqPtr &req, Addr daddr, const uint8_t *data)
+{ panic("not implemented"); }
+
+Fault *
+PciDev::writeBar2(MemReqPtr &req, Addr daddr, const uint8_t *data)
+{ panic("not implemented"); }
+
+Fault *
+PciDev::writeBar3(MemReqPtr &req, Addr daddr, const uint8_t *data)
+{ panic("not implemented"); }
+
+Fault *
+PciDev::writeBar4(MemReqPtr &req, Addr daddr, const uint8_t *data)
+{ panic("not implemented"); }
+
+Fault *
+PciDev::writeBar5(MemReqPtr &req, Addr daddr, const uint8_t *data)
+{ panic("not implemented"); }
+
 void
 PciDev::readConfig(int offset, int size, uint8_t *data)
 {
@@ -203,7 +259,7 @@ PciDev::writeConfig(int offset, int size, const uint8_t *data)
 
           case PCI0_ROM_BASE_ADDR:
             if (letoh(data32) == 0xfffffffe)
-                config.expansionROM = letoh(0xffffffff);
+                config.expansionROM = htole((uint32_t)0xffffffff);
             else
                 config.expansionROM = data32;
             break;
@@ -228,17 +284,18 @@ PciDev::writeConfig(int offset, int size, const uint8_t *data)
 void
 PciDev::serialize(ostream &os)
 {
-    SERIALIZE_ARRAY(BARSize, sizeof(BARSize));
-    SERIALIZE_ARRAY(BARAddrs, sizeof(BARAddrs));
-    SERIALIZE_ARRAY(config.data, sizeof(config.data));
+    SERIALIZE_ARRAY(BARSize, sizeof(BARSize) / sizeof(BARSize[0]));
+    SERIALIZE_ARRAY(BARAddrs, sizeof(BARAddrs) / sizeof(BARAddrs[0]));
+    SERIALIZE_ARRAY(config.data, sizeof(config.data) / sizeof(config.data[0]));
 }
 
 void
 PciDev::unserialize(Checkpoint *cp, const std::string &section)
 {
-    UNSERIALIZE_ARRAY(BARSize, sizeof(BARSize));
-    UNSERIALIZE_ARRAY(BARAddrs, sizeof(BARAddrs));
-    UNSERIALIZE_ARRAY(config.data, sizeof(config.data));
+    UNSERIALIZE_ARRAY(BARSize, sizeof(BARSize) / sizeof(BARSize[0]));
+    UNSERIALIZE_ARRAY(BARAddrs, sizeof(BARAddrs) / sizeof(BARAddrs[0]));
+    UNSERIALIZE_ARRAY(config.data,
+                      sizeof(config.data) / sizeof(config.data[0]));
 
     // Add the MMU mappings for the BARs
     for (int i=0; i < 6; i++) {