/*
- * Copyright (c) 2004 The Regents of The University of Michigan
+ * Copyright (c) 2004-2005 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
#include "base/misc.hh"
#include "base/str.hh" // for to_number
#include "base/trace.hh"
-#include "dev/pciareg.h"
#include "dev/pcidev.hh"
#include "dev/pciconfigall.hh"
#include "mem/bus/bus.hh"
-#include "mem/functional_mem/memory_control.hh"
+#include "mem/functional/memory_control.hh"
#include "sim/builder.hh"
#include "sim/param.hh"
-#include "sim/universe.hh"
+#include "sim/root.hh"
#include "dev/tsunamireg.h"
using namespace std;
p->configSpace->registerDevice(p->deviceNum, p->functionNum, this);
}
+Fault *
+PciDev::read(MemReqPtr &req, uint8_t *data)
+{ return NoFault; }
+
+Fault *
+PciDev::write(MemReqPtr &req, const uint8_t *data)
+{ return NoFault; }
+
+Fault *
+PciDev::readBar0(MemReqPtr &req, Addr daddr, uint8_t *data)
+{ panic("not implemented"); }
+
+Fault *
+PciDev::readBar1(MemReqPtr &req, Addr daddr, uint8_t *data)
+{ panic("not implemented"); }
+
+Fault *
+PciDev::readBar2(MemReqPtr &req, Addr daddr, uint8_t *data)
+{ panic("not implemented"); }
+
+Fault *
+PciDev::readBar3(MemReqPtr &req, Addr daddr, uint8_t *data)
+{ panic("not implemented"); }
+
+Fault *
+PciDev::readBar4(MemReqPtr &req, Addr daddr, uint8_t *data)
+{ panic("not implemented"); }
+
+Fault *
+PciDev::readBar5(MemReqPtr &req, Addr daddr, uint8_t *data)
+{ panic("not implemented"); }
+
+Fault *
+PciDev::writeBar0(MemReqPtr &req, Addr daddr, const uint8_t *data)
+{ panic("not implemented"); }
+
+Fault *
+PciDev::writeBar1(MemReqPtr &req, Addr daddr, const uint8_t *data)
+{ panic("not implemented"); }
+
+Fault *
+PciDev::writeBar2(MemReqPtr &req, Addr daddr, const uint8_t *data)
+{ panic("not implemented"); }
+
+Fault *
+PciDev::writeBar3(MemReqPtr &req, Addr daddr, const uint8_t *data)
+{ panic("not implemented"); }
+
+Fault *
+PciDev::writeBar4(MemReqPtr &req, Addr daddr, const uint8_t *data)
+{ panic("not implemented"); }
+
+Fault *
+PciDev::writeBar5(MemReqPtr &req, Addr daddr, const uint8_t *data)
+{ panic("not implemented"); }
+
void
-PciDev::ReadConfig(int offset, int size, uint8_t *data)
+PciDev::readConfig(int offset, int size, uint8_t *data)
{
if (offset >= PCI_DEVICE_SPECIFIC)
panic("Device specific PCI config space not implemented!\n");
switch(size) {
- case sizeof(uint32_t):
- memcpy((uint8_t*)data, config.data + offset, sizeof(uint32_t));
- *(uint32_t*)data = htoa(*(uint32_t*)data);
- DPRINTF(PCIDEV,
- "read device: %#x function: %#x register: %#x %d bytes: data: %#x\n",
- params()->deviceNum, params()->functionNum, offset, size,
- *(uint32_t*)(config.data + offset));
+ case sizeof(uint8_t):
+ *data = config.data[offset];
break;
-
case sizeof(uint16_t):
- memcpy((uint8_t*)data, config.data + offset, sizeof(uint16_t));
- *(uint16_t*)data = htoa(*(uint16_t*)data);
- DPRINTF(PCIDEV,
- "read device: %#x function: %#x register: %#x %d bytes: data: %#x\n",
- params()->deviceNum, params()->functionNum, offset, size,
- *(uint16_t*)(config.data + offset));
+ *(uint16_t*)data = *(uint16_t*)&config.data[offset];
break;
-
- case sizeof(uint8_t):
- memcpy((uint8_t*)data, config.data + offset, sizeof(uint8_t));
- DPRINTF(PCIDEV,
- "read device: %#x function: %#x register: %#x %d bytes: data: %#x\n",
- params()->deviceNum, params()->functionNum, offset, size,
- (uint16_t)(*(uint8_t*)(config.data + offset)));
+ case sizeof(uint32_t):
+ *(uint32_t*)data = *(uint32_t*)&config.data[offset];
break;
-
default:
- panic("Invalid Read Size");
+ panic("Invalid PCI configuration read size!\n");
}
+
+ DPRINTF(PCIDEV,
+ "read device: %#x function: %#x register: %#x %d bytes: data: %#x\n",
+ params()->deviceNum, params()->functionNum, offset, size,
+ *(uint32_t*)data);
}
void
-PciDev::WriteConfig(int offset, int size, uint32_t data)
+PciDev::writeConfig(int offset, int size, const uint8_t *data)
{
if (offset >= PCI_DEVICE_SPECIFIC)
panic("Device specific PCI config space not implemented!\n");
- uint32_t barnum;
-
- union {
- uint8_t byte_value;
- uint16_t half_value;
- uint32_t word_value;
- };
- word_value = data;
+ uint8_t &data8 = *(uint8_t*)data;
+ uint16_t &data16 = *(uint16_t*)data;
+ uint32_t &data32 = *(uint32_t*)data;
DPRINTF(PCIDEV,
"write device: %#x function: %#x reg: %#x size: %d data: %#x\n",
- params()->deviceNum, params()->functionNum, offset, size,
- word_value);
-
- barnum = (offset - PCI0_BASE_ADDR0) >> 2;
+ params()->deviceNum, params()->functionNum, offset, size, data32);
switch (size) {
case sizeof(uint8_t): // 1-byte access
switch (offset) {
case PCI0_INTERRUPT_LINE:
+ config.interruptLine = data8;
case PCI_CACHE_LINE_SIZE:
+ config.cacheLineSize = data8;
case PCI_LATENCY_TIMER:
- *(uint8_t *)&config.data[offset] = htoa(byte_value);
+ config.latencyTimer = data8;
+ break;
+ /* Do nothing for these read-only registers */
+ case PCI0_INTERRUPT_PIN:
+ case PCI0_MINIMUM_GRANT:
+ case PCI0_MAXIMUM_LATENCY:
+ case PCI_CLASS_CODE:
+ case PCI_REVISION_ID:
break;
-
default:
panic("writing to a read only register");
}
case sizeof(uint16_t): // 2-byte access
switch (offset) {
case PCI_COMMAND:
+ config.command = data16;
case PCI_STATUS:
+ config.status = data16;
case PCI_CACHE_LINE_SIZE:
- *(uint16_t *)&config.data[offset] = htoa(half_value);
+ config.cacheLineSize = data16;
break;
-
default:
panic("writing to a read only register");
}
break;
- case sizeof(uint16_t)+1: // 3-byte access
- panic("invalid access size");
-
case sizeof(uint32_t): // 4-byte access
switch (offset) {
case PCI0_BASE_ADDR0:
case PCI0_BASE_ADDR3:
case PCI0_BASE_ADDR4:
case PCI0_BASE_ADDR5:
+
+ uint32_t barnum, bar_mask;
+ Addr base_addr, base_size, space_base;
+
+ barnum = BAR_NUMBER(offset);
+
+ if (BAR_IO_SPACE(letoh(config.baseAddr[barnum]))) {
+ bar_mask = BAR_IO_MASK;
+ space_base = TSUNAMI_PCI0_IO;
+ } else {
+ bar_mask = BAR_MEM_MASK;
+ space_base = TSUNAMI_PCI0_MEMORY;
+ }
+
// Writing 0xffffffff to a BAR tells the card to set the
- // value of the bar
- // to size of memory it needs
- if (word_value == 0xffffffff) {
+ // value of the bar to size of memory it needs
+ if (letoh(data32) == 0xffffffff) {
// This is I/O Space, bottom two bits are read only
- if (htoa(config.data[offset]) & 0x1) {
- *(uint32_t *)&config.data[offset] = htoa(
- ~(BARSize[barnum] - 1) |
- (htoa(config.data[offset]) & 0x3));
- } else {
- // This is memory space, bottom four bits are read only
- *(uint32_t *)&config.data[offset] = htoa(
- ~(BARSize[barnum] - 1) |
- (htoa(config.data[offset]) & 0xF));
- }
+
+ config.baseAddr[barnum] = letoh(
+ (~(BARSize[barnum] - 1) & ~bar_mask) |
+ (letoh(config.baseAddr[barnum]) & bar_mask));
} else {
MemoryController *mmu = params()->mmu;
- // This is I/O Space, bottom two bits are read only
- if(htoa(config.data[offset]) & 0x1) {
- *(uint32_t *)&config.data[offset] =
- htoa((word_value & ~0x3) |
- (htoa(config.data[offset]) & 0x3));
-
- if (word_value & ~0x1) {
- Addr base_addr = (word_value & ~0x1) + TSUNAMI_PCI0_IO;
- Addr base_size = BARSize[barnum];
-
- // It's never been set
- if (BARAddrs[barnum] == 0)
- mmu->add_child((FunctionalMemory *)this,
- RangeSize(base_addr, base_size));
- else
- mmu->update_child((FunctionalMemory *)this,
- RangeSize(BARAddrs[barnum],
- base_size),
- RangeSize(base_addr, base_size));
-
- BARAddrs[barnum] = base_addr;
- }
-
- } else {
- // This is memory space, bottom four bits are read only
- *(uint32_t *)&config.data[offset] =
- htoa((word_value & ~0xF) |
- (htoa(config.data[offset]) & 0xF));
-
- if (word_value & ~0x3) {
- Addr base_addr = (word_value & ~0x3) +
- TSUNAMI_PCI0_MEMORY;
-
- Addr base_size = BARSize[barnum];
-
- // It's never been set
- if (BARAddrs[barnum] == 0)
- mmu->add_child((FunctionalMemory *)this,
- RangeSize(base_addr, base_size));
- else
- mmu->update_child((FunctionalMemory *)this,
- RangeSize(BARAddrs[barnum],
- base_size),
- RangeSize(base_addr, base_size));
-
- BARAddrs[barnum] = base_addr;
- }
- }
+ config.baseAddr[barnum] = letoh(
+ (letoh(data32) & ~bar_mask) |
+ (letoh(config.baseAddr[barnum]) & bar_mask));
+
+ if (letoh(config.baseAddr[barnum]) & ~bar_mask) {
+ base_addr = (letoh(data32) & ~bar_mask) + space_base;
+ base_size = BARSize[barnum];
+
+ // It's never been set
+ if (BARAddrs[barnum] == 0)
+ mmu->add_child((FunctionalMemory *)this,
+ RangeSize(base_addr, base_size));
+ else
+ mmu->update_child((FunctionalMemory *)this,
+ RangeSize(BARAddrs[barnum], base_size),
+ RangeSize(base_addr, base_size));
+
+ BARAddrs[barnum] = base_addr;
+ }
}
break;
case PCI0_ROM_BASE_ADDR:
- if (word_value == 0xfffffffe)
- *(uint32_t *)&config.data[offset] = 0xffffffff;
+ if (letoh(data32) == 0xfffffffe)
+ config.expansionROM = htole((uint32_t)0xffffffff);
else
- *(uint32_t *)&config.data[offset] = htoa(word_value);
+ config.expansionROM = data32;
break;
case PCI_COMMAND:
// This could also clear some of the error bits in the Status
// register. However they should never get set, so lets ignore
// it for now
- *(uint16_t *)&config.data[offset] = htoa(half_value);
+ config.command = data16;
break;
default:
DPRINTF(PCIDEV, "Writing to a read only register");
}
break;
+
+ default:
+ panic("invalid access size");
}
}
void
PciDev::serialize(ostream &os)
{
- SERIALIZE_ARRAY(BARSize, 6);
- SERIALIZE_ARRAY(BARAddrs, 6);
- SERIALIZE_ARRAY(config.data, 64);
+ SERIALIZE_ARRAY(BARSize, sizeof(BARSize) / sizeof(BARSize[0]));
+ SERIALIZE_ARRAY(BARAddrs, sizeof(BARAddrs) / sizeof(BARAddrs[0]));
+ SERIALIZE_ARRAY(config.data, sizeof(config.data) / sizeof(config.data[0]));
}
void
PciDev::unserialize(Checkpoint *cp, const std::string §ion)
{
- UNSERIALIZE_ARRAY(BARSize, 6);
- UNSERIALIZE_ARRAY(BARAddrs, 6);
- UNSERIALIZE_ARRAY(config.data, 64);
+ UNSERIALIZE_ARRAY(BARSize, sizeof(BARSize) / sizeof(BARSize[0]));
+ UNSERIALIZE_ARRAY(BARAddrs, sizeof(BARAddrs) / sizeof(BARAddrs[0]));
+ UNSERIALIZE_ARRAY(config.data,
+ sizeof(config.data) / sizeof(config.data[0]));
// Add the MMU mappings for the BARs
for (int i=0; i < 6; i++) {
BEGIN_DECLARE_SIM_OBJECT_PARAMS(PciConfigData)
- SimObjectParam<MemoryController *> mmu;
- Param<Addr> addr;
- SimObjectParam<Bus*> io_bus;
- Param<Tick> pio_latency;
-
Param<uint16_t> VendorID;
Param<uint16_t> DeviceID;
Param<uint16_t> Command;
BEGIN_INIT_SIM_OBJECT_PARAMS(PciConfigData)
- INIT_PARAM(mmu, "Memory Controller"),
- INIT_PARAM(addr, "Device Address"),
- INIT_PARAM_DFLT(io_bus, "The IO Bus to attach to", NULL),
- INIT_PARAM_DFLT(pio_latency, "Programmed IO latency in bus cycles", 1),
-
INIT_PARAM(VendorID, "Vendor ID"),
INIT_PARAM(DeviceID, "Device ID"),
INIT_PARAM_DFLT(Command, "Command Register", 0x00),
{
PciConfigData *data = new PciConfigData(getInstanceName());
- data->config.hdr.vendor = htoa(VendorID);
- data->config.hdr.device = htoa(DeviceID);
- data->config.hdr.command = htoa(Command);
- data->config.hdr.status = htoa(Status);
- data->config.hdr.revision = htoa(Revision);
- data->config.hdr.progIF = htoa(ProgIF);
- data->config.hdr.subClassCode = htoa(SubClassCode);
- data->config.hdr.classCode = htoa(ClassCode);
- data->config.hdr.cacheLineSize = htoa(CacheLineSize);
- data->config.hdr.latencyTimer = htoa(LatencyTimer);
- data->config.hdr.headerType = htoa(HeaderType);
- data->config.hdr.bist = htoa(BIST);
-
- data->config.hdr.pci0.baseAddr0 = htoa(BAR0);
- data->config.hdr.pci0.baseAddr1 = htoa(BAR1);
- data->config.hdr.pci0.baseAddr2 = htoa(BAR2);
- data->config.hdr.pci0.baseAddr3 = htoa(BAR3);
- data->config.hdr.pci0.baseAddr4 = htoa(BAR4);
- data->config.hdr.pci0.baseAddr5 = htoa(BAR5);
- data->config.hdr.pci0.cardbusCIS = htoa(CardbusCIS);
- data->config.hdr.pci0.subsystemVendorID = htoa(SubsystemVendorID);
- data->config.hdr.pci0.subsystemID = htoa(SubsystemVendorID);
- data->config.hdr.pci0.expansionROM = htoa(ExpansionROM);
- data->config.hdr.pci0.interruptLine = htoa(InterruptLine);
- data->config.hdr.pci0.interruptPin = htoa(InterruptPin);
- data->config.hdr.pci0.minimumGrant = htoa(MinimumGrant);
- data->config.hdr.pci0.maximumLatency = htoa(MaximumLatency);
+ data->config.vendor = htole(VendorID);
+ data->config.device = htole(DeviceID);
+ data->config.command = htole(Command);
+ data->config.status = htole(Status);
+ data->config.revision = htole(Revision);
+ data->config.progIF = htole(ProgIF);
+ data->config.subClassCode = htole(SubClassCode);
+ data->config.classCode = htole(ClassCode);
+ data->config.cacheLineSize = htole(CacheLineSize);
+ data->config.latencyTimer = htole(LatencyTimer);
+ data->config.headerType = htole(HeaderType);
+ data->config.bist = htole(BIST);
+
+ data->config.baseAddr0 = htole(BAR0);
+ data->config.baseAddr1 = htole(BAR1);
+ data->config.baseAddr2 = htole(BAR2);
+ data->config.baseAddr3 = htole(BAR3);
+ data->config.baseAddr4 = htole(BAR4);
+ data->config.baseAddr5 = htole(BAR5);
+ data->config.cardbusCIS = htole(CardbusCIS);
+ data->config.subsystemVendorID = htole(SubsystemVendorID);
+ data->config.subsystemID = htole(SubsystemVendorID);
+ data->config.expansionROM = htole(ExpansionROM);
+ data->config.interruptLine = htole(InterruptLine);
+ data->config.interruptPin = htole(InterruptPin);
+ data->config.minimumGrant = htole(MinimumGrant);
+ data->config.maximumLatency = htole(MaximumLatency);
data->BARSize[0] = BAR0Size;
data->BARSize[1] = BAR1Size;
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