/*
- * Copyright (c) 2003 The Regents of The University of Michigan
+ * Copyright (c) 2004 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
#include "base/str.hh" // for to_number
#include "base/trace.hh"
#include "dev/pciareg.h"
-#include "dev/scsi_ctrl.hh"
#include "dev/pcidev.hh"
#include "dev/pciconfigall.hh"
#include "mem/functional_mem/memory_control.hh"
using namespace std;
-PciDev::PciDev(const string &name, MemoryController *mmu, PCIConfigAll *cf,
- PciConfigData *cd, uint32_t bus, uint32_t dev, uint32_t func)
- : MmapDevice(name), MMU(mmu), ConfigSpace(cf), ConfigData(cd),
- Bus(bus), Device(dev), Function(func)
+PciDev::PciDev(Params *p)
+ : DmaDevice(p->name), _params(p), plat(p->plat), configData(p->configData)
{
// copy the config data from the PciConfigData object
- if (cd) {
- memcpy(config.data, cd->config.data, sizeof(config.data));
- memcpy(BARSize, cd->BARSize, sizeof(BARSize));
- memcpy(BARAddrs, cd->BARAddrs, sizeof(BARAddrs));
+ if (configData) {
+ memcpy(config.data, configData->config.data, sizeof(config.data));
+ memcpy(BARSize, configData->BARSize, sizeof(BARSize));
+ memcpy(BARAddrs, configData->BARAddrs, sizeof(BARAddrs));
} else
panic("NULL pointer to configuration data");
// Setup pointer in config space to point to this entry
- if (cf->devices[dev][func] != NULL)
- panic("Two PCI devices occuping same dev: %#x func: %#x", dev, func);
+ if (p->configSpace->deviceExists(p->deviceNum, p->functionNum))
+ panic("Two PCI devices occuping same dev: %#x func: %#x",
+ p->deviceNum, p->functionNum);
else
- cf->devices[dev][func] = this;
+ p->configSpace->registerDevice(p->deviceNum, p->functionNum, this);
}
void
PciDev::ReadConfig(int offset, int size, uint8_t *data)
{
+ if (offset >= PCI_DEVICE_SPECIFIC)
+ panic("Device specific PCI config space not implemented!\n");
+
switch(size) {
case sizeof(uint32_t):
- memcpy((uint32_t*)data, config.data + offset, sizeof(uint32_t));
+ memcpy((uint8_t*)data, config.data + offset, sizeof(uint32_t));
+ *(uint32_t*)data = htoa(*(uint32_t*)data);
DPRINTF(PCIDEV,
- "read device: %#x function: %#x register: %#x data: %#x\n",
- Device, Function, offset, *(uint32_t*)(config.data + offset));
+ "read device: %#x function: %#x register: %#x %d bytes: data: %#x\n",
+ params()->deviceNum, params()->functionNum, offset, size,
+ *(uint32_t*)(config.data + offset));
break;
case sizeof(uint16_t):
- memcpy((uint16_t*)data, config.data + offset, sizeof(uint16_t));
+ memcpy((uint8_t*)data, config.data + offset, sizeof(uint16_t));
+ *(uint16_t*)data = htoa(*(uint16_t*)data);
DPRINTF(PCIDEV,
- "read device: %#x function: %#x register: %#x data: %#x\n",
- Device, Function, offset, *(uint16_t*)(config.data + offset));
+ "read device: %#x function: %#x register: %#x %d bytes: data: %#x\n",
+ params()->deviceNum, params()->functionNum, offset, size,
+ *(uint16_t*)(config.data + offset));
break;
case sizeof(uint8_t):
memcpy((uint8_t*)data, config.data + offset, sizeof(uint8_t));
- printf("data: %#x\n", *(uint8_t*)(config.data + offset));
DPRINTF(PCIDEV,
- "read device: %#x function: %#x register: %#x data: %#x\n",
- Device, Function, offset, *(uint8_t*)(config.data + offset));
+ "read device: %#x function: %#x register: %#x %d bytes: data: %#x\n",
+ params()->deviceNum, params()->functionNum, offset, size,
+ (uint16_t)(*(uint8_t*)(config.data + offset)));
break;
default:
void
PciDev::WriteConfig(int offset, int size, uint32_t data)
{
+ if (offset >= PCI_DEVICE_SPECIFIC)
+ panic("Device specific PCI config space not implemented!\n");
+
uint32_t barnum;
union {
word_value = data;
DPRINTF(PCIDEV,
- "write device: %#x function: %#x reg: %#x size: %#x data: %#x\n",
- Device, Function, offset, size, word_value);
+ "write device: %#x function: %#x reg: %#x size: %d data: %#x\n",
+ params()->deviceNum, params()->functionNum, offset, size,
+ word_value);
barnum = (offset - PCI0_BASE_ADDR0) >> 2;
case PCI0_INTERRUPT_LINE:
case PCI_CACHE_LINE_SIZE:
case PCI_LATENCY_TIMER:
- *(uint8_t *)&config.data[offset] = byte_value;
+ *(uint8_t *)&config.data[offset] = htoa(byte_value);
break;
default:
case PCI_COMMAND:
case PCI_STATUS:
case PCI_CACHE_LINE_SIZE:
- *(uint16_t *)&config.data[offset] = half_value;
+ *(uint16_t *)&config.data[offset] = htoa(half_value);
break;
default:
// to size of memory it needs
if (word_value == 0xffffffff) {
// This is I/O Space, bottom two bits are read only
- if (config.data[offset] & 0x1) {
- *(uint32_t *)&config.data[offset] =
+ if (htoa(config.data[offset]) & 0x1) {
+ *(uint32_t *)&config.data[offset] = htoa(
~(BARSize[barnum] - 1) |
- (config.data[offset] & 0x3);
+ (htoa(config.data[offset]) & 0x3));
} else {
// This is memory space, bottom four bits are read only
- *(uint32_t *)&config.data[offset] =
+ *(uint32_t *)&config.data[offset] = htoa(
~(BARSize[barnum] - 1) |
- (config.data[offset] & 0xF);
+ (htoa(config.data[offset]) & 0xF));
}
} else {
+ MemoryController *mmu = params()->mmu;
+
// This is I/O Space, bottom two bits are read only
- if(config.data[offset] & 0x1) {
- *(uint32_t *)&config.data[offset] = (word_value & ~0x3) |
- (config.data[offset] & 0x3);
+ if(htoa(config.data[offset]) & 0x1) {
+ *(uint32_t *)&config.data[offset] =
+ htoa((word_value & ~0x3) |
+ (htoa(config.data[offset]) & 0x3));
if (word_value & ~0x1) {
+ Addr base_addr = (word_value & ~0x1) + TSUNAMI_PCI0_IO;
+ Addr base_size = BARSize[barnum];
+
// It's never been set
if (BARAddrs[barnum] == 0)
- AddMapping((word_value & ~0x1) + TSUNAMI_PCI0_IO,
- BARSize[barnum]-1, MMU);
+ mmu->add_child((FunctionalMemory *)this,
+ RangeSize(base_addr, base_size));
else
- ChangeMapping(BARAddrs[barnum], BARSize[barnum]-1,
- (word_value & ~0x1) + TSUNAMI_PCI0_IO,
- BARSize[barnum]-1, MMU);
- BARAddrs[barnum] = (word_value & ~0x1) + TSUNAMI_PCI0_IO;
+ mmu->update_child((FunctionalMemory *)this,
+ RangeSize(BARAddrs[barnum],
+ base_size),
+ RangeSize(base_addr, base_size));
+
+ BARAddrs[barnum] = base_addr;
}
} else {
// This is memory space, bottom four bits are read only
- *(uint32_t *)&config.data[offset] = (word_value & ~0xF) |
- (config.data[offset] & 0xF);
+ *(uint32_t *)&config.data[offset] =
+ htoa((word_value & ~0xF) |
+ (htoa(config.data[offset]) & 0xF));
if (word_value & ~0x3) {
+ Addr base_addr = (word_value & ~0x3) +
+ TSUNAMI_PCI0_MEMORY;
+
+ Addr base_size = BARSize[barnum];
+
// It's never been set
if (BARAddrs[barnum] == 0)
- AddMapping((word_value & ~0x3) + TSUNAMI_PCI0_MEMORY,
- BARSize[barnum]-1, MMU);
+ mmu->add_child((FunctionalMemory *)this,
+ RangeSize(base_addr, base_size));
else
- ChangeMapping(BARAddrs[barnum], BARSize[barnum]-1,
- (word_value & ~0x3) +
- TSUNAMI_PCI0_MEMORY,
- BARSize[barnum]-1, MMU);
- BARAddrs[barnum] = (word_value & ~0x3) +
- TSUNAMI_PCI0_MEMORY;
+ mmu->update_child((FunctionalMemory *)this,
+ RangeSize(BARAddrs[barnum],
+ base_size),
+ RangeSize(base_addr, base_size));
+
+ BARAddrs[barnum] = base_addr;
}
}
}
if (word_value == 0xfffffffe)
*(uint32_t *)&config.data[offset] = 0xffffffff;
else
- *(uint32_t *)&config.data[offset] = word_value;
+ *(uint32_t *)&config.data[offset] = htoa(word_value);
break;
case PCI_COMMAND:
// This could also clear some of the error bits in the Status
// register. However they should never get set, so lets ignore
// it for now
- *(uint16_t *)&config.data[offset] = half_value;
+ *(uint16_t *)&config.data[offset] = htoa(half_value);
break;
default:
- panic("writing to a read only register");
+ DPRINTF(PCIDEV, "Writing to a read only register");
}
break;
}
void
PciDev::serialize(ostream &os)
{
+ SERIALIZE_ARRAY(BARSize, 6);
+ SERIALIZE_ARRAY(BARAddrs, 6);
SERIALIZE_ARRAY(config.data, 64);
}
void
PciDev::unserialize(Checkpoint *cp, const std::string §ion)
{
+ UNSERIALIZE_ARRAY(BARSize, 6);
+ UNSERIALIZE_ARRAY(BARAddrs, 6);
UNSERIALIZE_ARRAY(config.data, 64);
+
+ // Add the MMU mappings for the BARs
+ for (int i=0; i < 6; i++) {
+ if (BARAddrs[i] != 0)
+ params()->mmu->add_child(this, RangeSize(BARAddrs[i], BARSize[i]));
+ }
}
#ifndef DOXYGEN_SHOULD_SKIP_THIS
BEGIN_DECLARE_SIM_OBJECT_PARAMS(PciConfigData)
- Param<int> VendorID;
- Param<int> DeviceID;
- Param<int> Command;
- Param<int> Status;
- Param<int> Revision;
- Param<int> ProgIF;
- Param<int> SubClassCode;
- Param<int> ClassCode;
- Param<int> CacheLineSize;
- Param<int> LatencyTimer;
- Param<int> HeaderType;
- Param<int> BIST;
+ Param<uint16_t> VendorID;
+ Param<uint16_t> DeviceID;
+ Param<uint16_t> Command;
+ Param<uint16_t> Status;
+ Param<uint8_t> Revision;
+ Param<uint8_t> ProgIF;
+ Param<uint8_t> SubClassCode;
+ Param<uint8_t> ClassCode;
+ Param<uint8_t> CacheLineSize;
+ Param<uint8_t> LatencyTimer;
+ Param<uint8_t> HeaderType;
+ Param<uint8_t> BIST;
Param<uint32_t> BAR0;
Param<uint32_t> BAR1;
Param<uint32_t> BAR2;
Param<uint32_t> BAR4;
Param<uint32_t> BAR5;
Param<uint32_t> CardbusCIS;
- Param<int> SubsystemVendorID;
- Param<int> SubsystemID;
+ Param<uint16_t> SubsystemVendorID;
+ Param<uint16_t> SubsystemID;
Param<uint32_t> ExpansionROM;
- Param<int> InterruptLine;
- Param<int> InterruptPin;
- Param<int> MinimumGrant;
- Param<int> MaximumLatency;
+ Param<uint8_t> InterruptLine;
+ Param<uint8_t> InterruptPin;
+ Param<uint8_t> MinimumGrant;
+ Param<uint8_t> MaximumLatency;
Param<uint32_t> BAR0Size;
Param<uint32_t> BAR1Size;
Param<uint32_t> BAR2Size;
{
PciConfigData *data = new PciConfigData(getInstanceName());
- data->config.hdr.vendor = VendorID;
- data->config.hdr.device = DeviceID;
- data->config.hdr.command = Command;
- data->config.hdr.status = Status;
- data->config.hdr.revision = Revision;
- data->config.hdr.progIF = ProgIF;
- data->config.hdr.subClassCode = SubClassCode;
- data->config.hdr.classCode = ClassCode;
- data->config.hdr.cacheLineSize = CacheLineSize;
- data->config.hdr.latencyTimer = LatencyTimer;
- data->config.hdr.headerType = HeaderType;
- data->config.hdr.bist = BIST;
-
- data->config.hdr.pci0.baseAddr0 = BAR0;
- data->config.hdr.pci0.baseAddr1 = BAR1;
- data->config.hdr.pci0.baseAddr2 = BAR2;
- data->config.hdr.pci0.baseAddr3 = BAR3;
- data->config.hdr.pci0.baseAddr4 = BAR4;
- data->config.hdr.pci0.baseAddr5 = BAR5;
- data->config.hdr.pci0.cardbusCIS = CardbusCIS;
- data->config.hdr.pci0.subsystemVendorID = SubsystemVendorID;
- data->config.hdr.pci0.subsystemID = SubsystemVendorID;
- data->config.hdr.pci0.expansionROM = ExpansionROM;
- data->config.hdr.pci0.interruptLine = InterruptLine;
- data->config.hdr.pci0.interruptPin = InterruptPin;
- data->config.hdr.pci0.minimumGrant = MinimumGrant;
- data->config.hdr.pci0.maximumLatency = MaximumLatency;
+ data->config.hdr.vendor = htoa(VendorID);
+ data->config.hdr.device = htoa(DeviceID);
+ data->config.hdr.command = htoa(Command);
+ data->config.hdr.status = htoa(Status);
+ data->config.hdr.revision = htoa(Revision);
+ data->config.hdr.progIF = htoa(ProgIF);
+ data->config.hdr.subClassCode = htoa(SubClassCode);
+ data->config.hdr.classCode = htoa(ClassCode);
+ data->config.hdr.cacheLineSize = htoa(CacheLineSize);
+ data->config.hdr.latencyTimer = htoa(LatencyTimer);
+ data->config.hdr.headerType = htoa(HeaderType);
+ data->config.hdr.bist = htoa(BIST);
+
+ data->config.hdr.pci0.baseAddr0 = htoa(BAR0);
+ data->config.hdr.pci0.baseAddr1 = htoa(BAR1);
+ data->config.hdr.pci0.baseAddr2 = htoa(BAR2);
+ data->config.hdr.pci0.baseAddr3 = htoa(BAR3);
+ data->config.hdr.pci0.baseAddr4 = htoa(BAR4);
+ data->config.hdr.pci0.baseAddr5 = htoa(BAR5);
+ data->config.hdr.pci0.cardbusCIS = htoa(CardbusCIS);
+ data->config.hdr.pci0.subsystemVendorID = htoa(SubsystemVendorID);
+ data->config.hdr.pci0.subsystemID = htoa(SubsystemVendorID);
+ data->config.hdr.pci0.expansionROM = htoa(ExpansionROM);
+ data->config.hdr.pci0.interruptLine = htoa(InterruptLine);
+ data->config.hdr.pci0.interruptPin = htoa(InterruptPin);
+ data->config.hdr.pci0.minimumGrant = htoa(MinimumGrant);
+ data->config.hdr.pci0.maximumLatency = htoa(MaximumLatency);
data->BARSize[0] = BAR0Size;
data->BARSize[1] = BAR1Size;
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