/*
- * Copyright (c) 2004 The Regents of The University of Michigan
+ * Copyright (c) 2004-2005 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
#include "base/inet.hh"
#include "cpu/exec_context.hh"
#include "cpu/intr_control.hh"
-#include "dev/dma.hh"
#include "dev/etherlink.hh"
#include "dev/sinic.hh"
#include "dev/pciconfigall.hh"
#include "mem/bus/dma_interface.hh"
#include "mem/bus/pio_interface.hh"
#include "mem/bus/pio_interface_impl.hh"
-#include "mem/functional_mem/memory_control.hh"
-#include "mem/functional_mem/physical_memory.hh"
+#include "mem/functional/memory_control.hh"
+#include "mem/functional/physical.hh"
#include "sim/builder.hh"
#include "sim/debug.hh"
#include "sim/eventq.hh"
// Sinic PCI Device
//
Base::Base(Params *p)
- : PciDev(p), rxEnable(false), txEnable(false),
- intrDelay(US2Ticks(p->intr_delay)),
- intrTick(0), cpuIntrEnable(false), cpuPendingIntr(false), intrEvent(0),
- interface(NULL)
+ : PciDev(p), rxEnable(false), txEnable(false), cycleTime(p->cycle_time),
+ intrDelay(p->intr_delay), intrTick(0), cpuIntrEnable(false),
+ cpuPendingIntr(false), intrEvent(0), interface(NULL)
{
}
{
reset();
- if (p->header_bus) {
- pioInterface = newPioInterface(p->name, p->hier, p->header_bus, this,
+ if (p->io_bus) {
+ pioInterface = newPioInterface(p->name, p->hier, p->io_bus, this,
&Device::cacheAccess);
- pioLatency = p->pio_latency * p->header_bus->clockRatio;
+ pioLatency = p->pio_latency * p->io_bus->clockRate;
if (p->payload_bus)
- dmaInterface = new DMAInterface<Bus>(p->name + ".dma",
- p->header_bus, p->payload_bus,
- 1);
+ dmaInterface = new DMAInterface<Bus>(p->name + ".dma", p->io_bus,
+ p->payload_bus, 1,
+ p->dma_no_allocate);
else
- dmaInterface = new DMAInterface<Bus>(p->name + ".dma",
- p->header_bus, p->header_bus,
- 1);
+ dmaInterface = new DMAInterface<Bus>(p->name + ".dma", p->io_bus,
+ p->io_bus, 1,
+ p->dma_no_allocate);
} else if (p->payload_bus) {
pioInterface = newPioInterface(p->name, p->hier, p->payload_bus, this,
&Device::cacheAccess);
- pioLatency = p->pio_latency * p->payload_bus->clockRatio;
+ pioLatency = p->pio_latency * p->payload_bus->clockRate;
dmaInterface = new DMAInterface<Bus>(p->name + ".dma", p->payload_bus,
- p->payload_bus, 1);
+ p->payload_bus, 1,
+ p->dma_no_allocate);
}
}
.prereq(rxBytes)
;
+ totBandwidth
+ .name(name() + ".totBandwidth")
+ .desc("Total Bandwidth (bits/s)")
+ .precision(0)
+ .prereq(totBytes)
+ ;
+
+ totPackets
+ .name(name() + ".totPackets")
+ .desc("Total Packets")
+ .precision(0)
+ .prereq(totBytes)
+ ;
+
+ totBytes
+ .name(name() + ".totBytes")
+ .desc("Total Bytes")
+ .precision(0)
+ .prereq(totBytes)
+ ;
+
+ totPacketRate
+ .name(name() + ".totPPS")
+ .desc("Total Tranmission Rate (packets/s)")
+ .precision(0)
+ .prereq(totBytes)
+ ;
+
txBytes
.name(name() + ".txBytes")
.desc("Bytes Transmitted")
txBandwidth = txBytes * Stats::constant(8) / simSeconds;
rxBandwidth = rxBytes * Stats::constant(8) / simSeconds;
+ totBandwidth = txBandwidth + rxBandwidth;
+ totBytes = txBytes + rxBytes;
+ totPackets = txPackets + rxPackets;
txPacketRate = txPackets / simSeconds;
rxPacketRate = rxPackets / simSeconds;
}
* This is to write to the PCI general configuration registers
*/
void
-Device::WriteConfig(int offset, int size, uint32_t data)
+Device::writeConfig(int offset, int size, const uint8_t *data)
{
switch (offset) {
case PCI0_BASE_ADDR0:
// Need to catch writes to BARs to update the PIO interface
- PciDev::WriteConfig(offset, size, data);
+ PciDev::writeConfig(offset, size, data);
if (BARAddrs[0] != 0) {
if (pioInterface)
pioInterface->addAddrRange(RangeSize(BARAddrs[0], BARSize[0]));
break;
default:
- PciDev::WriteConfig(offset, size, data);
+ PciDev::writeConfig(offset, size, data);
}
}
Fault
Device::read(MemReqPtr &req, uint8_t *data)
{
- assert(config.hdr.command & PCI_CMD_MSE);
+ assert(config.command & PCI_CMD_MSE);
//The mask is to give you only the offset into the device register file
Addr daddr = req->paddr & 0xfff;
Fault
Device::write(MemReqPtr &req, const uint8_t *data)
{
- assert(config.hdr.command & PCI_CMD_MSE);
+ assert(config.command & PCI_CMD_MSE);
Addr daddr = req->paddr & 0xfff;
if (Regs::regSize(daddr) == 0)
reschedule:
if (!txFifo.empty() && !txEvent.scheduled()) {
DPRINTF(Ethernet, "reschedule transmit\n");
- txEvent.schedule(curTick + 1000);
+ txEvent.schedule(curTick + retryTime);
}
}
DPRINTF(Ethernet, "transfer complete: data in txFifo...schedule xmit\n");
if (txEvent.scheduled())
- txEvent.reschedule(curTick + 1);
+ txEvent.reschedule(curTick + cycles(1));
else
- txEvent.schedule(curTick + 1);
+ txEvent.schedule(curTick + cycles(1));
}
bool
UNSERIALIZE_SCALAR(rxPacketExists);
rxPacket = 0;
if (rxPacketExists) {
- rxPacket = new PacketData;
+ rxPacket = new PacketData(16384);
rxPacket->unserialize("rxPacket", cp, section);
uint32_t rxPktBufPtr;
UNSERIALIZE_SCALAR(rxPktBufPtr);
UNSERIALIZE_SCALAR(txPacketExists);
txPacket = 0;
if (txPacketExists) {
- txPacket = new PacketData;
+ txPacket = new PacketData(16384);
txPacket->unserialize("txPacket", cp, section);
uint32_t txPktBufPtr;
UNSERIALIZE_SCALAR(txPktBufPtr);
BEGIN_DECLARE_SIM_OBJECT_PARAMS(Device)
+ Param<Addr> addr;
+ Param<Tick> cycle_time;
Param<Tick> tx_delay;
Param<Tick> rx_delay;
Param<Tick> intr_delay;
SimObjectParam<PhysicalMemory *> physmem;
Param<bool> rx_filter;
Param<string> hardware_address;
- SimObjectParam<Bus*> header_bus;
+ SimObjectParam<Bus*> io_bus;
SimObjectParam<Bus*> payload_bus;
SimObjectParam<HierParams *> hier;
Param<Tick> pio_latency;
Param<Tick> dma_read_factor;
Param<Tick> dma_write_delay;
Param<Tick> dma_write_factor;
+ Param<bool> dma_no_allocate;
END_DECLARE_SIM_OBJECT_PARAMS(Device)
BEGIN_INIT_SIM_OBJECT_PARAMS(Device)
+ INIT_PARAM(addr, "Device Address"),
+ INIT_PARAM(cycle_time, "State machine cycle time"),
INIT_PARAM_DFLT(tx_delay, "Transmit Delay", 1000),
INIT_PARAM_DFLT(rx_delay, "Receive Delay", 1000),
INIT_PARAM_DFLT(intr_delay, "Interrupt Delay in microseconds", 0),
INIT_PARAM(mmu, "Memory Controller"),
INIT_PARAM(physmem, "Physical Memory"),
INIT_PARAM_DFLT(rx_filter, "Enable Receive Filter", true),
- INIT_PARAM_DFLT(hardware_address, "Ethernet Hardware Address",
- "00:99:00:00:00:01"),
- INIT_PARAM_DFLT(header_bus, "The IO Bus to attach to for headers", NULL),
+ INIT_PARAM(hardware_address, "Ethernet Hardware Address"),
+ INIT_PARAM_DFLT(io_bus, "The IO Bus to attach to for headers", NULL),
INIT_PARAM_DFLT(payload_bus, "The IO Bus to attach to for payload", NULL),
INIT_PARAM_DFLT(hier, "Hierarchy global variables", &defaultHierParams),
INIT_PARAM_DFLT(pio_latency, "Programmed IO latency in bus cycles", 1),
INIT_PARAM_DFLT(dma_read_delay, "fixed delay for dma reads", 0),
INIT_PARAM_DFLT(dma_read_factor, "multiplier for dma reads", 0),
INIT_PARAM_DFLT(dma_write_delay, "fixed delay for dma writes", 0),
- INIT_PARAM_DFLT(dma_write_factor, "multiplier for dma writes", 0)
+ INIT_PARAM_DFLT(dma_write_factor, "multiplier for dma writes", 0),
+ INIT_PARAM_DFLT(dma_no_allocate, "Should we allocat on read in cache", true)
END_INIT_SIM_OBJECT_PARAMS(Device)
params->name = getInstanceName();
params->intr_delay = intr_delay;
params->physmem = physmem;
+ params->cycle_time = cycle_time;
params->tx_delay = tx_delay;
params->rx_delay = rx_delay;
params->mmu = mmu;
params->hier = hier;
- params->header_bus = header_bus;
+ params->io_bus = io_bus;
params->payload_bus = payload_bus;
params->pio_latency = pio_latency;
params->configSpace = configspace;
params->dma_read_factor = dma_read_factor;
params->dma_write_delay = dma_write_delay;
params->dma_write_factor = dma_write_factor;
+ params->dma_no_allocate = dma_no_allocate;
return new Device(params);
}
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