p->dma_no_allocate);
} else if (p->payload_bus)
panic("must define a header bus if defining a payload bus");
-
- pioDelayWrite = p->pio_delay_write && pioInterface;
}
Device::~Device()
void
Device::prepareWrite(int cpu, int index)
{
- if (cpu >= writeQueue.size())
- writeQueue.resize(cpu + 1);
-
prepareIO(cpu, index);
}
/**
* I/O read of device register
*/
-Fault *
+Fault
Device::read(MemReqPtr &req, uint8_t *data)
{
assert(config.command & PCI_CMD_MSE);
- Fault * fault = readBar(req, data);
+ Fault fault = readBar(req, data);
if (fault == MachineCheckFault) {
panic("address does not map to a BAR pa=%#x va=%#x size=%d",
return fault;
}
-Fault *
+Fault
Device::readBar0(MemReqPtr &req, Addr daddr, uint8_t *data)
{
int cpu = (req->xc->regs.ipr[TheISA::IPR_PALtemp16] >> 8) & 0xff;
/**
* IPR read of device register
*/
-Fault *
+Fault
Device::iprRead(Addr daddr, int cpu, uint64_t &result)
{
if (!regValid(daddr))
/**
* I/O write of device register
*/
-Fault *
+Fault
Device::write(MemReqPtr &req, const uint8_t *data)
{
assert(config.command & PCI_CMD_MSE);
- Fault * fault = writeBar(req, data);
+ Fault fault = writeBar(req, data);
if (fault == MachineCheckFault) {
panic("address does not map to a BAR pa=%#x va=%#x size=%d",
return fault;
}
-Fault *
+Fault
Device::writeBar0(MemReqPtr &req, Addr daddr, const uint8_t *data)
{
int cpu = (req->xc->regs.ipr[TheISA::IPR_PALtemp16] >> 8) & 0xff;
uint32_t reg32 = *(uint32_t *)data;
uint64_t reg64 = *(uint64_t *)data;
+ VirtualReg &vnic = virtualRegs[index];
+
DPRINTF(EthernetPIO,
"write %s: cpu=%d val=%#x da=%#x pa=%#x va=%#x size=%d\n",
info.name, cpu, info.size == 4 ? reg32 : reg64, daddr,
prepareWrite(cpu, index);
- if (pioDelayWrite)
- writeQueue[cpu].push_back(RegWriteData(daddr, reg64));
-
- if (!pioDelayWrite || !info.delay_write)
- regWrite(daddr, cpu, data);
-
- return NoFault;
-}
-
-void
-Device::regWrite(Addr daddr, int cpu, const uint8_t *data)
-{
- Addr index = daddr >> Regs::VirtualShift;
- Addr raddr = daddr & Regs::VirtualMask;
-
- uint32_t reg32 = *(uint32_t *)data;
- uint64_t reg64 = *(uint64_t *)data;
- VirtualReg &vnic = virtualRegs[index];
-
switch (raddr) {
case Regs::Config:
changeConfig(reg32);
}
break;
}
+
+ return NoFault;
}
void
DPRINTF(EthernetPIO, "timing %s to paddr=%#x bar=%d daddr=%#x\n",
req->cmd.toString(), req->paddr, bar, daddr);
- if (!pioDelayWrite || !req->cmd.isWrite())
- return curTick + pioLatency;
-
- if (bar == 0) {
- int cpu = (req->xc->regs.ipr[TheISA::IPR_PALtemp16] >> 8) & 0xff;
- std::list<RegWriteData> &wq = writeQueue[cpu];
- if (wq.empty())
- panic("WriteQueue for cpu %d empty timing daddr=%#x", cpu, daddr);
-
- const RegWriteData &data = wq.front();
- if (data.daddr != daddr)
- panic("read mismatch on cpu %d, daddr functional=%#x timing=%#x",
- cpu, data.daddr, daddr);
-
- const Regs::Info &info = regInfo(data.daddr);
- if (info.delay_write)
- regWrite(daddr, cpu, (uint8_t *)&data.value);
-
- wq.pop_front();
- }
-
return curTick + pioLatency;
}
Param<Tick> dma_write_factor;
Param<bool> dma_no_allocate;
Param<Tick> pio_latency;
- Param<bool> pio_delay_write;
Param<Tick> intr_delay;
Param<Tick> rx_delay;
INIT_PARAM(dma_write_factor, "multiplier for dma writes"),
INIT_PARAM(dma_no_allocate, "Should we allocat on read in cache"),
INIT_PARAM(pio_latency, "Programmed IO latency in bus cycles"),
- INIT_PARAM(pio_delay_write, ""),
INIT_PARAM(intr_delay, "Interrupt Delay"),
INIT_PARAM(rx_delay, "Receive Delay"),
params->dma_write_factor = dma_write_factor;
params->dma_no_allocate = dma_no_allocate;
params->pio_latency = pio_latency;
- params->pio_delay_write = pio_delay_write;
params->intr_delay = intr_delay;
params->tx_delay = tx_delay;