/*
- * Copyright (c) 2003 The Regents of The University of Michigan
+ * Copyright (c) 2004 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
+/**
+ * @file
+ * Declaration of top level class for the Tsunami chipset. This class just
+ * retains pointers to all its children so the children can communicate.
+ */
+
#ifndef __TSUNAMI_HH__
#define __TSUNAMI_HH__
-#include "sim/sim_object.hh"
+#include "dev/platform.hh"
-class IntrControl;
-class ConsoleListener;
-class SimConsole;
-class ScsiController;
+class IdeController;
class TlaserClock;
-class EtherDev;
+class NSGigE;
class TsunamiCChip;
+class TsunamiPChip;
+class TsunamiIO;
+class PciConfigAll;
+class System;
+
+/**
+ * Top level class for Tsunami Chipset emulation.
+ * This structure just contains pointers to all the
+ * children so the children can commnicate to do the
+ * read work
+ */
-class Tsunami : public SimObject
+class Tsunami : public Platform
{
public:
+ /** Max number of CPUs in a Tsunami */
static const int Max_CPUs = 4;
- IntrControl *intctrl;
-// ConsoleListener *listener;
- SimConsole *cons;
+ /** Pointer to the system */
+ System *system;
- ScsiController *scsi;
- EtherDev *ethernet;
+ /** Pointer to the TsunamiIO device which has the RTC */
+ TsunamiIO *io;
- TlaserClock *clock;
+ /** Pointer to the Tsunami CChip.
+ * The chip contains some configuration information and
+ * all the interrupt mask and status registers
+ */
TsunamiCChip *cchip;
+ /** Pointer to the Tsunami PChip.
+ * The pchip is the interface to the PCI bus, in our case
+ * it does not have to do much.
+ */
+ TsunamiPChip *pchip;
+
int intr_sum_type[Tsunami::Max_CPUs];
int ipi_pending[Tsunami::Max_CPUs];
- int interrupt_frequency;
-
public:
- Tsunami(const std::string &name, ScsiController *scsi,
- EtherDev *ethernet, TlaserClock *clock, TsunamiCChip *tc,
- SimConsole *, IntrControl *intctrl,
- int intrFreq);
+ /**
+ * Constructor for the Tsunami Class.
+ * @param name name of the object
+ * @param con pointer to the console
+ * @param intrcontrol pointer to the interrupt controller
+ * @param intrFreq frequency that interrupts happen
+ */
+ Tsunami(const std::string &name, System *s, IntrControl *intctrl,
+ PciConfigAll *pci, int intrFreq);
+
+ /**
+ * Return the interrupting frequency to AlphaAccess
+ * @return frequency of RTC interrupts
+ */
+ virtual Tick intrFrequency();
+ /**
+ * Cause the cpu to post a serial interrupt to the CPU.
+ */
+ virtual void postConsoleInt();
+
+ /**
+ * Clear a posted CPU interrupt (id=55)
+ */
+ virtual void clearConsoleInt();
+
+ /**
+ * Cause the chipset to post a cpi interrupt to the CPU.
+ */
+ virtual void postPciInt(int line);
+
+ /**
+ * Clear a posted PCI->CPU interrupt
+ */
+ virtual void clearPciInt(int line);
+
+ /**
+ * Serialize this object to the given output stream.
+ * @param os The stream to serialize to.
+ */
virtual void serialize(std::ostream &os);
+
+ /**
+ * Reconstruct the state of this object from a checkpoint.
+ * @param cp The checkpoint use.
+ * @param section The section name of this object
+ */
virtual void unserialize(Checkpoint *cp, const std::string §ion);
};