/*
- * Copyright (c) 2003 The Regents of The University of Michigan
+ * Copyright (c) 2004-2005 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* retains pointers to all its children so the children can communicate.
*/
-#ifndef __TSUNAMI_HH__
-#define __TSUNAMI_HH__
+#ifndef __DEV_TSUNAMI_HH__
+#define __DEV_TSUNAMI_HH__
-#include "sim/sim_object.hh"
+#include "dev/platform.hh"
-class IntrControl;
-class ConsoleListener;
-class SimConsole;
-class AdaptecController;
+class IdeController;
class TlaserClock;
-class EtherDev;
+class NSGigE;
class TsunamiCChip;
class TsunamiPChip;
-class PCIConfigAll;
+class TsunamiIO;
+class PciConfigAll;
+class System;
/**
* Top level class for Tsunami Chipset emulation.
* read work
*/
-class Tsunami : public SimObject
+class Tsunami : public Platform
{
public:
-
/** Max number of CPUs in a Tsunami */
- static const int Max_CPUs = 4;
+ static const int Max_CPUs = 64;
- /** Pointer to the interrupt controller (used to post and ack interrupts on the CPU) */
- IntrControl *intrctrl;
- /** Pointer to the UART emulation code */
- SimConsole *cons;
+ /** Pointer to the system */
+ System *system;
- /** Pointer to the SCSI controller device */
- AdaptecController *scsi;
- /** Pointer to the ethernet controller device */
- EtherDev *ethernet;
+ /** Pointer to the TsunamiIO device which has the RTC */
+ TsunamiIO *io;
/** Pointer to the Tsunami CChip.
- * The chip contains some configuration information and
- * all the interrupt mask and status registers
- */
+ * The chip contains some configuration information and
+ * all the interrupt mask and status registers
+ */
TsunamiCChip *cchip;
/** Pointer to the Tsunami PChip.
- * The pchip is the interface to the PCI bus, in our case
- * it does not have to do much.
- */
+ * The pchip is the interface to the PCI bus, in our case
+ * it does not have to do much.
+ */
TsunamiPChip *pchip;
- /** Pointer to the PCI Config Space
- * The config space in Tsunami all needs to return
- * -1 if a device is not there.
- */
- PCIConfigAll *pciconfig;
-
int intr_sum_type[Tsunami::Max_CPUs];
int ipi_pending[Tsunami::Max_CPUs];
- int interrupt_frequency;
-
public:
/**
- * Constructor for the Tsunami Class.
- * @param name name of the object
- * @param con pointer to the console
- * @param intrcontrol pointer to the interrupt controller
- * @param intrFreq frequency that interrupts happen
- */
- Tsunami(const std::string &name, EtherDev *ethernet, SimConsole *con,
- IntrControl *intctrl, int intrFreq);
+ * Constructor for the Tsunami Class.
+ * @param name name of the object
+ * @param intrctrl pointer to the interrupt controller
+ */
+ Tsunami(const std::string &name, System *s, IntrControl *intctrl,
+ PciConfigAll *pci);
+
+ /**
+ * Return the interrupting frequency to AlphaAccess
+ * @return frequency of RTC interrupts
+ */
+ virtual Tick intrFrequency();
+
+ /**
+ * Cause the cpu to post a serial interrupt to the CPU.
+ */
+ virtual void postConsoleInt();
+
+ /**
+ * Clear a posted CPU interrupt (id=55)
+ */
+ virtual void clearConsoleInt();
+ /**
+ * Cause the chipset to post a cpi interrupt to the CPU.
+ */
+ virtual void postPciInt(int line);
+
+ /**
+ * Clear a posted PCI->CPU interrupt
+ */
+ virtual void clearPciInt(int line);
+
+ virtual Addr pciToDma(Addr pciAddr) const;
+
+ /**
+ * Serialize this object to the given output stream.
+ * @param os The stream to serialize to.
+ */
virtual void serialize(std::ostream &os);
+
+ /**
+ * Reconstruct the state of this object from a checkpoint.
+ * @param cp The checkpoint use.
+ * @param section The section name of this object
+ */
virtual void unserialize(Checkpoint *cp, const std::string §ion);
};
-#endif // __TSUNAMI_HH__
+#endif // __DEV_TSUNAMI_HH__