/*
- * Copyright (c) 2004 The Regents of The University of Michigan
+ * Copyright (c) 2004-2005 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-/* @file
+/** @file
* Emulation of the Tsunami CChip CSRs
*/
#include "mem/bus/bus.hh"
#include "mem/bus/pio_interface.hh"
#include "mem/bus/pio_interface_impl.hh"
-#include "mem/functional_mem/memory_control.hh"
+#include "mem/functional/memory_control.hh"
#include "cpu/intr_control.hh"
#include "sim/builder.hh"
#include "sim/system.hh"
mmu->add_child(this, RangeSize(addr, size));
if (bus) {
- pioInterface = newPioInterface(name, hier, bus, this,
+ pioInterface = newPioInterface(name + ".pio", hier, bus, this,
&TsunamiCChip::cacheAccess);
pioInterface->addAddrRange(RangeSize(addr, size));
- pioLatency = pio_latency * bus->clockRatio;
+ pioLatency = pio_latency * bus->clockRate;
}
drir = 0;
break;
case sizeof(uint32_t):
+ if (regnum == TSDEV_CC_DRIR) {
+ warn("accessing DRIR with 32 bit read, "
+ "hopefully your just reading this for timing");
+ *(uint32_t*)data = drir;
+ } else
+ panic("invalid access size(?) for tsunami register!\n");
+ return No_Fault;
case sizeof(uint16_t):
case sizeof(uint8_t):
default: