Better handling of latency/frequency parameter types

[gem5.git] / dev / tsunami_cchip.hh

diff --git a/dev/tsunami_cchip.hh b/dev/tsunami_cchip.hh
index c1c196d184687be245555d68d03e6e42363356c6..05fafa7825077e0925f4ac7574c2bcfb726cdf4a 100644 (file)
--- a/dev/tsunami_cchip.hh
+++ b/dev/tsunami_cchip.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2003 The Regents of The University of Michigan
+ * Copyright (c) 2004 The Regents of The University of Michigan
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -27,44 +27,147 @@
  */
 
 /* @file
- * Turbolaser system bus node (processor, memory, or IO)
+ * Emulation of the Tsunami CChip CSRs
  */
 
 #ifndef __TSUNAMI_CCHIP_HH__
 #define __TSUNAMI_CCHIP_HH__
 
-#include "mem/functional_mem/mmap_device.hh"
 #include "dev/tsunami.hh"
+#include "base/range.hh"
+#include "dev/io_device.hh"
 
 /*
  * Tsunami CChip
  */
-class TsunamiCChip : public MmapDevice
+class TsunamiCChip : public PioDevice
 {
-  public:
+  private:
+    /** The base address of this device */
+    Addr addr;
+
+    /** The size of mappad from the above address */
+    static const Addr size = 0xfffffff;
 
   protected:
+    /**
+     * pointer to the tsunami object.
+     * This is our access to all the other tsunami
+     * devices.
+     */
     Tsunami *tsunami;
+
+    /**
+     * The dims are device interrupt mask registers.
+     * One exists for each CPU, the DRIR X DIM = DIR
+     */
     uint64_t dim[Tsunami::Max_CPUs];
+
+    /**
+     * The dirs are device interrupt registers.
+     * One exists for each CPU, the DRIR X DIM = DIR
+     */
     uint64_t dir[Tsunami::Max_CPUs];
-    bool dirInterrupting[Tsunami::Max_CPUs];
+
+    /**
+     * This register contains bits for each PCI interrupt
+     * that can occur.
+     */
     uint64_t drir;
 
+    /** Indicator of which CPUs have an IPI interrupt */
+    uint64_t ipint;
+
+    /** Indicator of which CPUs have an RTC interrupt */
+    uint64_t itint;
+
   public:
-    TsunamiCChip(const std::string &name, Tsunami *t,
-               Addr addr, Addr mask, MemoryController *mmu);
+    /**
+     * Initialize the Tsunami CChip by setting all of the
+     * device register to 0.
+     * @param name name of this device.
+     * @param t pointer back to the Tsunami object that we belong to.
+     * @param a address we are mapped at.
+     * @param mmu pointer to the memory controller that sends us events.
+     * @param hier object to store parameters universal the device hierarchy
+     * @param bus The bus that this device is attached to
+     */
+    TsunamiCChip(const std::string &name, Tsunami *t, Addr a,
+                 MemoryController *mmu, HierParams *hier, Bus *bus,
+                 Tick pio_latency);
+
+    /**
+      * Process a read to the CChip.
+      * @param req Contains the address to read from.
+      * @param data A pointer to write the read data to.
+      * @return The fault condition of the access.
+      */
+    virtual Fault read(MemReqPtr &req, uint8_t *data);
 
-    virtual Fault read(MemReqPtr req, uint8_t *data);
-    virtual Fault write(MemReqPtr req, const uint8_t *data);
 
-    void postDRIR(uint64_t bitvector);
-    void clearDRIR(uint64_t bitvector);
+    /**
+      * Process a write to the CChip.
+      * @param req Contains the address to write to.
+      * @param data The data to write.
+      * @return The fault condition of the access.
+      */
+    virtual Fault write(MemReqPtr &req, const uint8_t *data);
 
+    /**
+     * post an RTC interrupt to the CPU
+     */
+    void postRTC();
+
+    /**
+     * post an interrupt to the CPU.
+     * @param interrupt the interrupt number to post (0-64)
+     */
+    void postDRIR(uint32_t interrupt);
+
+    /**
+     * clear an interrupt previously posted to the CPU.
+     * @param interrupt the interrupt number to post (0-64)
+     */
+    void clearDRIR(uint32_t interrupt);
+
+    /**
+     * post an ipi interrupt  to the CPU.
+     * @param ipintr the cpu number to clear(bitvector)
+     */
+    void clearIPI(uint64_t ipintr);
+
+    /**
+     * clear a timer interrupt previously posted to the CPU.
+     * @param interrupt the cpu number to clear(bitvector)
+     */
+    void clearITI(uint64_t itintr);
+
+    /**
+     * request an interrupt be posted to the CPU.
+     * @param ipreq the cpu number to interrupt(bitvector)
+     */
+    void reqIPI(uint64_t ipreq);
+
+
+    /**
+     * Serialize this object to the given output stream.
+     * @param os The stream to serialize to.
+     */
     virtual void serialize(std::ostream &os);
+
+    /**
+     * Reconstruct the state of this object from a checkpoint.
+     * @param cp The checkpoint use.
+     * @param section The section name of this object
+     */
     virtual void unserialize(Checkpoint *cp, const std::string &section);
 
-    uint64_t misc;
-    bool RTCInterrupting;
+    /**
+     * Return how long this access will take.
+     * @param req the memory request to calcuate
+     * @return Tick when the request is done
+     */
+    Tick cacheAccess(MemReqPtr &req);
 };
 
 #endif // __TSUNAMI_CCHIP_HH__