* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-/* @file
+/** @file
* Emulation of the Tsunami CChip CSRs
*/
#include "base/range.hh"
#include "dev/io_device.hh"
-/*
- * Tsunami CChip
+/**
+ * Tsunami CChip CSR Emulation. This device includes all the interrupt
+ * handling code for the chipset.
*/
class TsunamiCChip : public PioDevice
{
Addr addr;
/** The size of mappad from the above address */
- static const Addr size = 0xfff;
+ static const Addr size = 0xfffffff;
protected:
/**
* One exists for each CPU, the DRIR X DIM = DIR
*/
uint64_t dir[Tsunami::Max_CPUs];
- bool dirInterrupting[Tsunami::Max_CPUs];
/**
* This register contains bits for each PCI interrupt
*/
uint64_t drir;
- /**
- * The MISC register contains the CPU we are currently on
- * as well as bits to ack RTC and IPI interrupts.
- */
- uint64_t misc;
-
- /** Count of the number of pending IPIs on a CPU */
- uint64_t ipiInterrupting[Tsunami::Max_CPUs];
+ /** Indicator of which CPUs have an IPI interrupt */
+ uint64_t ipint;
- /** Indicator of which CPUs have had an RTC interrupt */
- bool RTCInterrupting[Tsunami::Max_CPUs];
+ /** Indicator of which CPUs have an RTC interrupt */
+ uint64_t itint;
public:
/**
*/
void clearDRIR(uint32_t interrupt);
+ /**
+ * post an ipi interrupt to the CPU.
+ * @param ipintr the cpu number to clear(bitvector)
+ */
+ void clearIPI(uint64_t ipintr);
+
+ /**
+ * clear a timer interrupt previously posted to the CPU.
+ * @param interrupt the cpu number to clear(bitvector)
+ */
+ void clearITI(uint64_t itintr);
+
+ /**
+ * request an interrupt be posted to the CPU.
+ * @param ipreq the cpu number to interrupt(bitvector)
+ */
+ void reqIPI(uint64_t ipreq);
+
+
/**
* Serialize this object to the given output stream.
* @param os The stream to serialize to.