Fix doxgyen comments

[gem5.git] / dev / tsunami_cchip.hh

diff --git a/dev/tsunami_cchip.hh b/dev/tsunami_cchip.hh
index a358c98ba98ae32cd25325c0b210e48be927a5e4..d33905bc0254172dd16f8f70ca0a523cecedf3c4 100644 (file)
--- a/dev/tsunami_cchip.hh
+++ b/dev/tsunami_cchip.hh
@@ -26,7 +26,7 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-/* @file
+/** @file
  * Emulation of the Tsunami CChip CSRs
  */
 
@@ -37,8 +37,9 @@
 #include "base/range.hh"
 #include "dev/io_device.hh"
 
-/*
- * Tsunami CChip
+/**
+ * Tsunami CChip CSR Emulation. This device includes all the interrupt
+ * handling code for the chipset.
  */
 class TsunamiCChip : public PioDevice
 {
@@ -47,7 +48,7 @@ class TsunamiCChip : public PioDevice
     Addr addr;
 
     /** The size of mappad from the above address */
-    static const Addr size = 0xfff;
+    static const Addr size = 0xfffffff;
 
   protected:
     /**
@@ -68,7 +69,6 @@ class TsunamiCChip : public PioDevice
      * One exists for each CPU, the DRIR X DIM = DIR
      */
     uint64_t dir[Tsunami::Max_CPUs];
-    bool dirInterrupting[Tsunami::Max_CPUs];
 
     /**
      * This register contains bits for each PCI interrupt
@@ -76,17 +76,11 @@ class TsunamiCChip : public PioDevice
      */
     uint64_t drir;
 
-    /**
-     * The MISC register contains the CPU we are currently on
-     * as well as bits to ack RTC and IPI interrupts.
-     */
-    uint64_t misc;
-
-    /** Count of the number of pending IPIs on a CPU */
-    uint64_t ipiInterrupting[Tsunami::Max_CPUs];
+    /** Indicator of which CPUs have an IPI interrupt */
+    uint64_t ipint;
 
-    /** Indicator of which CPUs have had an RTC interrupt */
-    bool RTCInterrupting[Tsunami::Max_CPUs];
+    /** Indicator of which CPUs have an RTC interrupt */
+    uint64_t itint;
 
   public:
     /**
@@ -100,7 +94,8 @@ class TsunamiCChip : public PioDevice
      * @param bus The bus that this device is attached to
      */
     TsunamiCChip(const std::string &name, Tsunami *t, Addr a,
-                 MemoryController *mmu, HierParams *hier, Bus *bus);
+                 MemoryController *mmu, HierParams *hier, Bus *bus,
+                 Tick pio_latency);
 
     /**
       * Process a read to the CChip.
@@ -136,6 +131,25 @@ class TsunamiCChip : public PioDevice
      */
     void clearDRIR(uint32_t interrupt);
 
+    /**
+     * post an ipi interrupt  to the CPU.
+     * @param ipintr the cpu number to clear(bitvector)
+     */
+    void clearIPI(uint64_t ipintr);
+
+    /**
+     * clear a timer interrupt previously posted to the CPU.
+     * @param interrupt the cpu number to clear(bitvector)
+     */
+    void clearITI(uint64_t itintr);
+
+    /**
+     * request an interrupt be posted to the CPU.
+     * @param ipreq the cpu number to interrupt(bitvector)
+     */
+    void reqIPI(uint64_t ipreq);
+
+
     /**
      * Serialize this object to the given output stream.
      * @param os The stream to serialize to.