#include "base/trace.hh"
#include "dev/tsunami_io.hh"
#include "dev/tsunami.hh"
+#include "dev/pitreg.h"
#include "mem/bus/bus.hh"
#include "mem/bus/pio_interface.hh"
#include "mem/bus/pio_interface_impl.hh"
using namespace std;
-#define UNIX_YEAR_OFFSET 52
-
-struct tm TsunamiIO::tm = { 0 };
-
-// Timer Event for Periodic interrupt of RTC
-TsunamiIO::RTCEvent::RTCEvent(Tsunami* t, Tick i)
- : Event(&mainEventQueue), tsunami(t), interval(i)
+TsunamiIO::RTC::RTC(const string &name, Tsunami* t, Tick i)
+ : _name(name), event(t, i), addr(0)
{
- DPRINTF(MC146818, "RTC Event Initilizing\n");
- schedule(curTick + interval);
+ memset(clock_data, 0, sizeof(clock_data));
+ stat_regA = RTCA_32768HZ | RTCA_1024HZ;
+ stat_regB = RTCB_PRDC_IE |RTCB_BIN | RTCB_24HR;
}
void
-TsunamiIO::RTCEvent::process()
+TsunamiIO::RTC::set_time(time_t t)
{
- static int intr_count = 0;
- DPRINTF(MC146818, "RTC Timer Interrupt\n");
- schedule(curTick + interval);
- //Actually interrupt the processor here
- tsunami->cchip->postRTC();
- if (intr_count == 1023)
- tm.tm_sec = (tm.tm_sec + 1) % 60;
+ struct tm tm;
+ gmtime_r(&t, &tm);
- intr_count = (intr_count + 1) % 1024;
+ sec = tm.tm_sec;
+ min = tm.tm_min;
+ hour = tm.tm_hour;
+ wday = tm.tm_wday + 1;
+ mday = tm.tm_mday;
+ mon = tm.tm_mon + 1;
+ year = tm.tm_year;
+ DPRINTFN("Real-time clock set to %s", asctime(&tm));
}
-const char *
-TsunamiIO::RTCEvent::description()
+void
+TsunamiIO::RTC::writeAddr(const uint8_t *data)
{
- return "tsunami RTC interrupt";
+ if (*data <= RTC_STAT_REGD)
+ addr = *data;
+ else
+ panic("RTC addresses over 0xD are not implemented.\n");
}
void
-TsunamiIO::RTCEvent::serialize(std::ostream &os)
+TsunamiIO::RTC::writeData(const uint8_t *data)
{
- Tick time = when();
- SERIALIZE_SCALAR(time);
+ if (addr < RTC_STAT_REGA)
+ clock_data[addr] = *data;
+ else {
+ switch (addr) {
+ case RTC_STAT_REGA:
+ if (*data != (RTCA_32768HZ | RTCA_1024HZ))
+ panic("Unimplemented RTC register A value write!\n");
+ stat_regA = *data;
+ break;
+ case RTC_STAT_REGB:
+ if ((*data & ~(RTCB_PRDC_IE | RTCB_SQWE)) != (RTCB_BIN | RTCB_24HR))
+ panic("Write to RTC reg B bits that are not implemented!\n");
+
+ if (*data & RTCB_PRDC_IE) {
+ if (!event.scheduled())
+ event.scheduleIntr();
+ } else {
+ if (event.scheduled())
+ event.deschedule();
+ }
+ stat_regB = *data;
+ break;
+ case RTC_STAT_REGC:
+ case RTC_STAT_REGD:
+ panic("RTC status registers C and D are not implemented.\n");
+ break;
+ }
+ }
}
void
-TsunamiIO::RTCEvent::unserialize(Checkpoint *cp, const std::string §ion)
+TsunamiIO::RTC::readData(uint8_t *data)
{
- Tick time;
- UNSERIALIZE_SCALAR(time);
- reschedule(time);
+ if (addr < RTC_STAT_REGA)
+ *data = clock_data[addr];
+ else {
+ switch (addr) {
+ case RTC_STAT_REGA:
+ // toggle UIP bit for linux
+ stat_regA ^= RTCA_UIP;
+ *data = stat_regA;
+ break;
+ case RTC_STAT_REGB:
+ *data = stat_regB;
+ break;
+ case RTC_STAT_REGC:
+ case RTC_STAT_REGD:
+ *data = 0x00;
+ break;
+ }
+ }
}
+void
+TsunamiIO::RTC::serialize(const string &base, ostream &os)
+{
+ paramOut(os, base + ".addr", addr);
+ arrayParamOut(os, base + ".clock_data", clock_data, sizeof(clock_data));
+ paramOut(os, base + ".stat_regA", stat_regA);
+ paramOut(os, base + ".stat_regB", stat_regB);
+}
-// Timer Event for PIT Timers
-TsunamiIO::ClockEvent::ClockEvent()
- : Event(&mainEventQueue)
+void
+TsunamiIO::RTC::unserialize(const string &base, Checkpoint *cp,
+ const string §ion)
{
- /* This is the PIT Tick Rate. A constant for the 8254 timer. The
- * Tsunami platform has one of these cycle counters on the Cypress
- * South Bridge and it is used by linux for estimating the cycle
- * frequency of the machine it is running on. --Ali
- */
- interval = (Tick)(Clock::Float::s / 1193180.0);
+ paramIn(cp, section, base + ".addr", addr);
+ arrayParamIn(cp, section, base + ".clock_data", clock_data,
+ sizeof(clock_data));
+ paramIn(cp, section, base + ".stat_regA", stat_regA);
+ paramIn(cp, section, base + ".stat_regB", stat_regB);
+
+ // We're not unserializing the event here, but we need to
+ // rescehedule the event since curTick was moved forward by the
+ // checkpoint
+ event.reschedule(curTick + event.interval);
+}
- DPRINTF(Tsunami, "Clock Event Initilizing\n");
- mode = 0;
+TsunamiIO::RTC::RTCEvent::RTCEvent(Tsunami*t, Tick i)
+ : Event(&mainEventQueue), tsunami(t), interval(i)
+{
+ DPRINTF(MC146818, "RTC Event Initilizing\n");
+ schedule(curTick + interval);
+}
- current_count.whole = 0;
- latched_count.whole = 0;
- latch_on = false;
- read_msb = false;
+void
+TsunamiIO::RTC::RTCEvent::scheduleIntr()
+{
+ schedule(curTick + interval);
}
void
-TsunamiIO::ClockEvent::process()
+TsunamiIO::RTC::RTCEvent::process()
{
- DPRINTF(Tsunami, "Timer Interrupt\n");
- if (mode == 0)
- status = 0x20; // set bit that linux is looking for
- else
- schedule(curTick + interval);
+ DPRINTF(MC146818, "RTC Timer Interrupt\n");
+ schedule(curTick + interval);
+ //Actually interrupt the processor here
+ tsunami->cchip->postRTC();
+}
- current_count.whole--; //decrement count
+const char *
+TsunamiIO::RTC::RTCEvent::description()
+{
+ return "tsunami RTC interrupt";
+}
+
+TsunamiIO::PITimer::PITimer(const string &name)
+ : _name(name), counter0(name + ".counter0"), counter1(name + ".counter1"),
+ counter2(name + ".counter2")
+{
+ counter[0] = &counter0;
+ counter[1] = &counter0;
+ counter[2] = &counter0;
}
void
-TsunamiIO::ClockEvent::Program(int count)
+TsunamiIO::PITimer::writeControl(const uint8_t *data)
{
- DPRINTF(Tsunami, "Timer set to curTick + %d\n", count * interval);
- schedule(curTick + count * interval);
- status = 0;
+ int rw;
+ int sel;
+
+ sel = GET_CTRL_SEL(*data);
+
+ if (sel == PIT_READ_BACK)
+ panic("PITimer Read-Back Command is not implemented.\n");
+
+ rw = GET_CTRL_RW(*data);
- current_count.whole = count;
+ if (rw == PIT_RW_LATCH_COMMAND)
+ counter[sel]->latchCount();
+ else {
+ counter[sel]->setRW(rw);
+ counter[sel]->setMode(GET_CTRL_MODE(*data));
+ counter[sel]->setBCD(GET_CTRL_BCD(*data));
+ }
}
-const char *
-TsunamiIO::ClockEvent::description()
+void
+TsunamiIO::PITimer::serialize(const string &base, ostream &os)
{
- return "tsunami 8254 Interval timer";
+ // serialize the counters
+ counter0.serialize(base + ".counter0", os);
+ counter1.serialize(base + ".counter1", os);
+ counter2.serialize(base + ".counter2", os);
}
void
-TsunamiIO::ClockEvent::ChangeMode(uint8_t md)
+TsunamiIO::PITimer::unserialize(const string &base, Checkpoint *cp,
+ const string §ion)
{
- mode = md;
+ // unserialze the counters
+ counter0.unserialize(base + ".counter0", cp, section);
+ counter1.unserialize(base + ".counter1", cp, section);
+ counter2.unserialize(base + ".counter2", cp, section);
}
-uint8_t
-TsunamiIO::ClockEvent::Status()
+TsunamiIO::PITimer::Counter::Counter(const string &name)
+ : _name(name), event(this), count(0), latched_count(0), period(0),
+ mode(0), output_high(false), latch_on(false), read_byte(LSB),
+ write_byte(LSB)
{
- return status;
+
}
void
-TsunamiIO::ClockEvent::LatchCount()
+TsunamiIO::PITimer::Counter::latchCount()
{
+ // behave like a real latch
if(!latch_on) {
latch_on = true;
- read_msb = false;
- latched_count.whole = current_count.whole;
+ read_byte = LSB;
+ latched_count = count;
}
}
-uint8_t
-TsunamiIO::ClockEvent::Read()
+void
+TsunamiIO::PITimer::Counter::read(uint8_t *data)
{
- if(latch_on) {
- if(!read_msb) {
- read_msb = true;
- return latched_count.half.lsb;
- } else {
+ if (latch_on) {
+ switch (read_byte) {
+ case LSB:
+ read_byte = MSB;
+ *data = (uint8_t)latched_count;
+ break;
+ case MSB:
+ read_byte = LSB;
latch_on = false;
- return latched_count.half.msb;
+ *data = latched_count >> 8;
+ break;
}
} else {
- if(!read_msb) {
- read_msb = true;
- return current_count.half.lsb;
- } else {
- return current_count.half.msb;
+ switch (read_byte) {
+ case LSB:
+ read_byte = MSB;
+ *data = (uint8_t)count;
+ break;
+ case MSB:
+ read_byte = LSB;
+ *data = count >> 8;
+ break;
+ }
+ }
+}
+
+void
+TsunamiIO::PITimer::Counter::write(const uint8_t *data)
+{
+ switch (write_byte) {
+ case LSB:
+ count = (count & 0xFF00) | *data;
+
+ if (event.scheduled())
+ event.deschedule();
+ output_high = false;
+ write_byte = MSB;
+ break;
+
+ case MSB:
+ count = (count & 0x00FF) | (*data << 8);
+ period = count;
+
+ if (period > 0) {
+ DPRINTF(Tsunami, "Timer set to curTick + %d\n",
+ count * event.interval);
+ event.schedule(curTick + count * event.interval);
}
+ write_byte = LSB;
+ break;
}
}
+void
+TsunamiIO::PITimer::Counter::setRW(int rw_val)
+{
+ if (rw_val != PIT_RW_16BIT)
+ panic("Only LSB/MSB read/write is implemented.\n");
+}
+
+void
+TsunamiIO::PITimer::Counter::setMode(int mode_val)
+{
+ if(mode_val != PIT_MODE_INTTC && mode_val != PIT_MODE_RATEGEN &&
+ mode_val != PIT_MODE_SQWAVE)
+ panic("PIT mode %#x is not implemented: \n", mode_val);
+
+ mode = mode_val;
+}
+
+void
+TsunamiIO::PITimer::Counter::setBCD(int bcd_val)
+{
+ if (bcd_val != PIT_BCD_FALSE)
+ panic("PITimer does not implement BCD counts.\n");
+}
+
+bool
+TsunamiIO::PITimer::Counter::outputHigh()
+{
+ return output_high;
+}
void
-TsunamiIO::ClockEvent::serialize(std::ostream &os)
+TsunamiIO::PITimer::Counter::serialize(const string &base, ostream &os)
{
- Tick time = scheduled() ? when() : 0;
- SERIALIZE_SCALAR(time);
- SERIALIZE_SCALAR(status);
- SERIALIZE_SCALAR(mode);
- SERIALIZE_SCALAR(interval);
+ paramOut(os, base + ".count", count);
+ paramOut(os, base + ".latched_count", latched_count);
+ paramOut(os, base + ".period", period);
+ paramOut(os, base + ".mode", mode);
+ paramOut(os, base + ".output_high", output_high);
+ paramOut(os, base + ".latch_on", latch_on);
+ paramOut(os, base + ".read_byte", read_byte);
+ paramOut(os, base + ".write_byte", write_byte);
+
+ Tick event_tick = 0;
+ if (event.scheduled())
+ event_tick = event.when();
+ paramOut(os, base + ".event_tick", event_tick);
}
void
-TsunamiIO::ClockEvent::unserialize(Checkpoint *cp, const std::string §ion)
+TsunamiIO::PITimer::Counter::unserialize(const string &base, Checkpoint *cp,
+ const string §ion)
+{
+ paramIn(cp, section, base + ".count", count);
+ paramIn(cp, section, base + ".latched_count", latched_count);
+ paramIn(cp, section, base + ".period", period);
+ paramIn(cp, section, base + ".mode", mode);
+ paramIn(cp, section, base + ".output_high", output_high);
+ paramIn(cp, section, base + ".latch_on", latch_on);
+ paramIn(cp, section, base + ".read_byte", read_byte);
+ paramIn(cp, section, base + ".write_byte", write_byte);
+
+ Tick event_tick;
+ paramIn(cp, section, base + ".event_tick", event_tick);
+ if (event_tick)
+ event.schedule(event_tick);
+}
+
+TsunamiIO::PITimer::Counter::CounterEvent::CounterEvent(Counter* c_ptr)
+ : Event(&mainEventQueue)
+{
+ interval = (Tick)(Clock::Float::s / 1193180.0);
+ counter = c_ptr;
+}
+
+void
+TsunamiIO::PITimer::Counter::CounterEvent::process()
+{
+ DPRINTF(Tsunami, "Timer Interrupt\n");
+ switch (counter->mode) {
+ case PIT_MODE_INTTC:
+ counter->output_high = true;
+ case PIT_MODE_RATEGEN:
+ case PIT_MODE_SQWAVE:
+ break;
+ default:
+ panic("Unimplemented PITimer mode.\n");
+ }
+}
+
+const char *
+TsunamiIO::PITimer::Counter::CounterEvent::description()
{
- Tick time;
- UNSERIALIZE_SCALAR(time);
- UNSERIALIZE_SCALAR(status);
- UNSERIALIZE_SCALAR(mode);
- UNSERIALIZE_SCALAR(interval);
- if (time)
- schedule(time);
+ return "tsunami 8254 Interval timer";
}
TsunamiIO::TsunamiIO(const string &name, Tsunami *t, time_t init_time,
Addr a, MemoryController *mmu, HierParams *hier, Bus *bus,
Tick pio_latency, Tick ci)
- : PioDevice(name, t), addr(a), clockInterval(ci), tsunami(t), rtc(t, ci)
+ : PioDevice(name, t), addr(a), clockInterval(ci), tsunami(t),
+ pitimer(name + "pitimer"), rtc(name + ".rtc", t, ci)
{
mmu->add_child(this, RangeSize(addr, size));
if (bus) {
- pioInterface = newPioInterface(name, hier, bus, this,
+ pioInterface = newPioInterface(name + ".pio", hier, bus, this,
&TsunamiIO::cacheAccess);
pioInterface->addAddrRange(RangeSize(addr, size));
pioLatency = pio_latency * bus->clockRate;
tsunami->io = this;
timerData = 0;
- set_time(init_time == 0 ? time(NULL) : init_time);
- uip = 1;
+ rtc.set_time(init_time == 0 ? time(NULL) : init_time);
picr = 0;
picInterrupting = false;
}
return Clock::Frequency / clockInterval;
}
-void
-TsunamiIO::set_time(time_t t)
-{
- gmtime_r(&t, &tm);
- DPRINTFN("Real-time clock set to %s", asctime(&tm));
-}
-
Fault
TsunamiIO::read(MemReqPtr &req, uint8_t *data)
{
DPRINTF(Tsunami, "io read va=%#x size=%d IOPorrt=%#x\n",
req->vaddr, req->size, req->vaddr & 0xfff);
- Addr daddr = (req->paddr - (addr & EV5::PAddrImplMask)) + 0x20;
+ Addr daddr = (req->paddr - (addr & EV5::PAddrImplMask));
switch(req->size) {
// PIC2 not implemnted... just return 0
*(uint8_t*)data = 0x00;
return No_Fault;
- case TSDEV_TMR_CTL:
- *(uint8_t*)data = timer2.Status();
- return No_Fault;
case TSDEV_TMR0_DATA:
- *(uint8_t *)data = timer0.Read();
+ pitimer.counter0.read(data);
+ return No_Fault;
+ case TSDEV_TMR1_DATA:
+ pitimer.counter1.read(data);
+ return No_Fault;
+ case TSDEV_TMR2_DATA:
+ pitimer.counter2.read(data);
return No_Fault;
case TSDEV_RTC_DATA:
- switch(RTCAddress) {
- case RTC_CNTRL_REGA:
- *(uint8_t*)data = uip << 7 | 0x26;
- uip = !uip;
- return No_Fault;
- case RTC_CNTRL_REGB:
- // DM and 24/12 and UIE
- *(uint8_t*)data = 0x46;
- return No_Fault;
- case RTC_CNTRL_REGC:
- // If we want to support RTC user access in linux
- // This won't work, but for now it's fine
- *(uint8_t*)data = 0x00;
- return No_Fault;
- case RTC_CNTRL_REGD:
- panic("RTC Control Register D not implemented");
- case RTC_SEC:
- *(uint8_t *)data = tm.tm_sec;
- return No_Fault;
- case RTC_MIN:
- *(uint8_t *)data = tm.tm_min;
- return No_Fault;
- case RTC_HR:
- *(uint8_t *)data = tm.tm_hour;
- return No_Fault;
- case RTC_DOW:
- *(uint8_t *)data = tm.tm_wday;
- return No_Fault;
- case RTC_DOM:
- *(uint8_t *)data = tm.tm_mday;
- return No_Fault;
- case RTC_MON:
- *(uint8_t *)data = tm.tm_mon + 1;
- return No_Fault;
- case RTC_YEAR:
- *(uint8_t *)data = tm.tm_year - UNIX_YEAR_OFFSET;
- return No_Fault;
- default:
- panic("Unknown RTC Address\n");
- }
-
- /* Added for keyboard reads */
- case TSDEV_KBD:
- *(uint8_t *)data = 0x00;
+ rtc.readData(data);
return No_Fault;
- /* Added for ATA PCI DMA */
- case ATA_PCI_DMA:
- *(uint8_t *)data = 0x00;
+ case TSDEV_CTRL_PORTB:
+ if (pitimer.counter2.outputHigh())
+ *data = PORTB_SPKR_HIGH;
+ else
+ *data = 0x00;
return No_Fault;
default:
panic("I/O Read - va%#x size %d\n", req->vaddr, req->size);
DPRINTF(Tsunami, "io write - va=%#x size=%d IOPort=%#x Data=%#x\n",
req->vaddr, req->size, req->vaddr & 0xfff, dt64);
- Addr daddr = (req->paddr - (addr & EV5::PAddrImplMask)) + 0x20;
+ Addr daddr = (req->paddr - (addr & EV5::PAddrImplMask));
switch(req->size) {
case sizeof(uint8_t):
if (!(picr & mask1))
tsunami->cchip->clearDRIR(55);
return No_Fault;
+ case TSDEV_DMA1_CMND:
+ return No_Fault;
+ case TSDEV_DMA2_CMND:
+ return No_Fault;
+ case TSDEV_DMA1_MMASK:
+ return No_Fault;
+ case TSDEV_DMA2_MMASK:
+ return No_Fault;
case TSDEV_PIC2_ACK:
return No_Fault;
case TSDEV_DMA1_RESET:
case TSDEV_DMA1_MASK:
case TSDEV_DMA2_MASK:
return No_Fault;
- case TSDEV_TMR_CTL:
+ case TSDEV_TMR0_DATA:
+ pitimer.counter0.write(data);
return No_Fault;
- case TSDEV_TMR2_CTL:
- switch((*(uint8_t*)data >> 4) & 0x3) {
- case 0x0:
- switch(*(uint8_t*)data >> 6) {
- case 0:
- timer0.LatchCount();
- break;
- case 2:
- timer2.LatchCount();
- break;
- default:
- panic("Read Back Command not implemented\n");
- }
- break;
- case 0x3:
- break;
- default:
- panic("Only L/M write and Counter-Latch read supported\n");
- }
-
- switch(*(uint8_t*)data >> 6) {
- case 0:
- timer0.ChangeMode((*(uint8_t*)data & 0xF) >> 1);
- break;
- case 2:
- timer2.ChangeMode((*(uint8_t*)data & 0xF) >> 1);
- break;
- default:
- panic("Read Back Command not implemented\n");
- }
+ case TSDEV_TMR1_DATA:
+ pitimer.counter1.write(data);
return No_Fault;
case TSDEV_TMR2_DATA:
- /* two writes before we actually start the Timer
- so I set a flag in the timerData */
- if(timerData & 0x1000) {
- timerData &= 0x1000;
- timerData += *(uint8_t*)data << 8;
- timer2.Program(timerData);
- } else {
- timerData = *(uint8_t*)data;
- timerData |= 0x1000;
- }
+ pitimer.counter2.write(data);
return No_Fault;
- case TSDEV_TMR0_DATA:
- /* two writes before we actually start the Timer
- so I set a flag in the timerData */
- if(timerData & 0x1000) {
- timerData &= 0x1000;
- timerData += *(uint8_t*)data << 8;
- timer0.Program(timerData);
- } else {
- timerData = *(uint8_t*)data;
- timerData |= 0x1000;
- }
+ case TSDEV_TMR_CTRL:
+ pitimer.writeControl(data);
return No_Fault;
case TSDEV_RTC_ADDR:
- RTCAddress = *(uint8_t*)data;
+ rtc.writeAddr(data);
return No_Fault;
case TSDEV_KBD:
return No_Fault;
case TSDEV_RTC_DATA:
- switch(RTCAddress) {
- case RTC_CNTRL_REGA:
- return No_Fault;
- case RTC_CNTRL_REGB:
- return No_Fault;
- case RTC_CNTRL_REGC:
- return No_Fault;
- case RTC_CNTRL_REGD:
- return No_Fault;
- case RTC_SEC:
- tm.tm_sec = *(uint8_t *)data;
- return No_Fault;
- case RTC_MIN:
- tm.tm_min = *(uint8_t *)data;
- return No_Fault;
- case RTC_HR:
- tm.tm_hour = *(uint8_t *)data;
- return No_Fault;
- case RTC_DOW:
- tm.tm_wday = *(uint8_t *)data;
- return No_Fault;
- case RTC_DOM:
- tm.tm_mday = *(uint8_t *)data;
- return No_Fault;
- case RTC_MON:
- tm.tm_mon = *(uint8_t *)data - 1;
- return No_Fault;
- case RTC_YEAR:
- tm.tm_year = *(uint8_t *)data + UNIX_YEAR_OFFSET;
- return No_Fault;
- //panic("RTC Write not implmented (rtc.o won't work)\n");
- }
+ rtc.writeData(data);
+ return No_Fault;
+ case TSDEV_CTRL_PORTB:
+ // System Control Port B not implemented
+ return No_Fault;
default:
- panic("I/O Write - va%#x size %d\n", req->vaddr, req->size);
+ panic("I/O Write - va%#x size %d data %#x\n", req->vaddr, req->size, (int)*data);
}
case sizeof(uint16_t):
case sizeof(uint32_t):
}
void
-TsunamiIO::serialize(std::ostream &os)
+TsunamiIO::serialize(ostream &os)
{
SERIALIZE_SCALAR(timerData);
- SERIALIZE_SCALAR(uip);
SERIALIZE_SCALAR(mask1);
SERIALIZE_SCALAR(mask2);
SERIALIZE_SCALAR(mode1);
SERIALIZE_SCALAR(mode2);
SERIALIZE_SCALAR(picr);
SERIALIZE_SCALAR(picInterrupting);
- SERIALIZE_SCALAR(RTCAddress);
// Serialize the timers
- nameOut(os, csprintf("%s.timer0", name()));
- timer0.serialize(os);
- nameOut(os, csprintf("%s.timer2", name()));
- timer2.serialize(os);
- nameOut(os, csprintf("%s.rtc", name()));
- rtc.serialize(os);
+ pitimer.serialize("pitimer", os);
+ rtc.serialize("rtc", os);
}
void
-TsunamiIO::unserialize(Checkpoint *cp, const std::string §ion)
+TsunamiIO::unserialize(Checkpoint *cp, const string §ion)
{
UNSERIALIZE_SCALAR(timerData);
- UNSERIALIZE_SCALAR(uip);
UNSERIALIZE_SCALAR(mask1);
UNSERIALIZE_SCALAR(mask2);
UNSERIALIZE_SCALAR(mode1);
UNSERIALIZE_SCALAR(mode2);
UNSERIALIZE_SCALAR(picr);
UNSERIALIZE_SCALAR(picInterrupting);
- UNSERIALIZE_SCALAR(RTCAddress);
// Unserialize the timers
- timer0.unserialize(cp, csprintf("%s.timer0", section));
- timer2.unserialize(cp, csprintf("%s.timer2", section));
- rtc.unserialize(cp, csprintf("%s.rtc", section));
+ pitimer.unserialize("pitimer", cp, section);
+ rtc.unserialize("rtc", cp, section);
}
BEGIN_DECLARE_SIM_OBJECT_PARAMS(TsunamiIO)