Merge ktlim@zizzer:/bk/m5

[gem5.git] / dev / tsunami_pchip.cc

diff --git a/dev/tsunami_pchip.cc b/dev/tsunami_pchip.cc
index 0bad8b0e759d60a8dcef0ba4b52d560428addd84..46efc3dfe2183004f901e4fe606f3db35d281f53 100644 (file)
--- a/dev/tsunami_pchip.cc
+++ b/dev/tsunami_pchip.cc
@@ -47,10 +47,12 @@
 #include "sim/system.hh"
 
 using namespace std;
+//Should this be AlphaISA?
+using namespace TheISA;
 
 TsunamiPChip::TsunamiPChip(const string &name, Tsunami *t, Addr a,
                            MemoryController *mmu, HierParams *hier,
-                           Bus *bus, Tick pio_latency)
+                           Bus *pio_bus, Tick pio_latency)
     : PioDevice(name, t), addr(a), tsunami(t)
 {
     mmu->add_child(this, RangeSize(addr, size));
@@ -61,11 +63,11 @@ TsunamiPChip::TsunamiPChip(const string &name, Tsunami *t, Addr a,
         tba[i] = 0;
     }
 
-    if (bus) {
-        pioInterface = newPioInterface(name + ".pio", hier, bus, this,
+    if (pio_bus) {
+        pioInterface = newPioInterface(name + ".pio", hier, pio_bus, this,
                                       &TsunamiPChip::cacheAccess);
         pioInterface->addAddrRange(RangeSize(addr, size));
-        pioLatency = pio_latency * bus->clockRate;
+        pioLatency = pio_latency * pio_bus->clockRate;
     }
 
 
@@ -90,60 +92,60 @@ TsunamiPChip::read(MemReqPtr &req, uint8_t *data)
           switch(daddr) {
               case TSDEV_PC_WSBA0:
                     *(uint64_t*)data = wsba[0];
-                    return No_Fault;
+                    return NoFault;
               case TSDEV_PC_WSBA1:
                     *(uint64_t*)data = wsba[1];
-                    return No_Fault;
+                    return NoFault;
               case TSDEV_PC_WSBA2:
                     *(uint64_t*)data = wsba[2];
-                    return No_Fault;
+                    return NoFault;
               case TSDEV_PC_WSBA3:
                     *(uint64_t*)data = wsba[3];
-                    return No_Fault;
+                    return NoFault;
               case TSDEV_PC_WSM0:
                     *(uint64_t*)data = wsm[0];
-                    return No_Fault;
+                    return NoFault;
               case TSDEV_PC_WSM1:
                     *(uint64_t*)data = wsm[1];
-                    return No_Fault;
+                    return NoFault;
               case TSDEV_PC_WSM2:
                     *(uint64_t*)data = wsm[2];
-                    return No_Fault;
+                    return NoFault;
               case TSDEV_PC_WSM3:
                     *(uint64_t*)data = wsm[3];
-                    return No_Fault;
+                    return NoFault;
               case TSDEV_PC_TBA0:
                     *(uint64_t*)data = tba[0];
-                    return No_Fault;
+                    return NoFault;
               case TSDEV_PC_TBA1:
                     *(uint64_t*)data = tba[1];
-                    return No_Fault;
+                    return NoFault;
               case TSDEV_PC_TBA2:
                     *(uint64_t*)data = tba[2];
-                    return No_Fault;
+                    return NoFault;
               case TSDEV_PC_TBA3:
                     *(uint64_t*)data = tba[3];
-                    return No_Fault;
+                    return NoFault;
               case TSDEV_PC_PCTL:
                     *(uint64_t*)data = pctl;
-                    return No_Fault;
+                    return NoFault;
               case TSDEV_PC_PLAT:
                     panic("PC_PLAT not implemented\n");
               case TSDEV_PC_RES:
                     panic("PC_RES not implemented\n");
               case TSDEV_PC_PERROR:
                     *(uint64_t*)data = 0x00;
-                    return No_Fault;
+                    return NoFault;
               case TSDEV_PC_PERRMASK:
                     *(uint64_t*)data = 0x00;
-                    return No_Fault;
+                    return NoFault;
               case TSDEV_PC_PERRSET:
                     panic("PC_PERRSET not implemented\n");
               case TSDEV_PC_TLBIV:
                     panic("PC_TLBIV not implemented\n");
               case TSDEV_PC_TLBIA:
                     *(uint64_t*)data = 0x00; // shouldn't be readable, but linux
-                    return No_Fault;
+                    return NoFault;
               case TSDEV_PC_PMONCTL:
                     panic("PC_PMONCTL not implemented\n");
               case TSDEV_PC_PMONCNT:
@@ -162,7 +164,7 @@ TsunamiPChip::read(MemReqPtr &req, uint8_t *data)
     }
     DPRINTFN("Tsunami PChip ERROR: read  daddr=%#x size=%d\n", daddr, req->size);
 
-    return No_Fault;
+    return NoFault;
 }
 
 Fault
@@ -179,49 +181,49 @@ TsunamiPChip::write(MemReqPtr &req, const uint8_t *data)
           switch(daddr) {
               case TSDEV_PC_WSBA0:
                     wsba[0] = *(uint64_t*)data;
-                    return No_Fault;
+                    return NoFault;
               case TSDEV_PC_WSBA1:
                     wsba[1] = *(uint64_t*)data;
-                    return No_Fault;
+                    return NoFault;
               case TSDEV_PC_WSBA2:
                     wsba[2] = *(uint64_t*)data;
-                    return No_Fault;
+                    return NoFault;
               case TSDEV_PC_WSBA3:
                     wsba[3] = *(uint64_t*)data;
-                    return No_Fault;
+                    return NoFault;
               case TSDEV_PC_WSM0:
                     wsm[0] = *(uint64_t*)data;
-                    return No_Fault;
+                    return NoFault;
               case TSDEV_PC_WSM1:
                     wsm[1] = *(uint64_t*)data;
-                    return No_Fault;
+                    return NoFault;
               case TSDEV_PC_WSM2:
                     wsm[2] = *(uint64_t*)data;
-                    return No_Fault;
+                    return NoFault;
               case TSDEV_PC_WSM3:
                     wsm[3] = *(uint64_t*)data;
-                    return No_Fault;
+                    return NoFault;
               case TSDEV_PC_TBA0:
                     tba[0] = *(uint64_t*)data;
-                    return No_Fault;
+                    return NoFault;
               case TSDEV_PC_TBA1:
                     tba[1] = *(uint64_t*)data;
-                    return No_Fault;
+                    return NoFault;
               case TSDEV_PC_TBA2:
                     tba[2] = *(uint64_t*)data;
-                    return No_Fault;
+                    return NoFault;
               case TSDEV_PC_TBA3:
                     tba[3] = *(uint64_t*)data;
-                    return No_Fault;
+                    return NoFault;
               case TSDEV_PC_PCTL:
                     pctl = *(uint64_t*)data;
-                    return No_Fault;
+                    return NoFault;
               case TSDEV_PC_PLAT:
                     panic("PC_PLAT not implemented\n");
               case TSDEV_PC_RES:
                     panic("PC_RES not implemented\n");
               case TSDEV_PC_PERROR:
-                    return No_Fault;
+                    return NoFault;
               case TSDEV_PC_PERRMASK:
                     panic("PC_PERRMASK not implemented\n");
               case TSDEV_PC_PERRSET:
@@ -229,7 +231,7 @@ TsunamiPChip::write(MemReqPtr &req, const uint8_t *data)
               case TSDEV_PC_TLBIV:
                     panic("PC_TLBIV not implemented\n");
               case TSDEV_PC_TLBIA:
-                    return No_Fault; // value ignored, supposted to invalidate SG TLB
+                    return NoFault; // value ignored, supposted to invalidate SG TLB
               case TSDEV_PC_PMONCTL:
                     panic("PC_PMONCTL not implemented\n");
               case TSDEV_PC_PMONCNT:
@@ -249,7 +251,7 @@ TsunamiPChip::write(MemReqPtr &req, const uint8_t *data)
 
     DPRINTFN("Tsunami ERROR: write daddr=%#x size=%d\n", daddr, req->size);
 
-    return No_Fault;
+    return NoFault;
 }
 
 #define DMA_ADDR_MASK ULL(0x3ffffffff)
@@ -360,7 +362,7 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(TsunamiPChip)
     SimObjectParam<Tsunami *> tsunami;
     SimObjectParam<MemoryController *> mmu;
     Param<Addr> addr;
-    SimObjectParam<Bus*> io_bus;
+    SimObjectParam<Bus*> pio_bus;
     Param<Tick> pio_latency;
     SimObjectParam<HierParams *> hier;
 
@@ -371,7 +373,7 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(TsunamiPChip)
     INIT_PARAM(tsunami, "Tsunami"),
     INIT_PARAM(mmu, "Memory Controller"),
     INIT_PARAM(addr, "Device Address"),
-    INIT_PARAM_DFLT(io_bus, "The IO Bus to attach to", NULL),
+    INIT_PARAM_DFLT(pio_bus, "The IO Bus to attach to", NULL),
     INIT_PARAM_DFLT(pio_latency, "Programmed IO latency in bus cycles", 1),
     INIT_PARAM_DFLT(hier, "Hierarchy global variables", &defaultHierParams)
 
@@ -380,7 +382,7 @@ END_INIT_SIM_OBJECT_PARAMS(TsunamiPChip)
 CREATE_SIM_OBJECT(TsunamiPChip)
 {
     return new TsunamiPChip(getInstanceName(), tsunami, addr, mmu, hier,
-                            io_bus, pio_latency);
+                            pio_bus, pio_latency);
 }
 
 REGISTER_SIM_OBJECT("TsunamiPChip", TsunamiPChip)