/*
- * Copyright (c) 2004 The Regents of The University of Michigan
+ * Copyright (c) 2004-2005 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-/* @file
+/** @file
* Tsunami PChip (pci)
*/
#include <vector>
#include "base/trace.hh"
-#include "cpu/exec_context.hh"
-#include "dev/console.hh"
-#include "dev/etherdev.hh"
-#include "dev/scsi_ctrl.hh"
-#include "dev/tlaser_clock.hh"
#include "dev/tsunami_pchip.hh"
#include "dev/tsunamireg.h"
#include "dev/tsunami.hh"
-#include "mem/functional_mem/memory_control.hh"
-#include "mem/functional_mem/physical_memory.hh"
+#include "mem/bus/bus.hh"
+#include "mem/bus/pio_interface.hh"
+#include "mem/bus/pio_interface_impl.hh"
+#include "mem/functional/memory_control.hh"
+#include "mem/functional/physical.hh"
#include "sim/builder.hh"
#include "sim/system.hh"
using namespace std;
+//Should this be AlphaISA?
+using namespace TheISA;
TsunamiPChip::TsunamiPChip(const string &name, Tsunami *t, Addr a,
- MemoryController *mmu)
- : FunctionalMemory(name), addr(a), tsunami(t)
+ MemoryController *mmu, HierParams *hier,
+ Bus *pio_bus, Tick pio_latency)
+ : PioDevice(name, t), addr(a), tsunami(t)
{
- mmu->add_child(this, Range<Addr>(addr, addr + size));
+ mmu->add_child(this, RangeSize(addr, size));
for (int i = 0; i < 4; i++) {
wsba[i] = 0;
tba[i] = 0;
}
+ if (pio_bus) {
+ pioInterface = newPioInterface(name + ".pio", hier, pio_bus, this,
+ &TsunamiPChip::cacheAccess);
+ pioInterface->addAddrRange(RangeSize(addr, size));
+ pioLatency = pio_latency * pio_bus->clockRate;
+ }
+
+
// initialize pchip control register
pctl = (ULL(0x1) << 20) | (ULL(0x1) << 32) | (ULL(0x2) << 36);
tsunami->pchip = this;
}
-Fault
+Fault *
TsunamiPChip::read(MemReqPtr &req, uint8_t *data)
{
DPRINTF(Tsunami, "read va=%#x size=%d\n",
req->vaddr, req->size);
- Addr daddr = (req->paddr - (addr & PA_IMPL_MASK)) >> 6;
+ Addr daddr = (req->paddr - (addr & EV5::PAddrImplMask)) >> 6;
switch (req->size) {
switch(daddr) {
case TSDEV_PC_WSBA0:
*(uint64_t*)data = wsba[0];
- return No_Fault;
+ return NoFault;
case TSDEV_PC_WSBA1:
*(uint64_t*)data = wsba[1];
- return No_Fault;
+ return NoFault;
case TSDEV_PC_WSBA2:
*(uint64_t*)data = wsba[2];
- return No_Fault;
+ return NoFault;
case TSDEV_PC_WSBA3:
*(uint64_t*)data = wsba[3];
- return No_Fault;
+ return NoFault;
case TSDEV_PC_WSM0:
*(uint64_t*)data = wsm[0];
- return No_Fault;
+ return NoFault;
case TSDEV_PC_WSM1:
*(uint64_t*)data = wsm[1];
- return No_Fault;
+ return NoFault;
case TSDEV_PC_WSM2:
*(uint64_t*)data = wsm[2];
- return No_Fault;
+ return NoFault;
case TSDEV_PC_WSM3:
*(uint64_t*)data = wsm[3];
- return No_Fault;
+ return NoFault;
case TSDEV_PC_TBA0:
*(uint64_t*)data = tba[0];
- return No_Fault;
+ return NoFault;
case TSDEV_PC_TBA1:
*(uint64_t*)data = tba[1];
- return No_Fault;
+ return NoFault;
case TSDEV_PC_TBA2:
*(uint64_t*)data = tba[2];
- return No_Fault;
+ return NoFault;
case TSDEV_PC_TBA3:
*(uint64_t*)data = tba[3];
- return No_Fault;
+ return NoFault;
case TSDEV_PC_PCTL:
*(uint64_t*)data = pctl;
- return No_Fault;
+ return NoFault;
case TSDEV_PC_PLAT:
panic("PC_PLAT not implemented\n");
case TSDEV_PC_RES:
panic("PC_RES not implemented\n");
case TSDEV_PC_PERROR:
*(uint64_t*)data = 0x00;
- return No_Fault;
+ return NoFault;
case TSDEV_PC_PERRMASK:
*(uint64_t*)data = 0x00;
- return No_Fault;
+ return NoFault;
case TSDEV_PC_PERRSET:
panic("PC_PERRSET not implemented\n");
case TSDEV_PC_TLBIV:
panic("PC_TLBIV not implemented\n");
case TSDEV_PC_TLBIA:
*(uint64_t*)data = 0x00; // shouldn't be readable, but linux
- return No_Fault;
+ return NoFault;
case TSDEV_PC_PMONCTL:
panic("PC_PMONCTL not implemented\n");
case TSDEV_PC_PMONCNT:
}
DPRINTFN("Tsunami PChip ERROR: read daddr=%#x size=%d\n", daddr, req->size);
- return No_Fault;
+ return NoFault;
}
-Fault
+Fault *
TsunamiPChip::write(MemReqPtr &req, const uint8_t *data)
{
DPRINTF(Tsunami, "write - va=%#x size=%d \n",
req->vaddr, req->size);
- Addr daddr = (req->paddr - (addr & PA_IMPL_MASK)) >> 6;
+ Addr daddr = (req->paddr - (addr & EV5::PAddrImplMask)) >> 6;
switch (req->size) {
switch(daddr) {
case TSDEV_PC_WSBA0:
wsba[0] = *(uint64_t*)data;
- return No_Fault;
+ return NoFault;
case TSDEV_PC_WSBA1:
wsba[1] = *(uint64_t*)data;
- return No_Fault;
+ return NoFault;
case TSDEV_PC_WSBA2:
wsba[2] = *(uint64_t*)data;
- return No_Fault;
+ return NoFault;
case TSDEV_PC_WSBA3:
wsba[3] = *(uint64_t*)data;
- return No_Fault;
+ return NoFault;
case TSDEV_PC_WSM0:
wsm[0] = *(uint64_t*)data;
- return No_Fault;
+ return NoFault;
case TSDEV_PC_WSM1:
wsm[1] = *(uint64_t*)data;
- return No_Fault;
+ return NoFault;
case TSDEV_PC_WSM2:
wsm[2] = *(uint64_t*)data;
- return No_Fault;
+ return NoFault;
case TSDEV_PC_WSM3:
wsm[3] = *(uint64_t*)data;
- return No_Fault;
+ return NoFault;
case TSDEV_PC_TBA0:
tba[0] = *(uint64_t*)data;
- return No_Fault;
+ return NoFault;
case TSDEV_PC_TBA1:
tba[1] = *(uint64_t*)data;
- return No_Fault;
+ return NoFault;
case TSDEV_PC_TBA2:
tba[2] = *(uint64_t*)data;
- return No_Fault;
+ return NoFault;
case TSDEV_PC_TBA3:
tba[3] = *(uint64_t*)data;
- return No_Fault;
+ return NoFault;
case TSDEV_PC_PCTL:
pctl = *(uint64_t*)data;
- return No_Fault;
+ return NoFault;
case TSDEV_PC_PLAT:
panic("PC_PLAT not implemented\n");
case TSDEV_PC_RES:
panic("PC_RES not implemented\n");
case TSDEV_PC_PERROR:
- return No_Fault;
+ return NoFault;
case TSDEV_PC_PERRMASK:
panic("PC_PERRMASK not implemented\n");
case TSDEV_PC_PERRSET:
case TSDEV_PC_TLBIV:
panic("PC_TLBIV not implemented\n");
case TSDEV_PC_TLBIA:
- return No_Fault; // value ignored, supposted to invalidate SG TLB
+ return NoFault; // value ignored, supposted to invalidate SG TLB
case TSDEV_PC_PMONCTL:
panic("PC_PMONCTL not implemented\n");
case TSDEV_PC_PMONCNT:
DPRINTFN("Tsunami ERROR: write daddr=%#x size=%d\n", daddr, req->size);
- return No_Fault;
+ return NoFault;
}
#define DMA_ADDR_MASK ULL(0x3ffffffff)
UNSERIALIZE_ARRAY(tba, 4);
}
+Tick
+TsunamiPChip::cacheAccess(MemReqPtr &req)
+{
+ return curTick + pioLatency;
+}
+
BEGIN_DECLARE_SIM_OBJECT_PARAMS(TsunamiPChip)
SimObjectParam<Tsunami *> tsunami;
SimObjectParam<MemoryController *> mmu;
Param<Addr> addr;
+ SimObjectParam<Bus*> pio_bus;
+ Param<Tick> pio_latency;
+ SimObjectParam<HierParams *> hier;
END_DECLARE_SIM_OBJECT_PARAMS(TsunamiPChip)
INIT_PARAM(tsunami, "Tsunami"),
INIT_PARAM(mmu, "Memory Controller"),
- INIT_PARAM(addr, "Device Address")
+ INIT_PARAM(addr, "Device Address"),
+ INIT_PARAM_DFLT(pio_bus, "The IO Bus to attach to", NULL),
+ INIT_PARAM_DFLT(pio_latency, "Programmed IO latency in bus cycles", 1),
+ INIT_PARAM_DFLT(hier, "Hierarchy global variables", &defaultHierParams)
END_INIT_SIM_OBJECT_PARAMS(TsunamiPChip)
CREATE_SIM_OBJECT(TsunamiPChip)
{
- return new TsunamiPChip(getInstanceName(), tsunami, addr, mmu);
+ return new TsunamiPChip(getInstanceName(), tsunami, addr, mmu, hier,
+ pio_bus, pio_latency);
}
REGISTER_SIM_OBJECT("TsunamiPChip", TsunamiPChip)
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