Merge zizzer:/bk/m5 into zeep.eecs.umich.edu:/z/saidi/work/m5

[gem5.git] / dev / tsunami_pchip.cc

diff --git a/dev/tsunami_pchip.cc b/dev/tsunami_pchip.cc
index b1346bb1af60acd6f09decd635b01f16a0d6723c..9af19d9304fa19d401154e0bef7bc1672f055b14 100644 (file)
--- a/dev/tsunami_pchip.cc
+++ b/dev/tsunami_pchip.cc
@@ -50,10 +50,10 @@ using namespace std;
 
 TsunamiPChip::TsunamiPChip(const string &name, Tsunami *t, Addr a,
                            MemoryController *mmu, HierParams *hier,
-                           Bus *bus)
+                           Bus *bus, Tick pio_latency)
     : PioDevice(name), addr(a), tsunami(t)
 {
-    mmu->add_child(this, Range<Addr>(addr, addr + size));
+    mmu->add_child(this, RangeSize(addr, size));
 
     for (int i = 0; i < 4; i++) {
         wsba[i] = 0;
@@ -64,7 +64,8 @@ TsunamiPChip::TsunamiPChip(const string &name, Tsunami *t, Addr a,
     if (bus) {
         pioInterface = newPioInterface(name, hier, bus, this,
                                       &TsunamiPChip::cacheAccess);
-        pioInterface->addAddrRange(addr, addr + size - 1);
+        pioInterface->addAddrRange(RangeSize(addr, size));
+        pioLatency = pio_latency * bus->clockRatio;
     }
 
 
@@ -81,7 +82,7 @@ TsunamiPChip::read(MemReqPtr &req, uint8_t *data)
     DPRINTF(Tsunami, "read  va=%#x size=%d\n",
             req->vaddr, req->size);
 
-    Addr daddr = (req->paddr - (addr & PA_IMPL_MASK)) >> 6;
+    Addr daddr = (req->paddr - (addr & EV5::PAddrImplMask)) >> 6;
 
     switch (req->size) {
 
@@ -170,7 +171,7 @@ TsunamiPChip::write(MemReqPtr &req, const uint8_t *data)
     DPRINTF(Tsunami, "write - va=%#x size=%d \n",
             req->vaddr, req->size);
 
-    Addr daddr = (req->paddr - (addr & PA_IMPL_MASK)) >> 6;
+    Addr daddr = (req->paddr - (addr & EV5::PAddrImplMask)) >> 6;
 
     switch (req->size) {
 
@@ -351,7 +352,7 @@ TsunamiPChip::unserialize(Checkpoint *cp, const std::string &section)
 Tick
 TsunamiPChip::cacheAccess(MemReqPtr &req)
 {
-    return curTick + 1000;
+    return curTick + pioLatency;
 }
 
 BEGIN_DECLARE_SIM_OBJECT_PARAMS(TsunamiPChip)
@@ -360,6 +361,7 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(TsunamiPChip)
     SimObjectParam<MemoryController *> mmu;
     Param<Addr> addr;
     SimObjectParam<Bus*> io_bus;
+    Param<Tick> pio_latency;
     SimObjectParam<HierParams *> hier;
 
 END_DECLARE_SIM_OBJECT_PARAMS(TsunamiPChip)
@@ -370,13 +372,15 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(TsunamiPChip)
     INIT_PARAM(mmu, "Memory Controller"),
     INIT_PARAM(addr, "Device Address"),
     INIT_PARAM_DFLT(io_bus, "The IO Bus to attach to", NULL),
+    INIT_PARAM_DFLT(pio_latency, "Programmed IO latency in bus cycles", 1),
     INIT_PARAM_DFLT(hier, "Hierarchy global variables", &defaultHierParams)
 
 END_INIT_SIM_OBJECT_PARAMS(TsunamiPChip)
 
 CREATE_SIM_OBJECT(TsunamiPChip)
 {
-    return new TsunamiPChip(getInstanceName(), tsunami, addr, mmu, hier, io_bus);
+    return new TsunamiPChip(getInstanceName(), tsunami, addr, mmu, hier,
+                            io_bus, pio_latency);
 }
 
 REGISTER_SIM_OBJECT("TsunamiPChip", TsunamiPChip)