Better handling of latency/frequency parameter types

[gem5.git] / dev / tsunami_pchip.hh

diff --git a/dev/tsunami_pchip.hh b/dev/tsunami_pchip.hh
index 3ed66c54c4015b24be7e8f341a53ff3b9e9d97a1..f88098d58923eb4db9c190aef9d0a3b1e7a669ea 100644 (file)
--- a/dev/tsunami_pchip.hh
+++ b/dev/tsunami_pchip.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2003 The Regents of The University of Michigan
+ * Copyright (c) 2004 The Regents of The University of Michigan
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -33,38 +33,99 @@
 #ifndef __TSUNAMI_PCHIP_HH__
 #define __TSUNAMI_PCHIP_HH__
 
-#include "mem/functional_mem/functional_memory.hh"
 #include "dev/tsunami.hh"
+#include "base/range.hh"
+#include "dev/io_device.hh"
 
 /*
  * Tsunami PChip
  */
-class TsunamiPChip : public FunctionalMemory
+class TsunamiPChip : public PioDevice
 {
   private:
+    /** The base address of this device */
     Addr addr;
+
+    /** The size of mappad from the above address */
     static const Addr size = 0xfff;
 
   protected:
+    /**
+     * pointer to the tsunami object.
+     * This is our access to all the other tsunami
+     * devices.
+     */
     Tsunami *tsunami;
 
+    /** Pchip control register */
+    uint64_t pctl;
+
+    /** Window Base addresses */
     uint64_t wsba[4];
+
+    /** Window masks */
     uint64_t wsm[4];
+
+    /** Translated Base Addresses */
     uint64_t tba[4];
 
   public:
+    /**
+     * Register the PChip with the mmu and init all wsba, wsm, and tba to 0
+     * @param name the name of thes device
+     * @param t a pointer to the tsunami device
+     * @param a the address which we respond to
+     * @param mmu the mmu we are to register with
+     * @param hier object to store parameters universal the device hierarchy
+     * @param bus The bus that this device is attached to
+     */
     TsunamiPChip(const std::string &name, Tsunami *t, Addr a,
-                 MemoryController *mmu);
+                 MemoryController *mmu, HierParams *hier, Bus *bus,
+                 Tick pio_latency);
 
-    // @todo This hack does a quick and dirty translation of the PCI bus address to
-    //  a valid DMA address.  This is described in 10-10 of the Tsunami book, should be fixed
+    /**
+     * Translate a PCI bus address to a memory address for DMA.
+     * @todo Andrew says this needs to be fixed. What's wrong with it?
+     * @param busAddr PCI address to translate.
+     * @return memory system address
+     */
     Addr translatePciToDma(Addr busAddr);
 
+     /**
+      * Process a read to the PChip.
+      * @param req Contains the address to read from.
+      * @param data A pointer to write the read data to.
+      * @return The fault condition of the access.
+      */
     virtual Fault read(MemReqPtr &req, uint8_t *data);
+
+    /**
+      * Process a write to the PChip.
+      * @param req Contains the address to write to.
+      * @param data The data to write.
+      * @return The fault condition of the access.
+      */
     virtual Fault write(MemReqPtr &req, const uint8_t *data);
 
+    /**
+     * Serialize this object to the given output stream.
+     * @param os The stream to serialize to.
+     */
     virtual void serialize(std::ostream &os);
+
+    /**
+     * Reconstruct the state of this object from a checkpoint.
+     * @param cp The checkpoint use.
+     * @param section The section name of this object
+     */
     virtual void unserialize(Checkpoint *cp, const std::string &section);
+
+    /**
+     * Return how long this access will take.
+     * @param req the memory request to calcuate
+     * @return Tick when the request is done
+     */
+    Tick cacheAccess(MemReqPtr &req);
 };
 
 #endif // __TSUNAMI_PCHIP_HH__