/*
- * Copyright (c) 2003 The Regents of The University of Michigan
+ * Copyright (c) 2004-2005 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-/* @file
- * Tsunami PChip
+/** @file
+ * Tsunami PCI interface CSRs
*/
#ifndef __TSUNAMI_PCHIP_HH__
#define __TSUNAMI_PCHIP_HH__
-#include "mem/functional_mem/mmap_device.hh"
#include "dev/tsunami.hh"
+#include "base/range.hh"
+#include "dev/io_device.hh"
-/*
- * Tsunami PChip
+class MemoryController;
+
+/**
+ * A very simple implementation of the Tsunami PCI interface chips.
*/
-class TsunamiPChip : public MmapDevice
+class TsunamiPChip : public PioDevice
{
- public:
+ private:
+ /** The base address of this device */
+ Addr addr;
+
+ /** The size of mappad from the above address */
+ static const Addr size = 0xfff;
protected:
+ /**
+ * pointer to the tsunami object.
+ * This is our access to all the other tsunami
+ * devices.
+ */
Tsunami *tsunami;
- uint64_t wsba0;
- uint64_t wsba1;
- uint64_t wsba2;
- uint64_t wsba3;
- uint64_t wsm0;
- uint64_t wsm1;
- uint64_t wsm2;
- uint64_t wsm3;
- uint64_t tba0;
- uint64_t tba1;
- uint64_t tba2;
- uint64_t tba3;
+ /** Pchip control register */
+ uint64_t pctl;
+
+ /** Window Base addresses */
+ uint64_t wsba[4];
+ /** Window masks */
+ uint64_t wsm[4];
+
+ /** Translated Base Addresses */
+ uint64_t tba[4];
public:
- TsunamiPChip(const std::string &name, Tsunami *t,
- Addr addr, Addr mask, MemoryController *mmu);
+ /**
+ * Register the PChip with the mmu and init all wsba, wsm, and tba to 0
+ * @param name the name of thes device
+ * @param t a pointer to the tsunami device
+ * @param a the address which we respond to
+ * @param mmu the mmu we are to register with
+ * @param hier object to store parameters universal the device hierarchy
+ * @param bus The bus that this device is attached to
+ */
+ TsunamiPChip(const std::string &name, Tsunami *t, Addr a,
+ MemoryController *mmu, HierParams *hier, Bus *pio_bus,
+ Tick pio_latency);
+
+ /**
+ * Translate a PCI bus address to a memory address for DMA.
+ * @todo Andrew says this needs to be fixed. What's wrong with it?
+ * @param busAddr PCI address to translate.
+ * @return memory system address
+ */
+ Addr translatePciToDma(Addr busAddr);
+
+ /**
+ * Process a read to the PChip.
+ * @param req Contains the address to read from.
+ * @param data A pointer to write the read data to.
+ * @return The fault condition of the access.
+ */
+ virtual Fault * read(MemReqPtr &req, uint8_t *data);
- virtual Fault read(MemReqPtr &req, uint8_t *data);
- virtual Fault write(MemReqPtr &req, const uint8_t *data);
+ /**
+ * Process a write to the PChip.
+ * @param req Contains the address to write to.
+ * @param data The data to write.
+ * @return The fault condition of the access.
+ */
+ virtual Fault * write(MemReqPtr &req, const uint8_t *data);
+ /**
+ * Serialize this object to the given output stream.
+ * @param os The stream to serialize to.
+ */
virtual void serialize(std::ostream &os);
+
+ /**
+ * Reconstruct the state of this object from a checkpoint.
+ * @param cp The checkpoint use.
+ * @param section The section name of this object
+ */
virtual void unserialize(Checkpoint *cp, const std::string §ion);
+
+ /**
+ * Return how long this access will take.
+ * @param req the memory request to calcuate
+ * @return Tick when the request is done
+ */
+ Tick cacheAccess(MemReqPtr &req);
};
#endif // __TSUNAMI_PCHIP_HH__