Standardize clock parameter names to 'clock'.

[gem5.git] / dev / tsunamireg.h

diff --git a/dev/tsunamireg.h b/dev/tsunamireg.h
index b41b3994d32ec6e69d7ffeb32b0032e6be7aa21d..290f21a5bc7bc5b2b393e3c4b7407732c9d2aa72 100644 (file)
--- a/dev/tsunamireg.h
+++ b/dev/tsunamireg.h
@@ -1,7 +1,36 @@
+/*
+ * Copyright (c) 2004 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
 
 #ifndef __TSUNAMIREG_H__
 #define __TSUNAMIREG_H__
 
+#define ALPHA_K0SEG_BASE  ULL(0xfffffc0000000000)
+
 // CChip Registers
 #define TSDEV_CC_CSR    0x00
 #define TSDEV_CC_MTR    0x01
@@ -31,6 +60,13 @@
 #define TSDEV_CC_IIC2   0x1C
 #define TSDEV_CC_IIC3   0x1D
 
+// BigTsunami Registers
+#define TSDEV_CC_BDIMS  0x1000000
+#define TSDEV_CC_BDIRS  0x2000000
+#define TSDEV_CC_IPIQ   0x20  //0xf01a000800
+#define TSDEV_CC_IPIR   0x21  //0xf01a000840
+#define TSDEV_CC_ITIR   0x22  //0xf01a000880
+
 
 // PChip Registers
 #define TSDEV_PC_WSBA0      0x00
@@ -68,11 +104,41 @@
 // I/O Ports
 #define TSDEV_PIC1_MASK     0x21
 #define TSDEV_PIC2_MASK     0xA1
+#define TSDEV_PIC1_ISR      0x20
+#define TSDEV_PIC2_ISR      0xA0
+#define TSDEV_PIC1_ACK      0x20
+#define TSDEV_PIC2_ACK      0xA0
 #define TSDEV_DMA1_RESET    0x0D
 #define TSDEV_DMA2_RESET    0xDA
 #define TSDEV_DMA1_MODE     0x0B
 #define TSDEV_DMA2_MODE     0xD6
 #define TSDEV_DMA1_MASK     0x0A
 #define TSDEV_DMA2_MASK     0xD4
+#define TSDEV_TMR_CTL       0x61
+#define TSDEV_TMR2_CTL      0x43
+#define TSDEV_TMR2_DATA     0x42
+#define TSDEV_TMR0_DATA     0x40
+
+#define TSDEV_RTC_ADDR      0x70
+#define TSDEV_RTC_DATA      0x71
+
+#define PCHIP_PCI0_MEMORY       ULL(0x00000000000)
+#define PCHIP_PCI0_IO           ULL(0x001FC000000)
+#define TSUNAMI_UNCACHABLE_BIT  ULL(0x80000000000)
+#define TSUNAMI_PCI0_MEMORY     TSUNAMI_UNCACHABLE_BIT + PCHIP_PCI0_MEMORY
+#define TSUNAMI_PCI0_IO         TSUNAMI_UNCACHABLE_BIT + PCHIP_PCI0_IO
+
+
+// UART Defines
+#define UART_IER_RDI            0x01
+#define UART_IER_THRI           0x02
+#define UART_IER_RLSI           0x04
+
+
+#define UART_LSR_TEMT   0x40
+#define UART_LSR_THRE   0x20
+#define UART_LSR_DR     0x01
+
+#define UART_MCR_LOOP   0x10
 
 #endif // __TSUNAMIREG_H__