#include "mem/bus/pio_interface_impl.hh"
#include "mem/functional_mem/memory_control.hh"
#include "sim/builder.hh"
-#include "targetarch/ev5.hh"
using namespace std;
-Uart::IntrEvent::IntrEvent(Uart *u)
+Uart::IntrEvent::IntrEvent(Uart *u, int bit)
: Event(&mainEventQueue), uart(u)
{
DPRINTF(Uart, "UART Interrupt Event Initilizing\n");
+ intrBit = bit;
}
const char *
void
Uart::IntrEvent::process()
{
- if (UART_IER_THRI & uart->IER) {
+ if (intrBit & uart->IER) {
DPRINTF(Uart, "UART InterEvent, interrupting\n");
uart->platform->postConsoleInt();
- uart->status |= TX_INT;
+ uart->status |= intrBit;
}
else
DPRINTF(Uart, "UART InterEvent, not interrupting\n");
void
Uart::IntrEvent::scheduleIntr()
{
- DPRINTF(Uart, "Scheduling IER interrupt\n");
+ DPRINTF(Uart, "Scheduling IER interrupt for %#x, at cycle %lld\n", intrBit,
+ curTick + (ticksPerSecond/2000) * 350);
if (!scheduled())
/* @todo Make this cleaner, will be much easier with
* nanosecond time everywhere. Hint hint Nate. */
- schedule(curTick + (ticksPerSecond/2000) * 350);
+ schedule(curTick + (ticksPerSecond/2000000000) * 450);
else
- reschedule(curTick + (ticksPerSecond/2000) * 350);
+ reschedule(curTick + (ticksPerSecond/2000000000) * 450);
}
Uart::Uart(const string &name, SimConsole *c, MemoryController *mmu, Addr a,
- Addr s, HierParams *hier, Bus *bus, Platform *p)
- : PioDevice(name), addr(a), size(s), cons(c), intrEvent(this), platform(p)
+ Addr s, HierParams *hier, Bus *bus, Tick pio_latency, Platform *p)
+ : PioDevice(name, p), addr(a), size(s), cons(c),
+ txIntrEvent(this, TX_INT), rxIntrEvent(this, RX_INT)
{
- mmu->add_child(this, Range<Addr>(addr, addr + size));
+ mmu->add_child(this, RangeSize(addr, size));
if (bus) {
pioInterface = newPioInterface(name, hier, bus, this,
&Uart::cacheAccess);
- pioInterface->addAddrRange(addr, addr + size - 1);
+ pioInterface->addAddrRange(RangeSize(addr, size));
+ pioLatency = pio_latency * bus->clockRatio;
}
readAddr = 0;
Fault
Uart::read(MemReqPtr &req, uint8_t *data)
{
- Addr daddr = req->paddr - (addr & PA_IMPL_MASK);
+ Addr daddr = req->paddr - (addr & EV5::PAddrImplMask);
DPRINTF(Uart, " read register %#x\n", daddr);
switch (daddr) {
case 0x0:
if (!(LCR & 0x80)) { // read byte
- //assert(cons->dataAvailable());
if (cons->dataAvailable())
cons->in(*data);
else {
// A limited amount of these are ok.
DPRINTF(Uart, "empty read of RX register\n");
}
+ status &= ~RX_INT;
+ platform->clearConsoleInt();
- if (cons->dataAvailable())
- platform->postConsoleInt();
- else
- {
- status &= ~RX_INT;
- platform->clearConsoleInt();
- }
+ if (cons->dataAvailable() && (IER & UART_IER_RDI))
+ rxIntrEvent.scheduleIntr();
} else { // dll divisor latch
;
}
}
break;
case 0x2: // Intr Identification Register (IIR)
+ DPRINTF(Uart, "IIR Read, status = %#x\n", (uint32_t)status);
if (status)
- *(uint8_t*)data = 1;
- else
*(uint8_t*)data = 0;
+ else
+ *(uint8_t*)data = 1;
break;
case 0x3: // Line Control Register (LCR)
*(uint8_t*)data = LCR;
Fault
Uart::write(MemReqPtr &req, const uint8_t *data)
{
- Addr daddr = req->paddr - (addr & PA_IMPL_MASK);
+ Addr daddr = req->paddr - (addr & EV5::PAddrImplMask);
DPRINTF(Uart, " write register %#x value %#x\n", daddr, *(uint8_t*)data);
switch (daddr) {
case 0x0:
if (!(LCR & 0x80)) { // write byte
- cons->out(*(uint64_t *)data);
+ cons->out(*(uint8_t *)data);
platform->clearConsoleInt();
status &= ~TX_INT;
if (UART_IER_THRI & IER)
- intrEvent.scheduleIntr();
+ txIntrEvent.scheduleIntr();
} else { // dll divisor latch
;
}
case 0x1:
if (!(LCR & 0x80)) { // Intr Enable Register(IER)
IER = *(uint8_t*)data;
- if ((UART_IER_THRI & IER) || ((UART_IER_RDI & IER) && cons->dataAvailable()))
- platform->postConsoleInt();
- else
+ if (UART_IER_THRI & IER)
{
- platform->clearConsoleInt();
- if (intrEvent.scheduled())
- intrEvent.deschedule();
-
+ DPRINTF(Uart, "IER: IER_THRI set, scheduling TX intrrupt\n");
+ txIntrEvent.scheduleIntr();
}
- if (!(UART_IER_THRI & IER))
+ else
+ {
+ DPRINTF(Uart, "IER: IER_THRI cleared, descheduling TX intrrupt\n");
+ if (txIntrEvent.scheduled())
+ txIntrEvent.deschedule();
+ if (status & TX_INT)
+ platform->clearConsoleInt();
status &= ~TX_INT;
- if (!((UART_IER_RDI & IER) && cons->dataAvailable()))
+ }
+
+ if ((UART_IER_RDI & IER) && cons->dataAvailable()) {
+ DPRINTF(Uart, "IER: IER_RDI set, scheduling RX intrrupt\n");
+ rxIntrEvent.scheduleIntr();
+ } else {
+ DPRINTF(Uart, "IER: IER_RDI cleared, descheduling RX intrrupt\n");
+ if (rxIntrEvent.scheduled())
+ rxIntrEvent.deschedule();
+ if (status & RX_INT)
+ platform->clearConsoleInt();
status &= ~RX_INT;
+ }
} else { // DLM divisor latch MSB
;
}
Tick
Uart::cacheAccess(MemReqPtr &req)
{
- return curTick + 1000;
+ return curTick + pioLatency;
}
void
SERIALIZE_SCALAR(DLAB);
SERIALIZE_SCALAR(LCR);
SERIALIZE_SCALAR(MCR);
- Tick intrwhen;
- if (intrEvent.scheduled())
- intrwhen = intrEvent.when();
+ Tick rxintrwhen;
+ if (rxIntrEvent.scheduled())
+ rxintrwhen = rxIntrEvent.when();
+ else
+ rxintrwhen = 0;
+ Tick txintrwhen;
+ if (txIntrEvent.scheduled())
+ txintrwhen = txIntrEvent.when();
else
- intrwhen = 0;
- SERIALIZE_SCALAR(intrwhen);
+ txintrwhen = 0;
+ SERIALIZE_SCALAR(rxintrwhen);
+ SERIALIZE_SCALAR(txintrwhen);
#endif
}
UNSERIALIZE_SCALAR(DLAB);
UNSERIALIZE_SCALAR(LCR);
UNSERIALIZE_SCALAR(MCR);
- Tick intrwhen;
- UNSERIALIZE_SCALAR(intrwhen);
- if (intrwhen != 0)
- intrEvent.schedule(intrwhen);
+ Tick rxintrwhen;
+ Tick txintrwhen;
+ UNSERIALIZE_SCALAR(rxintrwhen);
+ UNSERIALIZE_SCALAR(txintrwhen);
+ if (rxintrwhen != 0)
+ rxIntrEvent.schedule(rxintrwhen);
+ if (txintrwhen != 0)
+ txIntrEvent.schedule(txintrwhen);
#endif
}
Param<Addr> addr;
Param<Addr> size;
SimObjectParam<Bus*> io_bus;
+ Param<Tick> pio_latency;
SimObjectParam<HierParams *> hier;
INIT_PARAM(addr, "Device Address"),
INIT_PARAM_DFLT(size, "Device size", 0x8),
INIT_PARAM_DFLT(io_bus, "The IO Bus to attach to", NULL),
+ INIT_PARAM_DFLT(pio_latency, "Programmed IO latency in bus cycles", 1),
INIT_PARAM_DFLT(hier, "Hierarchy global variables", &defaultHierParams)
END_INIT_SIM_OBJECT_PARAMS(Uart)
CREATE_SIM_OBJECT(Uart)
{
return new Uart(getInstanceName(), console, mmu, addr, size, hier, io_bus,
- platform);
+ pio_latency, platform);
}
REGISTER_SIM_OBJECT("Uart", Uart)
projects / gem5.git / blobdiff