}
Uart::Uart(const string &name, SimConsole *c, MemoryController *mmu, Addr a,
- Addr s, HierParams *hier, Bus *bus, Platform *p)
+ Addr s, HierParams *hier, Bus *bus, Tick pio_latency, Platform *p)
: PioDevice(name), addr(a), size(s), cons(c), txIntrEvent(this, TX_INT),
rxIntrEvent(this, RX_INT), platform(p)
{
- mmu->add_child(this, Range<Addr>(addr, addr + size));
+ mmu->add_child(this, RangeSize(addr, size));
if (bus) {
pioInterface = newPioInterface(name, hier, bus, this,
&Uart::cacheAccess);
- pioInterface->addAddrRange(addr, addr + size - 1);
+ pioInterface->addAddrRange(RangeSize(addr, size));
+ pioLatency = pio_latency * bus->clockRatio;
}
readAddr = 0;
switch (daddr) {
case 0x0:
if (!(LCR & 0x80)) { // write byte
- cons->out(*(uint64_t *)data);
+ cons->out(*(uint8_t *)data);
platform->clearConsoleInt();
status &= ~TX_INT;
if (UART_IER_THRI & IER)
Tick
Uart::cacheAccess(MemReqPtr &req)
{
- return curTick + 1000;
+ return curTick + pioLatency;
}
void
if (txIntrEvent.scheduled())
txintrwhen = txIntrEvent.when();
else
- rxintrwhen = 0;
+ txintrwhen = 0;
SERIALIZE_SCALAR(rxintrwhen);
SERIALIZE_SCALAR(txintrwhen);
#endif
Param<Addr> addr;
Param<Addr> size;
SimObjectParam<Bus*> io_bus;
+ Param<Tick> pio_latency;
SimObjectParam<HierParams *> hier;
INIT_PARAM(addr, "Device Address"),
INIT_PARAM_DFLT(size, "Device size", 0x8),
INIT_PARAM_DFLT(io_bus, "The IO Bus to attach to", NULL),
+ INIT_PARAM_DFLT(pio_latency, "Programmed IO latency in bus cycles", 1),
INIT_PARAM_DFLT(hier, "Hierarchy global variables", &defaultHierParams)
END_INIT_SIM_OBJECT_PARAMS(Uart)
CREATE_SIM_OBJECT(Uart)
{
return new Uart(getInstanceName(), console, mmu, addr, size, hier, io_bus,
- platform);
+ pio_latency, platform);
}
REGISTER_SIM_OBJECT("Uart", Uart)