Merge zizzer:/bk/m5 into zeep.eecs.umich.edu:/z/saidi/work/m5-smp
[gem5.git] / dev / uart.cc
index 8ba59579dc0050de6a5dba2eeccb087128a99d2d..b71ab2d448fa9b278bb7c6240950c221cf48a049 100644 (file)
@@ -92,13 +92,13 @@ Uart::Uart(const string &name, SimConsole *c, MemoryController *mmu, Addr a,
     : PioDevice(name), addr(a), size(s), cons(c), txIntrEvent(this, TX_INT),
       rxIntrEvent(this, RX_INT), platform(p)
 {
-    mmu->add_child(this, Range<Addr>(addr, addr + size));
+    mmu->add_child(this, RangeSize(addr, size));
 
 
     if (bus) {
         pioInterface = newPioInterface(name, hier, bus, this,
                                       &Uart::cacheAccess);
-        pioInterface->addAddrRange(addr, addr + size - 1);
+        pioInterface->addAddrRange(RangeSize(addr, size));
         pioLatency = pio_latency * bus->clockRatio;
     }
 
@@ -287,7 +287,7 @@ Uart::write(MemReqPtr &req, const uint8_t *data)
     switch (daddr) {
         case 0x0:
             if (!(LCR & 0x80)) { // write byte
-                cons->out(*(uint64_t *)data);
+                cons->out(*(uint8_t *)data);
                 platform->clearConsoleInt();
                 status &= ~TX_INT;
                 if (UART_IER_THRI & IER)
@@ -395,7 +395,7 @@ Uart::serialize(ostream &os)
     if (txIntrEvent.scheduled())
         txintrwhen = txIntrEvent.when();
     else
-        rxintrwhen = 0;
+        txintrwhen = 0;
      SERIALIZE_SCALAR(rxintrwhen);
      SERIALIZE_SCALAR(txintrwhen);
 #endif