JTAG UART example correction

[libreriscv.git] / docs / pinmux.mdwn

diff --git a/docs/pinmux.mdwn b/docs/pinmux.mdwn
index 8d14217801aa54957d88a5c0302a0ded7c531161..018a41fa23a63061cfd141098b8c3c9a3c01a218 100644 (file)
--- a/docs/pinmux.mdwn
+++ b/docs/pinmux.mdwn
@@ -7,6 +7,7 @@ Links:
 * <https://ftp.libre-soc.org/Pin_Control_Subsystem_Overview.pdf>
 * <https://bugs.libre-soc.org/show_bug.cgi?id=50>
 * <https://git.libre-soc.org/?p=c4m-jtag.git;a=tree;hb=HEAD>
+* Extra info: [[/docs/pinmux/temp_pinmux_info]]
 
 Managing IO on an ASIC is nowhere near as simple as on an FPGA.
 An FPGA has built-in IO Pads, the wires terminate inside an
@@ -291,8 +292,8 @@ the Blinky example, wire up a JTAG instance:
           m.d.comb += intermediary.eq(urx.core.i) # pass rx to tx
 
           # wire up the IO Pads (in right direction) to Platform
-          m.d.comb += uart.tx.eq(utx.pad.i) # transmit JTAG to pad
-          m.d.comb += utx.pad.o.eq(uart.rx) # pass rx to JTAG
+          m.d.comb += uart.rx.eq(utx.pad.i) # receive rx from JTAG input pad
+          m.d.comb += utx.pad.o.eq(uart.tx) # transmit tx to JTAG output pad
           return m
 
 Compared to the non-scan-capable version, which connected UART