(no commit message)

[libreriscv.git] / docs / pinmux.mdwn

diff --git a/docs/pinmux.mdwn b/docs/pinmux.mdwn
index c603e0357571d59acc37b705134a84a4b426d637..0a6b4197163f5b854eba99773d9635d099989f13 100644 (file)
--- a/docs/pinmux.mdwn
+++ b/docs/pinmux.mdwn
@@ -6,6 +6,7 @@ Links:
 * <https://www10.edacafe.com/book/ASIC/CH02/CH02.7.php>
 * <https://ftp.libre-soc.org/Pin_Control_Subsystem_Overview.pdf>
 * <https://bugs.libre-soc.org/show_bug.cgi?id=50>
+* <https://bugs.libre-soc.org/show_bug.cgi?id=750>
 * <https://git.libre-soc.org/?p=c4m-jtag.git;a=tree;hb=HEAD>
 * Extra info: [[/docs/pinmux/temp_pinmux_info]]
 
@@ -18,6 +19,11 @@ out-enable) to be routed right the way from the ASIC, all
 the way to the IO PAD, where only then does a wire bond connect
 it to a single external pin.
 
+Below, therefore is a (simplified) diagram of what is
+usually contained in an FPGA's bi-directional IO Pad,
+and consequently this is what you must also provide, and explicitly
+wire up in your ASIC's HDL.
+
 [[!img asic_iopad_gen.svg]]
 
 Designing an ASIC, there is no guarantee that the IO pad is
@@ -260,9 +266,9 @@ It is then your responsibility to:
 * connect up each and every peripheral input and output
   to the right IO Core Record in your HDL
 * connect up each and every IO Pad input and output
-  to the right IO Pad in the Platform. **This
-  does not happen automatically and is not the
-  responsibility of the TAP Interface*
+  to the right IO Pad in the Platform.
+* **This does not happen automatically and is not the
+  responsibility of the TAP Interface, it is yours**
 
 The TAP interface connects the **other** side of the pads
 and cores Records: **to the Muxes**.  You **have** to
@@ -410,7 +416,8 @@ there will be a lag on the output data compared to the incoming
 
 # Pinmux GPIO Block
 The following diagram is an example of a GPIO block with switchable banks and comes from the Ericson presentation on a GPIO architecture.
-[[!img gpio-block.svg ]]
+
+[[!img gpio-block.svg size="800x"]]
 
 The block we are developing is very similar, but is lacking some of configuration of the former (due to complexity and time constraints).
 
@@ -483,16 +490,15 @@ The 32-bit on the other hand has four address rows, and so will take four write
 
 64-bit:
 
-* 0x00 - Configure GPIOs  0-7
-* 0x01 - Configure GPIOs  8-15
+* 0x00 - Configure GPIOs  0-7  - requires 8-bit `sel` one bit per GPIO
+* 0x01 - Configure GPIOs  8-15 - requires 8-bit `sel` one bit per GPIO
 
 32-bit:
 
-* 0x00 - Configure GPIOs  0-3
-* 0x01 - Configure GPIOs  4-7
-* 0x02 - Configure GPIOs  8-11
-* 0x03 - Configure GPIOs 12-15
-
+* 0x00 - Configure GPIOs  0-3 - requires 4-bit `sel` one bit per GPIO
+* 0x01 - Configure GPIOs  4-7 - requires 4-bit `sel` one bit per GPIO
+* 0x02 - Configure GPIOs  8-11 - requires 4-bit `sel` one bit per GPIO
+* 0x03 - Configure GPIOs 12-15 - requires 4-bit `sel` one bit per GPIO
 
 ## Combining JTAG BS Chain and Pinmux (In Progress)
 [[!img io_mux_bank_planning.JPG size="600x"]]