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[libreriscv.git] / docs.mdwn

diff --git a/docs.mdwn b/docs.mdwn
index e1e40263c7c66591f5549e0dbe904ff449a008bc..0bdef1267c0c7ed6cf54c0b10680638cf3e44ab7 100644 (file)
--- a/docs.mdwn
+++ b/docs.mdwn
@@ -12,7 +12,7 @@ construction of FSMs and arbitrary length pipelines.
 
 | Git Repo | Documentation | Description   | Pypi    |
 |----------|---------------|---------------|--------
-| [SOC](https://git.libre-soc.org/?p=soc.git;a=tree) | [Libre-SOC](https://docs.libre-soc.org/soc/) | Main OpenPOWER Hybrid CPU-GPU | |
+| [SOC](https://git.libre-soc.org/?p=soc.git;a=tree) | [Libre-SOC](https://docs.libre-soc.org/soc/) | Main OpenPOWER Hybrid CPU-GPU | TBD |
 | [FPU](https://git.libre-soc.org/?p=ieee754fpu.git;a=tree) | -- | Equivalent to hardfloat-3 | [libresoc-ieee754fpu](https://pypi.org/project/libresoc-ieee754fpu) |
 | [nmutil](https://git.libre-soc.org/?p=nmutil.git;a=tree) | -- | Equivalent to Chisel3.util | [libresoc-nmutil](https://pypi.org/project/libresoc-nmutil) |
 | [OpenPOWER ISA](https://git.libre-soc.org/?p=nmutil.git;a=tree) | [OpenPOWER ISA](https://docs.libre-soc.org/openpower-isa/) | Simulator, ISA spec compiler, co-simulation infrastructure |  [libresoc-openpower-isa](https://pypi.org/project/libresoc-openpower-isa/)  |