Merge pull request #3 from YosysHQ/master

[yosys.git] / examples / basys3 / example.xdc

diff --git a/examples/basys3/example.xdc b/examples/basys3/example.xdc
index c1fd0e925ee9d745ab9bc031ecbd565f2ea7d2da..8cdaa19964e6b089a9f4f6d316dd6570c5ab32a2 100644 (file)
--- a/examples/basys3/example.xdc
+++ b/examples/basys3/example.xdc
@@ -19,3 +19,6 @@ set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN L1  } [get_ports {LD[15]}]
 
 create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports CLK]
 
+set_property CONFIG_VOLTAGE 3.3 [current_design]
+set_property CFGBVS VCCO [current_design]
+