fhdl.dsl: comb/sync/sync.pix→d.comb/d.sync/d.pix.

[nmigen.git] / examples / ctrl.py

diff --git a/examples/ctrl.py b/examples/ctrl.py
index 9e6d76c7065fb71ff00f2f372d7770f20495eaf6..2d8fcf87121cdce35cf2b5acc2897a387b417cb2 100644 (file)
--- a/examples/ctrl.py
+++ b/examples/ctrl.py
@@ -9,14 +9,14 @@ class ClockDivisor:
         self.ce = Signal()
 
     def get_fragment(self, platform):
-        f = Module()
-        f.sync += self.v.eq(self.v + 1)
-        f.comb += self.o.eq(self.v[-1])
-        return CEInserter(self.ce)(f.lower())
+        m = Module()
+        m.d.sync += self.v.eq(self.v + 1)
+        m.d.comb += self.o.eq(self.v[-1])
+        return CEInserter(self.ce)(m.lower(platform))
 
 
-sys  = ClockDomain()
+sync = ClockDomain()
 ctr  = ClockDivisor(factor=16)
 frag = ctr.get_fragment(platform=None)
-# print(rtlil.convert(frag, ports=[sys.clk, ctr.o, ctr.ce], clock_domains={"sys": sys}))
-print(verilog.convert(frag, ports=[sys.clk, ctr.o, ctr.ce], clock_domains={"sys": sys}))
+# print(rtlil.convert(frag, ports=[sync.clk, ctr.o, ctr.ce], clock_domains={"sync": sync}))
+print(verilog.convert(frag, ports=[sync.clk, ctr.o, ctr.ce], clock_domains={"sync": sync}))