gram.test.test_core_bankmachine: Reduce formal test depth

[gram.git] / examples / soc.py

diff --git a/examples/soc.py b/examples/soc.py
index b43e95e649e32116c2f380066dcdc05f0c16fbee..4c317b995806a6680944018c89a3aa0490895527 100644 (file)
--- a/examples/soc.py
+++ b/examples/soc.py
@@ -17,7 +17,7 @@ from gram.phy.ecp5ddrphy import ECP5DDRPHY
 from gram.modules import MT41K256M16
 from gram.frontend.wishbone import gramWishbone
 
-from ecpix5_85 import ECPIX585Platform
+from nmigen_boards.ecpix5 import *
 from uartbridge import UARTBridge
 from crg import *
 
@@ -31,6 +31,8 @@ class DDR3SoC(SoC, Elaboratable):
         self._decoder = wishbone.Decoder(addr_width=30, data_width=32, granularity=8,
                                          features={"cti", "bte"})
 
+        freq = 100e6
+
         self.crg = ECPIX5CRG()
 
         self.cpu = MinervaCPU(reset_address=0)
@@ -48,20 +50,20 @@ class DDR3SoC(SoC, Elaboratable):
         self.ram = SRAMPeripheral(size=4096)
         self._decoder.add(self.ram.bus, addr=0x1000)
 
-        self.uart = AsyncSerialPeripheral(divisor=100000000//115200, pins=uart_pins)
+        self.uart = AsyncSerialPeripheral(divisor=int(freq//115200), pins=uart_pins)
         self._decoder.add(self.uart.bus, addr=0x2000)
 
         
         self.ddrphy = DomainRenamer("dramsync")(ECP5DDRPHY(ddr_pins))
         self._decoder.add(self.ddrphy.bus, addr=ddrphy_addr)
 
-        ddrmodule = MT41K256M16(platform.default_clk_frequency, "1:2")
+        ddrmodule = MT41K256M16(freq, "1:2")
 
         self.dramcore = DomainRenamer("dramsync")(gramCore(
             phy=self.ddrphy,
             geom_settings=ddrmodule.geom_settings,
             timing_settings=ddrmodule.timing_settings,
-            clk_freq=platform.default_clk_frequency))
+            clk_freq=freq))
         self._decoder.add(self.dramcore.bus, addr=dramcore_addr)
 
         self.drambone = DomainRenamer("dramsync")(gramWishbone(self.dramcore))
@@ -69,7 +71,7 @@ class DDR3SoC(SoC, Elaboratable):
 
         self.memory_map = self._decoder.bus.memory_map
 
-        self.clk_freq = platform.default_clk_frequency
+        self.clk_freq = freq
 
     def elaborate(self, platform):
         m = Module()