Fix some ghdlsynth issues with fpga_bram

[microwatt.git] / fpga / nexys_a7.xdc

diff --git a/fpga/nexys_a7.xdc b/fpga/nexys_a7.xdc
index 09a08d955328046dc2512b7a56e71e89c59de804..a572772e6e144dbf7fa464ab5601ebd3bb95cd5e 100644 (file)
--- a/fpga/nexys_a7.xdc
+++ b/fpga/nexys_a7.xdc
@@ -5,3 +5,10 @@ set_property -dict {PACKAGE_PIN C12 IOSTANDARD LVCMOS33} [get_ports ext_rst]
 
 set_property -dict {PACKAGE_PIN D4 IOSTANDARD LVCMOS33} [get_ports uart0_txd]
 set_property -dict {PACKAGE_PIN C4 IOSTANDARD LVCMOS33} [get_ports uart0_rxd]
+
+set_property CONFIG_VOLTAGE 3.3 [current_design]
+set_property CFGBVS VCCO [current_design]
+
+set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
+set_property BITSTREAM.CONFIG.CONFIGRATE 33 [current_design]
+set_property CONFIG_MODE SPIx4 [current_design]