mw_debug: Fix memory overflow with "sim" backend

[microwatt.git] / fpga / top-nexys-video.vhdl

diff --git a/fpga/top-nexys-video.vhdl b/fpga/top-nexys-video.vhdl
index c0e3659261d878a484338b7f48bc1edc4c93e804..9acbee144af097aed62bce73362e9223af20b12b 100644 (file)
--- a/fpga/top-nexys-video.vhdl
+++ b/fpga/top-nexys-video.vhdl
@@ -57,11 +57,15 @@ architecture behaviour of toplevel is
     signal system_clk : std_ulogic;
     signal system_clk_locked : std_ulogic;
 
-    -- DRAM wishbone connection
-    signal wb_dram_in   : wishbone_master_out;
-    signal wb_dram_out  : wishbone_slave_out;
-    signal wb_dram_csr  : std_ulogic;
-    signal wb_dram_init : std_ulogic;
+    -- DRAM main data wishbone connection
+    signal wb_dram_in       : wishbone_master_out;
+    signal wb_dram_out      : wishbone_slave_out;
+
+    -- DRAM control wishbone connection
+    signal wb_dram_ctrl_in  : wb_io_master_out;
+    signal wb_dram_ctrl_out : wb_io_slave_out;
+    signal wb_dram_is_csr   : std_ulogic;
+    signal wb_dram_is_init  : std_ulogic;
 
     -- Control/status
     signal core_alt_reset : std_ulogic;
@@ -87,8 +91,10 @@ begin
            uart0_rxd         => uart_main_rx,
            wb_dram_in        => wb_dram_in,
            wb_dram_out       => wb_dram_out,
-           wb_dram_csr       => wb_dram_csr,
-           wb_dram_init      => wb_dram_init,
+           wb_dram_ctrl_in   => wb_dram_ctrl_in,
+           wb_dram_ctrl_out  => wb_dram_ctrl_out,
+           wb_dram_is_csr    => wb_dram_is_csr,
+           wb_dram_is_init   => wb_dram_is_init,
            alt_reset         => core_alt_reset
            );
 
@@ -140,8 +146,7 @@ begin
     has_dram: if USE_LITEDRAM generate
        signal dram_init_done  : std_ulogic;
        signal dram_init_error : std_ulogic;
-       signal soc_rst_0       : std_ulogic;
-       signal soc_rst_1       : std_ulogic;
+       signal dram_sys_rst    : std_ulogic;
     begin
 
        -- Eventually dig out the frequency from the generator
@@ -150,15 +155,17 @@ begin
 
        reset_controller: entity work.soc_reset
            generic map(
-               RESET_LOW => RESET_LOW
+               RESET_LOW => RESET_LOW,
+                PLL_RESET_BITS => 18,
+                SOC_RESET_BITS => 1
                )
            port map(
                ext_clk => ext_clk,
                pll_clk => system_clk,
-               pll_locked_in => system_clk_locked,
+               pll_locked_in => '1',
                ext_rst_in => ext_rst,
                pll_rst_out => pll_rst,
-               rst_out => soc_rst_0
+               rst_out => open
                );
 
        dram: entity work.litedram_wrapper
@@ -170,13 +177,15 @@ begin
                clk_in          => ext_clk,
                rst             => pll_rst,
                system_clk      => system_clk,
-               system_reset    => soc_rst_1,
+               system_reset    => soc_rst,
                pll_locked      => system_clk_locked,
 
                wb_in           => wb_dram_in,
                wb_out          => wb_dram_out,
-               wb_is_csr       => wb_dram_csr,
-               wb_is_init      => wb_dram_init,
+               wb_ctrl_in      => wb_dram_ctrl_in,
+               wb_ctrl_out     => wb_dram_ctrl_out,
+               wb_ctrl_is_csr  => wb_dram_is_csr,
+               wb_ctrl_is_init => wb_dram_is_init,
 
                serial_tx       => open,
                serial_rx       => '0',
@@ -203,7 +212,6 @@ begin
 
        led0 <= dram_init_done and not dram_init_error;
        led1 <= dram_init_error; -- Make it blink ?
-       soc_rst <= soc_rst_0 or soc_rst_1;
 
     end generate;
 end architecture behaviour;