AST_TO_BITS,
AST_TO_SIGNED,
AST_TO_UNSIGNED,
+ AST_SELFSZ,
+ AST_CAST_SIZE,
AST_CONCAT,
AST_REPLICATE,
AST_BIT_NOT,
AST_SHIFT_RIGHT,
AST_SHIFT_SLEFT,
AST_SHIFT_SRIGHT,
+ AST_SHIFTX,
+ AST_SHIFT,
AST_LT,
AST_LE,
AST_EQ,
AST_GENCASE,
AST_GENBLOCK,
AST_TECALL,
-
+
AST_POSEDGE,
AST_NEGEDGE,
AST_EDGE,
AST_PACKAGE,
AST_WIRETYPE,
- AST_TYPEDEF
+ AST_TYPEDEF,
+ AST_STRUCT,
+ AST_UNION,
+ AST_STRUCT_ITEM
+ };
+
+ struct AstSrcLocType {
+ unsigned int first_line, last_line;
+ unsigned int first_column, last_column;
+ AstSrcLocType() : first_line(0), last_line(0), first_column(0), last_column(0) {}
+ AstSrcLocType(int _first_line, int _first_column, int _last_line, int _last_column) : first_line(_first_line), last_line(_last_line), first_column(_first_column), last_column(_last_column) {}
};
// convert an node type to a string (e.g. for debug output)
// if this is a multirange memory then this vector contains offset and length of each dimension
std::vector<int> multirange_dimensions;
+ std::vector<bool> multirange_swapped; // true if range is swapped, not used for structs
// this is set by simplify and used during RTLIL generation
AstNode *id2ast;
// this is used by simplify to detect if basic analysis has been performed already on the node
bool basic_prep;
+ // this is used for ID references in RHS expressions that should use the "new" value for non-blocking assignments
+ bool lookahead;
+
// this is the original sourcecode location that resulted in this AST node
// it is automatically set by the constructor using AST::current_filename and
// the AST::get_line_num() callback function.
std::string filename;
- int linenum;
+ AstSrcLocType location;
// creating and deleting nodes
AstNode(AstNodeType type = AST_NONE, AstNode *child1 = NULL, AstNode *child2 = NULL, AstNode *child3 = NULL);
// simplify() creates a simpler AST by unrolling for-loops, expanding generate blocks, etc.
// it also sets the id2ast pointers so that identifier lookups are fast in genRTLIL()
bool simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, int width_hint, bool sign_hint, bool in_param);
+ void replace_result_wire_name_in_function(const std::string &from, const std::string &to);
AstNode *readmem(bool is_readmemh, std::string mem_filename, AstNode *memory, int start_addr, int finish_addr, bool unconditional_init);
- void expand_genblock(std::string index_var, std::string prefix, std::map<std::string, std::string> &name_map);
- void replace_ids(const std::string &prefix, const std::map<std::string, std::string> &rules);
+ void expand_genblock(const std::string &prefix);
+ void label_genblks(std::set<std::string>& existing, int &counter);
void mem2reg_as_needed_pass1(dict<AstNode*, pool<std::string>> &mem2reg_places,
dict<AstNode*, uint32_t> &mem2reg_flags, dict<AstNode*, uint32_t> &proc_flags, uint32_t &status_flags);
bool mem2reg_as_needed_pass2(pool<AstNode*> &mem2reg_set, AstNode *mod, AstNode *block, AstNode *&async_block);
bool mem2reg_check(pool<AstNode*> &mem2reg_set);
void mem2reg_remove(pool<AstNode*> &mem2reg_set, vector<AstNode*> &delnodes);
void meminfo(int &mem_width, int &mem_size, int &addr_bits);
+ bool detect_latch(const std::string &var);
// additional functionality for evaluating constant functions
struct varinfo_t { RTLIL::Const val; int offset; bool is_signed; };
bool has_const_only_constructs(bool &recommend_const_eval);
+ bool has_const_only_constructs(std::set<std::string>& visited, bool &recommend_const_eval);
void replace_variables(std::map<std::string, varinfo_t> &variables, AstNode *fcall);
AstNode *eval_const_function(AstNode *fcall);
bool is_simple_const_expr();
// helpers for enum
void allocateDefaultEnumValues();
+ void annotateTypedEnums(AstNode *template_node);
};
// process an AST tree (ast must point to an AST_DESIGN node) and generate RTLIL code
struct AstModule : RTLIL::Module {
AstNode *ast;
bool nolatches, nomeminit, nomem2reg, mem2reg, noblackbox, lib, nowb, noopt, icells, pwires, autowire;
- ~AstModule() YS_OVERRIDE;
- RTLIL::IdString derive(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Const> parameters, bool mayfail) YS_OVERRIDE;
- RTLIL::IdString derive(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Const> parameters, dict<RTLIL::IdString, RTLIL::Module*> interfaces, dict<RTLIL::IdString, RTLIL::IdString> modports, bool mayfail) YS_OVERRIDE;
- std::string derive_common(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Const> parameters, AstNode **new_ast_out, bool quiet = false);
- void reprocess_module(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Module *> local_interfaces) YS_OVERRIDE;
- RTLIL::Module *clone() const YS_OVERRIDE;
+ ~AstModule() override;
+ RTLIL::IdString derive(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> ¶meters, bool mayfail) override;
+ RTLIL::IdString derive(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> ¶meters, const dict<RTLIL::IdString, RTLIL::Module*> &interfaces, const dict<RTLIL::IdString, RTLIL::IdString> &modports, bool mayfail) override;
+ std::string derive_common(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> ¶meters, AstNode **new_ast_out, bool quiet = false);
+ void reprocess_module(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Module *> &local_interfaces) override;
+ RTLIL::Module *clone() const override;
void loadconfig() const;
};
extern AST::AstNode *current_always, *current_top_block, *current_block, *current_block_child;
extern AST::AstModule *current_module;
extern bool current_always_clocked;
+ struct LookaheadRewriter;
struct ProcessGenerator;
}
projects / yosys.git / blobdiff