verilog: significant block scoping improvements

[yosys.git] / frontends / ast / ast.h

diff --git a/frontends/ast/ast.h b/frontends/ast/ast.h
index 8932108e3790dd2fbc4b2ffb734a060e1e517d03..6f173ca22f2f11c9bae6cbdf50f0b06040adfe74 100644 (file)
--- a/frontends/ast/ast.h
+++ b/frontends/ast/ast.h
@@ -76,6 +76,7 @@ namespace AST
                AST_TO_SIGNED,
                AST_TO_UNSIGNED,
                AST_SELFSZ,
+               AST_CAST_SIZE,
                AST_CONCAT,
                AST_REPLICATE,
                AST_BIT_NOT,
@@ -143,7 +144,7 @@ namespace AST
                AST_GENCASE,
                AST_GENBLOCK,
                AST_TECALL,
-               
+
                AST_POSEDGE,
                AST_NEGEDGE,
                AST_EDGE,
@@ -156,7 +157,10 @@ namespace AST
                AST_PACKAGE,
 
                AST_WIRETYPE,
-               AST_TYPEDEF
+               AST_TYPEDEF,
+               AST_STRUCT,
+               AST_UNION,
+               AST_STRUCT_ITEM
        };
 
        struct AstSrcLocType {
@@ -198,6 +202,7 @@ namespace AST
 
                // if this is a multirange memory then this vector contains offset and length of each dimension
                std::vector<int> multirange_dimensions;
+               std::vector<bool> multirange_swapped; // true if range is swapped, not used for structs
 
                // this is set by simplify and used during RTLIL generation
                AstNode *id2ast;
@@ -245,19 +250,22 @@ namespace AST
                // simplify() creates a simpler AST by unrolling for-loops, expanding generate blocks, etc.
                // it also sets the id2ast pointers so that identifier lookups are fast in genRTLIL()
                bool simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, int width_hint, bool sign_hint, bool in_param);
+               void replace_result_wire_name_in_function(const std::string &from, const std::string &to);
                AstNode *readmem(bool is_readmemh, std::string mem_filename, AstNode *memory, int start_addr, int finish_addr, bool unconditional_init);
-               void expand_genblock(std::string index_var, std::string prefix, std::map<std::string, std::string> &name_map);
-               void replace_ids(const std::string &prefix, const std::map<std::string, std::string> &rules);
+               void expand_genblock(const std::string &prefix);
+               void label_genblks(std::set<std::string>& existing, int &counter);
                void mem2reg_as_needed_pass1(dict<AstNode*, pool<std::string>> &mem2reg_places,
                                dict<AstNode*, uint32_t> &mem2reg_flags, dict<AstNode*, uint32_t> &proc_flags, uint32_t &status_flags);
                bool mem2reg_as_needed_pass2(pool<AstNode*> &mem2reg_set, AstNode *mod, AstNode *block, AstNode *&async_block);
                bool mem2reg_check(pool<AstNode*> &mem2reg_set);
                void mem2reg_remove(pool<AstNode*> &mem2reg_set, vector<AstNode*> &delnodes);
                void meminfo(int &mem_width, int &mem_size, int &addr_bits);
+               bool detect_latch(const std::string &var);
 
                // additional functionality for evaluating constant functions
                struct varinfo_t { RTLIL::Const val; int offset; bool is_signed; };
                bool has_const_only_constructs(bool &recommend_const_eval);
+               bool has_const_only_constructs(std::set<std::string>& visited, bool &recommend_const_eval);
                void replace_variables(std::map<std::string, varinfo_t> &variables, AstNode *fcall);
                AstNode *eval_const_function(AstNode *fcall);
                bool is_simple_const_expr();
@@ -306,6 +314,7 @@ namespace AST
 
                // helpers for enum
                void allocateDefaultEnumValues();
+               void annotateTypedEnums(AstNode *template_node);
        };
 
        // process an AST tree (ast must point to an AST_DESIGN node) and generate RTLIL code
@@ -317,12 +326,12 @@ namespace AST
        struct AstModule : RTLIL::Module {
                AstNode *ast;
                bool nolatches, nomeminit, nomem2reg, mem2reg, noblackbox, lib, nowb, noopt, icells, pwires, autowire;
-               ~AstModule() YS_OVERRIDE;
-               RTLIL::IdString derive(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> &parameters, bool mayfail) YS_OVERRIDE;
-               RTLIL::IdString derive(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> &parameters, const dict<RTLIL::IdString, RTLIL::Module*> &interfaces, const dict<RTLIL::IdString, RTLIL::IdString> &modports, bool mayfail) YS_OVERRIDE;
+               ~AstModule() override;
+               RTLIL::IdString derive(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> &parameters, bool mayfail) override;
+               RTLIL::IdString derive(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> &parameters, const dict<RTLIL::IdString, RTLIL::Module*> &interfaces, const dict<RTLIL::IdString, RTLIL::IdString> &modports, bool mayfail) override;
                std::string derive_common(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> &parameters, AstNode **new_ast_out, bool quiet = false);
-               void reprocess_module(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Module *> &local_interfaces) YS_OVERRIDE;
-               RTLIL::Module *clone() const YS_OVERRIDE;
+               void reprocess_module(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Module *> &local_interfaces) override;
+               RTLIL::Module *clone() const override;
                void loadconfig() const;
        };