Merge pull request #591 from hzeller/virtual-override

[yosys.git] / frontends / ast / ast.h

diff --git a/frontends/ast/ast.h b/frontends/ast/ast.h
index 756629aca1efdd9946820f4fd8ff1e59ef6d6ec1..d94199643ccb37ddb93bc7cb99d3f3464a35adfa 100644 (file)
--- a/frontends/ast/ast.h
+++ b/frontends/ast/ast.h
@@ -1,4 +1,4 @@
-/*
+/* -*- c++ -*-
  *  yosys -- Yosys Open SYnthesis Suite
  *
  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
@@ -168,7 +168,7 @@ namespace AST
                // node content - most of it is unused in most node types
                std::string str;
                std::vector<RTLIL::State> bits;
-               bool is_input, is_output, is_reg, is_signed, is_string, range_valid, range_swapped;
+               bool is_input, is_output, is_reg, is_logic, is_signed, is_string, range_valid, range_swapped, was_checked;
                int port_id, range_left, range_right;
                uint32_t integer;
                double realvalue;
@@ -282,9 +282,9 @@ namespace AST
        struct AstModule : RTLIL::Module {
                AstNode *ast;
                bool nolatches, nomeminit, nomem2reg, mem2reg, lib, noopt, icells, autowire;
-               virtual ~AstModule();
-               virtual RTLIL::IdString derive(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Const> parameters, bool mayfail);
-               virtual RTLIL::Module *clone() const;
+               ~AstModule() YS_OVERRIDE;
+               RTLIL::IdString derive(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Const> parameters, bool mayfail) YS_OVERRIDE;
+               RTLIL::Module *clone() const YS_OVERRIDE;
        };
 
        // this must be set by the language frontend before parsing the sources