verific: allow memories to be inferred in loops

[yosys.git] / frontends / verific / verific.cc

diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index 44196a3103b8593a4b769d911407e0bef9da4050..b53bad7dace41e368b67991d9b94c023a02b4746 100644 (file)
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -2548,6 +2548,7 @@ struct VerificPass : public Pass {
 
                        RuntimeFlags::SetVar("veri_extract_dualport_rams", 0);
                        RuntimeFlags::SetVar("veri_extract_multiport_rams", 1);
+                       RuntimeFlags::SetVar("veri_allow_any_ram_in_loop", 1);
 
 #ifdef VERIFIC_VHDL_SUPPORT
                        RuntimeFlags::SetVar("vhdl_extract_dualport_rams", 0);