Merge pull request #2023 from YosysHQ/eddie/specify_src

[yosys.git] / frontends / verilog / Makefile.inc

diff --git a/frontends/verilog/Makefile.inc b/frontends/verilog/Makefile.inc
index 6a8462b4189ab968a98235f2095e5da6e72464ec..cf9b9531e49421533d848811e84e87228012b871 100644 (file)
--- a/frontends/verilog/Makefile.inc
+++ b/frontends/verilog/Makefile.inc
@@ -10,7 +10,7 @@ frontends/verilog/verilog_parser.tab.cc: frontends/verilog/verilog_parser.y
 
 frontends/verilog/verilog_parser.tab.hh: frontends/verilog/verilog_parser.tab.cc
 
-frontends/verilog/verilog_lexer.cc: frontends/verilog/verilog_lexer.l
+frontends/verilog/verilog_lexer.cc: frontends/verilog/verilog_lexer.l frontends/verilog/verilog_parser.tab.cc
        $(Q) mkdir -p $(dir $@)
        $(P) flex -o frontends/verilog/verilog_lexer.cc $<