Merge pull request #2023 from YosysHQ/eddie/specify_src

[yosys.git] / frontends / verilog / Makefile.inc

diff --git a/frontends/verilog/Makefile.inc b/frontends/verilog/Makefile.inc
index dbaace5854c9762a5d673274e5a1db2c7b52fa71..cf9b9531e49421533d848811e84e87228012b871 100644 (file)
--- a/frontends/verilog/Makefile.inc
+++ b/frontends/verilog/Makefile.inc
@@ -10,10 +10,12 @@ frontends/verilog/verilog_parser.tab.cc: frontends/verilog/verilog_parser.y
 
 frontends/verilog/verilog_parser.tab.hh: frontends/verilog/verilog_parser.tab.cc
 
-frontends/verilog/verilog_lexer.cc: frontends/verilog/verilog_lexer.l
+frontends/verilog/verilog_lexer.cc: frontends/verilog/verilog_lexer.l frontends/verilog/verilog_parser.tab.cc
        $(Q) mkdir -p $(dir $@)
        $(P) flex -o frontends/verilog/verilog_lexer.cc $<
 
+frontends/verilog/verilog_parser.tab.o: CXXFLAGS += -DYYMAXDEPTH=10000000
+
 OBJS += frontends/verilog/verilog_parser.tab.o
 OBJS += frontends/verilog/verilog_lexer.o
 OBJS += frontends/verilog/preproc.o