Merge pull request #3014 from YosysHQ/claire/fix-vgtest

[yosys.git] / frontends / verilog / verilog_parser.y

diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index 80b40f9826f60c056ba60c8b929b40dc3c606ab8..5eb1115ce9abd22ef814867fa1de3fc13a6769a8 100644 (file)
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -2677,6 +2677,7 @@ for_initialization:
                AstNode *node = new AstNode(AST_ASSIGN_EQ, ident, $3);
                ast_stack.back()->children.push_back(node);
                SET_AST_NODE_LOC(node, @1, @3);
+               delete $1;
        } |
        non_io_wire_type range TOK_ID {
                frontend_verilog_yyerror("For loop variable declaration is missing initialization!");