+2019-02-10 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR gas/24165
+ * frags.c (frag_var_init): Pass max_chars to TC_FRAG_INIT as
+ max_bytes.
+ * config/tc-aarch64.h (TC_FRAG_INIT): Add and pass max_bytes to
+ aarch64_init_frag.
+ * /config/tc-arm.h (TC_FRAG_INIT): And and pass max_bytes to
+ arm_init_frag.
+ * config/tc-avr.h (TC_FRAG_INIT): And and ignore max_bytes.
+ * config/tc-ia64.h (TC_FRAG_INIT): Likewise.
+ * config/tc-mmix.h (TC_FRAG_INIT): Likewise.
+ * config/tc-nds32.h (TC_FRAG_INIT): Likewise.
+ * config/tc-ns32k.h (TC_FRAG_INIT): Likewise.
+ * config/tc-rl78.h (TC_FRAG_INIT): Likewise.
+ * config/tc-rx.h (TC_FRAG_INIT): Likewise.
+ * config/tc-score.h (TC_FRAG_INIT): Likewise.
+ * config/tc-tic54x.h (TC_FRAG_INIT): Likewise.
+ * config/tc-tic6x.h (TC_FRAG_INIT): Likewise.
+ * config/tc-xtensa.h (TC_FRAG_INIT): Likewise.
+ * config/tc-i386.h (MAX_MEM_FOR_RS_ALIGN_CODE): Set to
+ (alignment ? ((1 << alignment) - 1) : 1)
+ (i386_tc_frag_data): Add max_bytes.
+ (TC_FRAG_INIT): Add and track max_bytes.
+ (HANDLE_ALIGN): Replace MAX_MEM_FOR_RS_ALIGN_CODE with
+ fragP->tc_frag_data.max_bytes.
+ * doc/internals.texi: Update TC_FRAG_TYPE with max_bytes.
+
+2019-02-08 Jim Wilson <jimw@sifive.com>
+
+ * config/tc-riscv.c (validate_riscv_insn) <'C'>: Add 'z' support.
+ (riscv_ip) <'C'>: Add 'z' support.
+
+2019-02-07 Tamar Christina <tamar.christina@arm.com>
+
+ * config/tc-arm.c (insns): Redefine THUMB_VARIANT and ARM_VARIANT for
+ hlt to armv1.
+ * testsuite/gas/arm/armv8a-automatic-hlt.d: Update TAGs
+ * testsuite/gas/arm/hlt.d: New test.
+ * testsuite/gas/arm/hlt.s: New test.
+
+2019-02-07 Tamar Christina <tamar.christina@arm.com>
+
+ * testsuite/gas/aarch64/undefined_advsimd_armv8_3.d: New test.
+ * testsuite/gas/aarch64/undefined_advsimd_armv8_3.s: New test.
+
+2019-02-07 Tamar Christina <tamar.christina@arm.com>
+
+ PR binutils/23212
+ * testsuite/gas/aarch64/undefined_by_elem_sz_l.s: New test.
+ * testsuite/gas/aarch64/undefined_by_elem_sz_l.d: New test.
+
+2019-02-07 Eric Botcazou <ebotcazou@adacore.com>
+
+ * config/tc-visium.c (md_assemble) <mode_cad>: Align instruction on
+ 64-bit boundaries for the GR6.
+ * testsuite/gas/visium/allinsn_gr6.s: Tweak.
+ * testsuite/gas/visium/allinsn_gr6.d: Likewise.
+ * testsuite/gas/visium/bra-1.d: New test.
+ * testsuite/gas/visium/bra-1.s: Likewise.
+ * testsuite/gas/visium/visium.exp: Run bra-1 test.
+
+2019-01-31 John Darrington <john@darrington.wattle.id.au>
+
+ * config/tc-s12z.c (lex_imm): Add new argument exp_o.
+ (emit_reloc): New function.
+ (md_apply_fix): [BFD_RELOC_S12Z_OPR] Recognise that it
+ can be either 2 bytes or 3 bytes long.
+ * testsuite/gas/s12z/mov-imm-reloc.d: New file.
+ * testsuite/gas/s12z/mov-imm-reloc.s: New file.
+ * testsuite/gas/s12z/s12z.exp: Add them.
+
+2019-01-31 John Darrington <john@darrington.wattle.id.au>
+
+ * config/tc-s12z.c (md_apply_fix): Fix incorrect limits.
+ * testsuite/gas/s12z/pc-rel-bad.d: New file.
+ * testsuite/gas/s12z/pc-rel-bad.l: New file.
+ * testsuite/gas/s12z/pc-rel-bad.s: New file.
+ * testsuite/gas/s12z/pc-rel-good.d: New file.
+ * testsuite/gas/s12z/pc-rel-good.s: New file.
+ * testsuite/gas/s12z/s12z.exp: Add them.
+
+2019-01-31 John Darrington <john@darrington.wattle.id.au>
+
+ * config/tc-s12z.c (tfr): Emit warning if operands are the same.
+ * testsuite/gas/s12z/exg.d: New test case.
+ * testsuite/gas/s12z/exg.l: New file.
+
+2019-01-31 John Darrington <john@darrington.wattle.id.au>
+
+ * config/tc-s12z.c (lex_opr): Add a parameter to indicate whether
+ immediate mode operands should be permitted.
+ * testsuite/s12z/imm-dest.d: New file.
+ * testsuite/s12z/imm-dest.l: New file.
+ * testsuite/s12z/imm-dest.s: New file.
+ * testsuite/s12z/s12z.exp: Add them.
+
+2019-01-31 Andreas Krebbel <krebbel@linux.ibm.com>
+
+ * config/tc-s390.c (s390_parse_cpu): New entry for arch13.
+ * doc/c-s390.texi: Document arch13 march option.
+ * testsuite/gas/s390/s390.exp: Run the arch13 related tests.
+ * testsuite/gas/s390/zarch-arch13.d: New test.
+ * testsuite/gas/s390/zarch-arch13.s: New test.
+ * testsuite/gas/s390/zarch-z13.d: Expect the renamed mnemonics
+ also for z13.
+
+2019-01-31 Alan Modra <amodra@gmail.com>
+
+ * config/tc-alpha.c (md_apply_fix): Correct range checks for
+ BFD_RELOC_ALPHA_NOP, BFD_RELOC_ALPHA_LDA, BFD_RELOC_ALPHA_BSR.
+ * config/tc-arm.c (md_apply_fix): Use llabs rather than abs.
+ * config/tc-csky.c (get_macro_reg_vals): Pass s to csky_show_error.
+
+2019-01-28 Max Filippov <jcmvbkbc@gmail.com>
+
+ * config/tc-xtensa.c (md_apply_fix): Mark fixups for constant
+ symbols as done in md_apply_fix.
+ * testsuite/gas/all/forward.d: Don't XFAIL for xtensa.
+
+2019-01-28 Nick Clifton <nickc@redhat.com>
+
+ * po/fr.po: Updated French translation.
+ * po/ru.po: Updated Russian translation.
+
+2019-01-28 Alan Modra <amodra@gmail.com>
+
+ * configure.ac (ac_checking): Set from bfd/development.sh
+ development variable.
+ * configure: Regenerate.
+
+2019-01-25 Sudakshina Das <sudi.das@arm.com>
+
+ * config/tc-aarch64.c (warn_unpredictable_ldst): Exempt
+ stg, st2g, stzg and stz2g from Xt == Xn with writeback warning.
+ * testsuite/gas/aarch64/armv8_5-a-memtag.d: Change tests for
+ stg, stzg, st2g and stz2g.
+ * testsuite/gas/aarch64/armv8_5-a-memtag.s: Likewise.
+ * testsuite/gas/aarch64/illegal-memtag.l: Likewise.
+ * testsuite/gas/aarch64/illegal-memtag.s: Likewise.
+
+2019-01-25 Sudakshina Das <sudi.das@arm.com>
+
+ * testsuite/gas/aarch64/armv8_5-a-memtag.d: New tests for stzgm.
+ * testsuite/gas/aarch64/armv8_5-a-memtag.s: Likewise.
+ * testsuite/gas/aarch64/illegal-memtag.l: Likewise.
+ * testsuite/gas/aarch64/illegal-memtag.s: Likewise.
+
+2019-01-25 Sudakshina Das <sudi.das@arm.com>
+ Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
+
+ * config/tc-aarch64.c (parse_address_main): Remove support for
+ [base]! address expression.
+ (parse_operands): Remove support for AARCH64_OPND_ADDR_SIMPLE_2.
+ (warn_unpredictable_ldst): Remove support for ldstgv_indexed.
+ * testsuite/gas/aarch64/armv8_5-a-memtag.d: Remove tests for ldgv
+ and stgv.
+ * testsuite/gas/aarch64/armv8_5-a-memtag.s: Likewise.
+ * testsuite/gas/aarch64/illegal-memtag.l: Likewise.
+ * testsuite/gas/aarch64/illegal-memtag.s: Likewise.
+
+2019-01-25 Wu Heng <wu.heng@zte.com.cn>
+
+ PR gas/23940
+ * macro.c (getstring): Check array bound before accessing.
+
+2019-01-25 Alan Modra <amodra@gmail.com>
+
+ PR 20902
+ PR 24125
+ * read.c (stringer): Delete assertion.
+
+2019-01-21 Nick Clifton <nickc@redhat.com>
+
+ * po/uk.po: Updated Ukranian translation.
+
+2019-01-19 Nick Clifton <nickc@redhat.com>
+
+ * config.in: Regenerate.
+ * configure: Regenerate.
+ * po/gas.pot: Regenerate.
+
+2018-06-24 Nick Clifton <nickc@redhat.com>
+
+ 2.32 branch created.
+
+2019-01-17 Tamar Christina <tamar.christina@arm.com>
+
+ * testsuite/gas/arm/archv6t2-1-pe.d: New test.
+ * testsuite/gas/arm/archv6t2-1.d: Skip pe.
+ * testsuite/gas/arm/csdb.d: Skip pe.
+ * testsuite/gas/arm/sb-thumb1-pe.d: New test.
+ * testsuite/gas/arm/sb-thumb1.d: Skip pe.
+ * testsuite/gas/arm/sb-thumb2-pe.d: New test.
+ * testsuite/gas/arm/sb-thumb2.d: Skip pe.
+ * testsuite/gas/arm/udf.d: Skip pe.
+
+2019-01-16 Kito Cheng <kito@andestech.com>
+
+ * testsuite/gas/riscv/attribute-empty.d: New.
+
+2019-01-16 Kito Cheng <kito@andestech.com>
+ Nelson Chu <nelson@andestech.com>
+
+ * config/tc-riscv.c (DEFAULT_RISCV_ATTR): Define to 0 if not defined.
+ (riscv_set_options): Add `arch_attr` field.
+ (riscv_opts): Set default value for arch_attr.
+ (riscv_write_out_arch_attr): New.
+ (riscv_set_public_attributes): Likewise.
+ (riscv_md_end): Likewise.
+ (riscv_convert_symbolic_attribute): Likewise.
+ (s_riscv_attribute): Likewise.
+ (explicit_arch_attr): Likewise.
+ (riscv_pseudo_table): Add .attribute to the table.
+ (options): Add OPTION_ARCH_ATTR and OPTION_NO_ARCH_ATTR
+ enumeration constants.
+ (md_longopts): Add `march-attr' and `mno-arch-attr' options.
+ (md_parse_option): Handle the new options.
+ (md_show_usage): Document the `march-attr' option.
+ * config/tc-riscv.h (md_end): Define as riscv_md_end
+ (riscv_md_end): Declare.
+ (CONVERT_SYMBOLIC_ATTRIBUTE): Define as
+ riscv_convert_symbolic_attribute.
+ (riscv_convert_symbolic_attribute): Declare.
+ (start_assemble): Declare.
+ * testsuite/gas/elf/elf.exp: Adjust test case for section2.e.
+ * testsuite/gas/elf/section2.e-riscv: New.
+ * testsuite/gas/riscv/attribute-01.d: New test
+ * testsuite/gas/riscv/attribute-02.d: Likewise.
+ * testsuite/gas/riscv/attribute-03.d: Likewise.
+ * testsuite/gas/riscv/attribute-04.d: Likewise.
+ * testsuite/gas/riscv/attribute-04.s: Likewise.
+ * testsuite/gas/riscv/attribute-05.d: Likewise.
+ * testsuite/gas/riscv/attribute-05.s: Likewise.
+ * testsuite/gas/riscv/attribute-06.d: Likewise.
+ * testsuite/gas/riscv/attribute-06.s: Likewise.
+ * testsuite/gas/riscv/attribute-07.d: Likewise.
+ * testsuite/gas/riscv/attribute-07.s: Likewise.
+ * testsuite/gas/riscv/attribute-08.d: Likewise.
+ * testsuite/gas/riscv/attribute-08.s: Likewise.
+ * testsuite/gas/riscv/attribute-unknown.d: Likewise.
+ * testsuite/gas/riscv/attribute-unknown.s: Likewise.
+ * testsuite/gas/riscv/empty.l: Likewise.
+ * doc/c-riscv.texi (.attribute): Add documentation.
+ * configure.ac (--enable-default-riscv-attribute): New options.
+ * configure: Re-generate.
+ * config.in: Re-generate.
+
2019-01-16 John Darrington <john@darrington.wattle.id.au>
- * config/tc-s12z.c (tfr): Change as_bad to as_warn.
+ * config/tc-s12z.c (lex_reg_name): Compare the length of the strings
+ before the contents.
+ * testsuite/gas/s12z/labels.d: New file.
+ * testsuite/gas/s12z/labels.s: New file.
+ * testsuite/gas/s12z/s12z.exp: Add them.
+ * config/tc-s12z.c (tfr): Change as_bad to as_warn.
Also fix message typo and semantics.
- * config/tc-s12z.c (emit_opr): Emit BFD_RELOC_S12Z_OPR instead of
+ * config/tc-s12z.c (emit_opr): Emit BFD_RELOC_S12Z_OPR instead of
BFD_RELOC_24.
* testsuite/gas/s12z/opr-indirect-expr.d: Expect R_S12Z_OPR instead
of R_S12Z_EXT24.