+2020-12-15 Alan Modra <amodra@gmail.com>
+
+ PR 27071
+ * config/obj-elf.c (elf_obj_symbol_clone_hook): New function.
+ (elf_format_ops): Set symbol_clone_hook.
+ * config/obj-elf.h (elf_obj_symbol_clone_hook): Declare.
+ (obj_symbol_clone_hook): Define.
+ * listing.c (buffer_line): Avoid integer overflow on paper_width
+ set to zero.
+
+2020-12-14 Alan Modra <amodra@gmail.com>
+
+ * testsuite/gas/elf/section27.s: Reorder .text, .data and .bss
+ so that output section order does not depend on those sections
+ being already created. Use ".section .text" rather than ".text".
+
+2020-12-13 Borislav Petkov <bp@suse.de>
+
+ * testsuite/gas/i386/align-branch-9.s: Don't use labels that are
+ automatically local for ELF targets.
+ * testsuite/gas/i386/branch.s: Likewise.
+ * testsuite/gas/i386/x86-64-align-branch-9.s: Likewise.
+ * testsuite/gas/i386/x86-64-branch.s: Likewise.
+ * testsuite/gas/i386/align-branch-9.d: Adjust to match more targets.
+ * testsuite/gas/i386/branch.d: Likewise.
+ * testsuite/gas/i386/ilp32/x86-64-branch.d: Likewise.
+ * testsuite/gas/i386/x86-64-align-branch-9.d: Likewise.
+ * testsuite/gas/i386/x86-64-branch.d: Likewise.
+
+2020-12-11 Sergey Belyashov <sergey.belyashov@gmail.com>
+ Nick Clifton <nickc@redhat.com>
+
+ PR 27047
+ * config/tc-z80.c (s_bss): New function.
+ (md_pseudo_table): Add bss entry.
+
+2020-12-10 Nelson Chu <nelson.chu@sifive.com>
+
+ * config/tc-riscv.c (riscv_ext): New function. Use md_assemblef
+ to expand the zext and sext pseudos, to give them a chance to be
+ expanded into c-ext instructions.
+ (macro): Handle M_ZEXTH, M_ZEXTW, M_SEXTB and M_SEXTH.
+ * testsuite/gas/riscv/ext.s: New testcase.
+ * testsuite/gas/riscv/ext-32.d: Likewise.
+ * testsuite/gas/riscv/ext-64.d: Likewise.
+
+2020-12-10 Nelson Chu <nelson.chu@sifive.com>
+
+ * config/tc-riscv.c (riscv_multi_subset_supports): Handle INSN_CLASS_ZICSR
+ and INSN_CLASS_ZIFENCEI.
+ * testsuite/gas/riscv/march-imply-i.s: New testcase.
+ * testsuite/gas/riscv/march-imply-i2p0-01.d: New testcase. The version
+ of i is less than 2.1, and zi* are supported in the chosen spec, so
+ enable the fence.i and csr instructions, also output the implicit zi* to
+ the arch string.
+ * testsuite/gas/riscv/march-imply-i2p0-02.d: Likewise, but the zi* are
+ not supported in the spec 2.2. Enable the related instructions since
+ i's version is less than 2.1, but do not output them.
+ * testsuite/gas/riscv/march-imply-i2p1-01.d: New testcase. The version
+ of i is 2.1, so don't add it's implicit zi*, and disable the related
+ instructions.
+ * testsuite/gas/riscv/march-imply-i2p1-01.l: Likewise.
+ * testsuite/gas/riscv/march-imply-i2p1-02.d: Likewise, and set the zi*
+ explicitly, so enable the related instructions.
+ * testsuite/gas/riscv/march-imply-i2p0.d: Removed.
+ * testsuite/gas/riscv/march-imply-i2p1.d: Removed.
+
+2020-12-08 H.J. Lu <hongjiu.lu@intel.com>
+
+ * config/obj-elf.c (SEC_ASSEMBLER_SHF_MASK): New.
+ (get_section_by_match): Also check if SEC_ASSEMBLER_SHF_MASK of
+ sh_flags matches. Rename info to sh_info.
+ (obj_elf_change_section): Don't check previous SHF_GNU_RETAIN.
+ Rename info to sh_info.
+ (obj_elf_section): Rename info to sh_info. Set sh_flags for
+ SHF_GNU_RETAIN.
+ * config/obj-elf.h (elf_section_match): Rename info to sh_info.
+ Add sh_flags.
+ * testsuite/gas/elf/elf.exp: Run section27.
+ * testsuite/gas/elf/section24b.d: Updated.
+ * testsuite/gas/elf/section27.d: New file.
+ * testsuite/gas/elf/section27.s: Likewise.
+
+2020-12-04 Andreas Krebbel <krebbel@linux.ibm.com>
+
+ * testsuite/gas/s390/zarch-z10.s: Add tests for risbgz.
+ * testsuite/gas/s390/zarch-z10.d: Add regexp for risbgz.
+ * testsuite/gas/s390/zarch-zEC12.s: Add tests for risbgnz.
+ * testsuite/gas/s390/zarch-zEC12.d: Add regexp for risbgnz.
+
+2020-12-03 Andreas Krebbel <krebbel@linux.ibm.com>
+
+ * testsuite/gas/s390/esa-g5.s: Test new extended mnemonics.
+ * testsuite/gas/s390/esa-g5.d: Likewise.
+ * testsuite/gas/s390/esa-z900.s: Likewise.
+ * testsuite/gas/s390/esa-z900.d: Likewise.
+ * testsuite/gas/s390/zarch-z900.s: Likewise.
+ * testsuite/gas/s390/zarch-z900.d: Likewise.
+
+2020-12-01 Nelson Chu <nelson.chu@sifive.com>
+
+ * testsuite/gas/riscv/attribute-10.d: Updated.
+ * testsuite/gas/riscv/march-imply-g.d: New testcase for g.
+ * testsuite/gas/riscv/march-imply-unsupported.d: The zicsr and zifencei
+ are not supported in the ISA spec v2.2, so don't add and output them.
+
+2020-12-01 Nelson Chu <nelson.chu@sifive.com>
+
+ * config/tc-riscv.c (riscv_subset_supports): Updated.
+ * testsuite/gas/riscv/march-imply-i2p0.d: New testcase. Need to
+ add the implicit zicsr and zifencei when i's version less than 2.1.
+ * testsuite/gas/riscv/march-imply-i2p1.d: New testcase.
+ * testsuite/gas/riscv/march-imply-d.d: Likewise.
+ * testsuite/gas/riscv/march-imply-f.d: Likewise.
+ * testsuite/gas/riscv/march-imply-q.d: Likewise.
+ * testsuite/gas/riscv/march-fail-rv32iq.l: Updated.
+ * testsuite/gas/riscv/march-fail-rv32id.d: Removed.
+ * testsuite/gas/riscv/march-fail-rv32id.l: Likewise.
+ * testsuite/gas/riscv/march-fail-rv64iq.d: Likewise.
+ * testsuite/gas/riscv/march-fail-rv64iq.l: Likewise.
+
+2020-12-01 Nelson Chu <nelson.chu@sifive.com>
+
+ * config/tc-riscv.c (riscv_get_default_ext_version):
+ Change the version type from unsigned to int.
+ (riscv_set_arch): Use as_bad rather than as_fatal to
+ report more errors.
+ * testsuite/gas/riscv/attribute-02.d: Updated since x must be
+ set with versions.
+ * testsuite/gas/riscv/attribute-03.d: Likewise.
+ * testsuite/gas/riscv/march-ok-two-nse.d: Likewise.
+ * testsuite/gas/riscv/attribute-09.d: zicsr wasn't supported
+ in the spec 2.2, so choose the newer spec.
+ * testsuite/gas/riscv/march-fail-base-01.l: Updated since as_bad.
+ * testsuite/gas/riscv/march-fail-base-02.l: Likewise.
+ * testsuite/gas/riscv/march-fail-order-std.l: Likewise.
+ * testsuite/gas/riscv/march-fail-order-x.l: Likewise.
+ * testsuite/gas/riscv/march-fail-order-z.l: Likewise.
+ * testsuite/gas/riscv/march-fail-porder.l: Likewise.
+ * testsuite/gas/riscv/march-fail-rv32ef.l: Likewise.
+ * testsuite/gas/riscv/march-fail-rv32id.l: Likewise.
+ * testsuite/gas/riscv/march-fail-rv32iq.l: Likewise.
+ * testsuite/gas/riscv/march-fail-rv64iq.l: Likewise.
+ * testsuite/gas/riscv/march-fail-single-char.l: Likewise.
+ * testsuite/gas/riscv/march-fail-unknown-std.l: Likewise.
+ * testsuite/gas/riscv/march-fail-unknown.l: Likewise.
+ * testsuite/gas/riscv/march-fail-uppercase.l: Likewise.
+ * testsuite/gas/riscv/march-fail-version.l: Likewise.
+ * testsuite/gas/riscv/march-fail-isa-spec.d: Likewise.
+ * testsuite/gas/riscv/march-fail-isa-spec.l: Likewise.
+
+2020-12-01 Nelson Chu <nelson.chu@sifive.com>
+
+ * testsuite/gas/riscv/march-fail-order-z.d: New testcase, check
+ orders of prefixed z extensions.
+ * testsuite/gas/riscv/march-fail-order-z.l: Likewise.
+ * testsuite/gas/riscv/march-fail-single-char-h.d: New testcase.
+ * testsuite/gas/riscv/march-fail-single-char.l: Updated.
+ * testsuite/gas/riscv/march-fail-unknown-h.d: New testcase.
+ * testsuite/gas/riscv/march-fail-unknown.l: Updated.
+
+2020-12-01 Nelson Chu <nelson.chu@sifive.com>
+
+ * testsuite/gas/riscv/march-fail-uppercase-base.d: Updated.
+ * testsuite/gas/riscv/march-fail-uppercase.l: Updated.
+ * testsuite/gas/riscv/march-fail-uppercase-x.d: New testcase.
+
+2020-12-01 Nelson Chu <nelson.chu@sifive.com>
+
+ (These are new testcases that cover more cases)
+ * testsuite/gas/riscv/march-fail-base-01.d: The first extension must
+ be e, i or g.
+ * testsuite/gas/riscv/march-fail-base-01.l: Likewise.
+ * testsuite/gas/riscv/march-fail-base-02.d: rv64e is an invalid base ISA.
+ * testsuite/gas/riscv/march-fail-base-02.l: Likewise.
+ * testsuite/gas/riscv/march-fail-order-std.d: Check orders of standard
+ extensions.
+ * testsuite/gas/riscv/march-fail-order-std.l: Likewise.
+ * testsuite/gas/riscv/march-fail-order-x.d: Check orders of prefixed
+ x extensions.
+ * testsuite/gas/riscv/march-fail-order-x.l: Likewise.
+ * testsuite/gas/riscv/march-fail-porder-x-std.d: Check orders when
+ standard and prefixed extensions are set at the same time.
+ * testsuite/gas/riscv/march-fail-porder-x-z.d: Likewise.
+ * testsuite/gas/riscv/march-fail-porder-z-std.d: Likewise.
+ * testsuite/gas/riscv/march-fail-porder.l: Likewise.
+ * testsuite/gas/riscv/march-fail-single-char-s.d: Only standard
+ extensions can use single char.
+ * testsuite/gas/riscv/march-fail-single-char-x.d: Likewise.
+ * testsuite/gas/riscv/march-fail-single-char-z.d: Likewise.
+ * testsuite/gas/riscv/march-fail-single-char.l: Likewise.
+ * testsuite/gas/riscv/march-fail-unknown-s.d: All extensions
+ should be known, except the non-standard x extensions.
+ * testsuite/gas/riscv/march-fail-unknown-std.d: Likewise.
+ * testsuite/gas/riscv/march-fail-unknown-std.l: Likewise.
+ * testsuite/gas/riscv/march-fail-unknown-z.d: Likewise.
+ * testsuite/gas/riscv/march-fail-unknown.l: Likewise.
+ * testsuite/gas/riscv/march-fail-uppercase-base.d: Do not
+ allow any uppercase in the arch string.
+ * testsuite/gas/riscv/march-fail-uppercase-std.d: Likewise.
+ * testsuite/gas/riscv/march-fail-uppercase-z.d: Likewise.
+ * testsuite/gas/riscv/march-fail-uppercase.l: Likewise.
+ * testsuite/gas/riscv/march-fail-version-x.d: Failed to set versions.
+ * testsuite/gas/riscv/march-fail-version-z.d: Likewise.
+ * testsuite/gas/riscv/march-fail-version.l: Likewise.
+ * testsuite/gas/riscv/march-fail-rv32ef.l: Updated.
+ * testsuite/gas/riscv/march-fail-rv32id.d: Need f-ext.
+ * testsuite/gas/riscv/march-fail-rv32iq.d: Should be rv64.
+ * testsuite/gas/riscv/march-fail-rv32iq.l: Likewise.
+ * testsuite/gas/riscv/march-fail-rv64iq.d: Need d-ext and f-ext.
+ * testsuite/gas/riscv/march-fail-rv64iq.l: Likewise.
+
+ (The following testcases are removed and covered by new testcases)
+ * testsuite/gas/riscv/march-fail-rv32i.d: march-fail-uppercase-base.
+ * testsuite/gas/riscv/march-fail-rv32i.l: Likewise.
+ * testsuite/gas/riscv/march-fail-rv32iam.d: march-fail-order-std.
+ * testsuite/gas/riscv/march-fail-rv32iam.l: Likewise.
+ * testsuite/gas/riscv/march-fail-rv32ic.d: march-fail-uppercase-std.
+ * testsuite/gas/riscv/march-fail-rv32ic.l: Likewise.
+ * testsuite/gas/riscv/march-fail-rv32icx2p.d: march-fail-version-x.
+ * testsuite/gas/riscv/march-fail-rv32icx2p.l: Likewise.
+ * testsuite/gas/riscv/march-fail-rv32imc.d: march-fail-order-std.
+ * testsuite/gas/riscv/march-fail-rv32imc.l: Likewise.
+ * testsuite/gas/riscv/march-fail-rv64I.d: march-fail-uppercase-std.
+ * testsuite/gas/riscv/march-fail-rv64I.l: Likewise.
+ * testsuite/gas/riscv/march-fail-rv64e.d: march-fail-base-02.
+ * testsuite/gas/riscv/march-fail-rv64e.l: Likewise.
+ * testsuite/gas/riscv/march-fail-s-with-version.d: march-fail-unknown-s.
+ * testsuite/gas/riscv/march-fail-s-with-version.l: Likewise.
+ * testsuite/gas/riscv/march-fail-s.d: march-fail-unknown-s.
+ * testsuite/gas/riscv/march-fail-s.l: Likewise.
+ * testsuite/gas/riscv/march-fail-sx.d: march-fail-unknown-s.
+ * testsuite/gas/riscv/march-fail-sx.l: Likewise.
+
+2002-11-29 Borislav Petkov <bp@suse.de>
+
+ * testsuite/gas/i386/branch.d: Add new branch insns test.
+ * testsuite/gas/i386/branch.s: Likewise.
+ * testsuite/gas/i386/i386.exp: Insert the new branch test.
+ * testsuite/gas/i386/x86-64-branch.d: Test for branch hints insns.
+ * testsuite/gas/i386/x86-64-branch.s: Likewise.
+ * testsuite/gas/i386/ilp32/x86-64-branch.d: Likewise.
+
+2020-11-27 Jozef Lawrynowicz <jozef.l@mittosystems.com>
+
+ * testsuite/gas/elf/elf.exp: Run new tests.
+ * testsuite/gas/elf/section25.d: New test.
+ * testsuite/gas/elf/section25.s: New test.
+ * testsuite/gas/elf/section26.d: New test.
+ * testsuite/gas/elf/section26.s: New test.
+
+2020-11-25 Alan Modra <amodra@gmail.com>
+
+ * output-file.c (output_file_close): Remove "can't close" from
+ error message.
+ * testsuite/gas/mips/reginfo-2.l: Update expected output.
+
+2020-11-04 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
+
+ * config/tc-aarch64.c (aarch64_cpus): Add Cortex-A78C.
+ * doc/c-aarch64.texi: Document -mcpu=cortex-a78c.
+ * doc/NEWS: Update news.
+
+2020-11-19 Jozef Lawrynowicz <jozef.l@mittosystems.com>
+
+ * testsuite/gas/elf/section22.d: Allow FreeBSD OSABI in readelf
+ output.
+ * testsuite/gas/elf/section23a.d: Likewise.
+ * testsuite/gas/elf/section24a.d: Likewise.
+
+2020-11-18 Alan Modra <amodra@gmail.com>
+
+ * doc/as.texi (.nop): Document optional size arg.
+ * dwarf2dbg.c (dwarf2_gen_line_info_1): Only check SEC_ALLOC
+ when ELF. Warn whenever dwarf line number information is ignored.
+ * frags.c (frag_offset_ignore_align_p): New function.
+ * frags.h (frag_offset_ignore_align_p): Declare.
+ * read.c (s_nop): Extend to support optional size arg.
+ * testsuite/gas/elf/dwarf2-20.d: Expect warnings, and exact range.
+ * testsuite/gas/elf/dwarf2-20.s: Emit 16 bytes worth of nops.
+ * testsuite/gas/m68hc11/indexed12.d: Expect warnings.
+
+2020-11-18 Jozef Lawrynowicz <jozef.l@mittosystems.com>
+ H.J. Lu <hongjiu.lu@intel.com>
+
+ * NEWS: Announce SHF_GNU_RETAIN support.
+ * config/obj-elf.c (obj_elf_change_section): Merge SHF_GNU_RETAIN bit
+ between section declarations.
+ (obj_elf_parse_section_letters): Handle 'R' flag.
+ Handle numeric flag values within the SHF_MASKOS range.
+ (obj_elf_section): Validate SHF_GNU_RETAIN usage.
+ * doc/as.texi: Document 'R' flag to .section directive.
+ * testsuite/gas/elf/elf.exp: Run new tests.
+ * testsuite/gas/elf/section10.d: Unset SHF_GNU_RETAIN bit.
+ * testsuite/gas/elf/section10.s: Likewise.
+ * testsuite/gas/elf/section22.d: New test.
+ * testsuite/gas/elf/section22.s: New test.
+ * testsuite/gas/elf/section23.s: New test.
+ * testsuite/gas/elf/section23a.d: New test.
+ * testsuite/gas/elf/section23b.d: New test.
+ * testsuite/gas/elf/section23b.err: New test.
+ * testsuite/gas/elf/section24.s: New test.
+ * testsuite/gas/elf/section24a.d: New test.
+ * testsuite/gas/elf/section24b.d: New test.
+
+2020-11-13 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
+
+ * NEWS: Update news.
+ * config/tc-aarch64.c: Add option +pauth to -march.
+ * doc/c-aarch64.texi: Update docs.
+ * testsuite/gas/aarch64/pac-feat.d: New test.
+ * testsuite/gas/aarch64/pac-feat.s: New test.
+
+2020-11-16 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
+
+ * NEWS: Update news.
+ * config/tc-aarch64.c: New feature flag +flagm.
+ * doc/c-aarch64.texi: Update docs.
+ * testsuite/gas/aarch64/flagm.d: New test.
+ * testsuite/gas/aarch64/flagm.s: New test.
+
+2020-11-16 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
+
+ * config/tc-arm.c (arm_cpus): Add Cortex-A78C.
+ * doc/c-arm.texi: Document -mcpu=cortex-a78c.
+ * testsuite/gas/arm/cpu-cortex-a78c.d: New test.
+
+2020-11-14 Borislav Petkov <bp@suse.de>
+
+ * testsuite/gas/i386/x86-64-segovr.d: Adjust regexes.
+ * testsuite/gas/i386/x86-64-nops.d: Likewise.
+ * testsuite/gas/i386/x86-64-nops-1.d: Likewise.
+ * testsuite/gas/i386/x86-64-nops-1-g64.d: Likewise.
+ * testsuite/gas/i386/x86-64-nops-1-core2.d: Likewise.
+ * testsuite/gas/i386/x86-64-nops-1-k8.d: Likewise.
+ * testsuite/gas/i386/x86-64-nops-2.d: Likewise.
+ * testsuite/gas/i386/x86-64-nops-3.d: Likewise.
+ * testsuite/gas/i386/x86-64-nops-4.d: Likewise.
+ * testsuite/gas/i386/x86-64-nops-4-core2.d: Likewise.
+ * testsuite/gas/i386/x86-64-nops-4-k8.d: Likewise.
+ * testsuite/gas/i386/x86-64-nops-5.d: Likewise.
+ * testsuite/gas/i386/x86-64-nops-5-k8.d: Likewise.
+ * testsuite/gas/i386/x86-64-nops-7.d: Likewise.
+ * testsuite/gas/i386/x86-64-nop-1.d: Likewise.
+ * testsuite/gas/i386/x86-64-align-branch-1a.d: Likewise.
+ * testsuite/gas/i386/x86-64-align-branch-1b.d: Likewise.
+ * testsuite/gas/i386/x86-64-align-branch-1c.d: Likewise.
+ * testsuite/gas/i386/x86-64-align-branch-1d.d: Likewise.
+ * testsuite/gas/i386/x86-64-align-branch-1g.d: Likewise.
+ * testsuite/gas/i386/x86-64-align-branch-2c.d: Likewise.
+ * testsuite/gas/i386/x86-64-align-branch-6.d: Likewise.
+ * testsuite/gas/i386/x86-64-align-branch-7.d: Likewise.
+ * testsuite/gas/i386/x86-64-align-branch-8.d: Likewise.
+ * testsuite/gas/i386/ilp32/x86-64-nops-1-core2.d: Likewise.
+ * testsuite/gas/i386/ilp32/x86-64-nops-1-k8.d: Likewise.
+ * testsuite/gas/i386/ilp32/x86-64-nops-1.d: Likewise.
+ * testsuite/gas/i386/ilp32/x86-64-nops-2.d: Likewise.
+ * testsuite/gas/i386/ilp32/x86-64-nops-3.d: Likewise.
+ * testsuite/gas/i386/ilp32/x86-64-nops-4-core2.d: Likewise.
+ * testsuite/gas/i386/ilp32/x86-64-nops-4-k8.d: Likewise.
+ * testsuite/gas/i386/ilp32/x86-64-nops-4.d: Likewise.
+ * testsuite/gas/i386/ilp32/x86-64-nops-5-k8.d: Likewise.
+ * testsuite/gas/i386/ilp32/x86-64-nops-5.d: Likewise.
+ * testsuite/gas/i386/ilp32/x86-64-nops.d:: Likewise.
+
+2020-11-12 Jozef Lawrynowicz <jozef.l@mittosystems.com>
+
+ * config/tc-msp430.c (OPTION_MOVE_DATA): Define.
+ (md_parse_option): Ignore OPTION_MOVE_DATA.
+ (md_longopts): Handle -md option.
+ * testsuite/gas/msp430/msp430.exp: Run new test.
+ * testsuite/gas/msp430/empty.s: New test.
+ * testsuite/gas/msp430/ignore-md.d: New test.
+
+2020-11-12 Nick Clifton <nickc@redhat.com>
+
+ PR 26850
+ * dwarf2dbg.c (dwarf2_gen_line_info_1): Do not record lines in
+ sections that are not executable or not loadable.
+ (out_debug_line): Move warning message into dwarf2_gen_line_info_1.
+ * testsuite/gas/elf/dwarf2-20.s: New test.
+ * testsuite/gas/elf/dwarf2-20.d: New test driver.
+ * testsuite/gas/elf/elf.exp: Run the new test.
+ * testsuite/gas/elf/warn-2.s: Use the .nop directive.
+
+2020-11-11 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
+
+ * testsuite/gas/aarch64/ls64.s: Update test.
+
+2020-11-09 Denys Zagorui <dzagorui@cisco.com>
+
+ * config/obj-elf (obj_elf_init_stab_section): Improve
+ reproducibility for stabs debugging data format
+
+2020-11-09 Spencer E. Olson <olsonse@umich.edu>
+
+ * testsuite/gas/pru/misc.s: Add tests for lmbd (left-most bit
+ detect).
+ * testsuite/gas/pru/misc.d: Update expected disassembly.
+
+2020-11-09 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
+
+ * config/tc-aarch64.c: Fix comment.
+ * testsuite/gas/aarch64/ls64.d: New test.
+ * testsuite/gas/aarch64/ls64.s: Test for ACCDATA_EL1 register.
+
+2020-11-09 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
+
+ * config/tc-aarch64.c (process_omitted_operand): Add AARCH64_OPND_Rt_LS64.
+ (parse_operands): Parse Rt range for AARCH64_OPND_Rt_LS64.
+ * testsuite/gas/aarch64/ls64-invalid.l: Update test.
+ * testsuite/gas/aarch64/ls64-invalid.s: Update test.
+ * testsuite/gas/aarch64/ls64.s: Update test.
+
+2020-11-09 Andreas Schwab <schwab@linux-m68k.org>
+
+ * Makefile.am (development.exp): Fix regexp.
+ * Makefile.in: Regenerate.
+
+2020-11-09 Nelson Chu <nelson.chu@sifive.com>
+
+ * config/tc-riscv.c (explicit_mabi): New boolean to indicate if
+ the -mabi= option is explictly set.
+ (md_parse_option): Set explicit_mabi to TRUE if -mabi is set.
+ (riscv_set_abi_by_arch): New function. If the -mabi option isn't
+ set, then we set the abi according to the architecture string.
+ Otherwise, check if there are conflicts between architecture
+ and abi setting.
+ (riscv_after_parse_args): Move the abi setting to md_assemble nad
+ riscv_elf_final_processing.
+ (md_assemble): Call the riscv_set_abi_by_arch when we set the
+ start_assemble to TRUE.
+ (riscv_elf_final_processing): Likewise, in case the file without
+ any instruction.
+ * testsuite/gas/riscv/mabi-attr-01.s: New testcase.
+ * testsuite/gas/riscv/mabi-attr-02.s: Likewise.
+ * testsuite/gas/riscv/mabi-attr-03.s: Likewise.
+ * testsuite/gas/riscv/mabi-fail-01.d: Likewise.
+ * testsuite/gas/riscv/mabi-fail-01.l: Likewise.
+ * testsuite/gas/riscv/mabi-fail-02.d: Likewise.
+ * testsuite/gas/riscv/mabi-fail-02.l: Likewise.
+ * testsuite/gas/riscv/mabi-noabi-attr-01a.d: Likewise.
+ * testsuite/gas/riscv/mabi-noabi-attr-01b.d: Likewise.
+ * testsuite/gas/riscv/mabi-noabi-attr-02a.d: Likewise.
+ * testsuite/gas/riscv/mabi-noabi-attr-02b.d: Likewise.
+ * testsuite/gas/riscv/mabi-noabi-attr-03a.d: Likewise.
+ * testsuite/gas/riscv/mabi-noabi-attr-03b.d: Likewise.
+ * testsuite/gas/riscv/mabi-noabi-march-01.d: Likewise.
+ * testsuite/gas/riscv/mabi-noabi-march-02.d: Likewise.
+ * testsuite/gas/riscv/mabi-noabi-march-03.d: Likewise.
+
+2020-11-04 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
+
+ * testsuite/gas/aarch64/armv8-ras-1_1-invalid.d: New test.
+ * testsuite/gas/aarch64/armv8-ras-1_1-invalid.l: New test.
+ * testsuite/gas/aarch64/armv8-ras-1_1-invalid.s: New test.
+ * testsuite/gas/aarch64/armv8-ras-1_1.d: New test.
+ * testsuite/gas/aarch64/armv8-ras-1_1.s: New test.
+ * testsuite/gas/aarch64/illegal-ras-1.d: Remove.
+ * testsuite/gas/aarch64/illegal-ras-1.l: Remove.
+ * testsuite/gas/aarch64/illegal-ras-1.s: Remove.
+ * testsuite/gas/aarch64/illegal-sysreg-2.d: Remove.
+ * testsuite/gas/aarch64/illegal-sysreg-2.l: Remove.
+
+2020-11-03 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
+
+ * NEWS: Update docs.
+ * config/tc-aarch64.c: Add +ls64 feature to -march flags set.
+ * testsuite/gas/aarch64/ls64-invalid.d: New test.
+ * testsuite/gas/aarch64/ls64-invalid.l: New test.
+ * testsuite/gas/aarch64/ls64-invalid.s: New test.
+ * testsuite/gas/aarch64/ls64.s: New test.
+
+2020-11-03 Christian Eggers <ceggers@gmx.de>
+
+ * config/obj-elf (elf_frob_symbol): Fix symbol value calculation
+ for versioned symbol aliases.
+
+2020-10-30 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR gas/26703
+ * config/tc-i386.c (output_insn): Update for
+ GNU_PROPERTY_X86_ISA_1_BASELINE.
+ * testsuite/gas/i386/property-1.d: Updated.
+ * testsuite/gas/i386/property-2.d: Likewise.
+ * testsuite/gas/i386/property-3.d: Likewise.
+ * testsuite/gas/i386/property-4.d: Likewise.
+ * testsuite/gas/i386/property-5.d: Likewise.
+ * testsuite/gas/i386/property-6.d: Likewise.
+ * testsuite/gas/i386/property-11.d: Likewise.
+ * testsuite/gas/i386/property-12.d: Likewise.
+ * testsuite/gas/i386/x86-64-property-1.d: Likewise.
+ * testsuite/gas/i386/x86-64-property-2.d: Likewise.
+ * testsuite/gas/i386/x86-64-property-3.d: Likewise.
+ * testsuite/gas/i386/x86-64-property-4.d: Likewise.
+ * testsuite/gas/i386/x86-64-property-5.d: Likewise.
+ * testsuite/gas/i386/x86-64-property-6.d: Likewise.
+ * testsuite/gas/i386/x86-64-property-11.d: Likewise.
+ * testsuite/gas/i386/x86-64-property-12.d: Likewise.
+
+2020-10-30 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
+
+ * NEWS: Update docs.
+ * testsuite/gas/aarch64/system-5.d: Update test with WFIT insn.
+ * testsuite/gas/aarch64/system-5.s: Update test with WFIT insn.
+
+2020-10-28 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
+
+ * config/tc-aarch64.c (parse_operands): Check for C0-C15 value of DSB
+ immediate string operand.
+ * testsuite/gas/aarch64/system-4.d: Update test.
+ * testsuite/gas/aarch64/system-4.s: Update test.
+
+2020-10-27 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
+
+ * NEWS: Update docs.
+ * config/tc-aarch64.c (parse_csr_operand): New operand parser.
+ (parse_operands): Call to CSR operand parser.
+ * testsuite/gas/aarch64/csre_csr-invalid.d: New test.
+ * testsuite/gas/aarch64/csre_csr-invalid.l: New test.
+ * testsuite/gas/aarch64/csre_csr-invalid.s: New test.
+ * testsuite/gas/aarch64/csre_csr.d: New test.
+ * testsuite/gas/aarch64/csre_csr.s: New test.
+
+2020-10-27 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
+
+ * NEWS: Update docs.
+ * testsuite/gas/aarch64/system-5.d: New test.
+ * testsuite/gas/aarch64/system-5.s: New test.
+
+2020-10-26 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR gas/26778
+ * * dwarf2dbg.c (num_of_auto_assigned): New.
+ (allocate_filenum): Increment num_of_auto_assigned.
+ (dwarf2_directive_filename): Clear the slots auto-assigned
+ before the first .file <NUMBER> directive was seen.
+ * testsuite/gas/i386/dwarf4-line-1.d: New file.
+ * testsuite/gas/i386/dwarf4-line-1.s: Likewise.
+ * testsuite/gas/i386/i386.exp: Run dwarf4-line-1.
+
+2020-10-26 Cooper Qu <cooper.qu@linux.alibaba.com>
+
+ * config/tc-csky.c (dump_literals): Fix the literal dump
+ of big vector constant.
+
+2020-10-26 Cooper Qu <cooper.qu@linux.alibaba.com>
+
+ * testsuite/gas/csky/enhance_dsp.s : Change plsl.u16 to plsl.16.
+ * testsuite/gas/csky/enhance_dsp.d : Change plsl.u16 to plsl.16.
+
+2020-10-26 Cooper Qu <cooper.qu@linux.alibaba.com>
+
+ * config/tc-csky.c (md_begin): Add version flag in eflag.
+
+2020-10-26 Cooper Qu <cooper.qu@linux.alibaba.com>
+
+ * config/tc-csky.c (get_operand_value): Add handler for
+ OPRND_TYPE_IMM5b_VSH and OPRND_TYPE_VREG_WITH_INDEX.
+ * testsuite/gas/csky/csky_vdsp.d : Fix the disassembling for
+ vector register.
+
+2020-10-26 Lili Cui <lili.cui@intel.com>
+
+ * testsuite/gas/i386/avx-vnni.d: Change psuedo prefix from
+ {vex3} to {vex}
+ * testsuite/gas/i386/x86-64-avx-vnni.d: Likewise.
+
+2020-10-23 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
+
+ * NEWS: Docs update.
+ * config/tc-aarch64.c (parse_operands): Add
+ AARCH64_OPND_BARRIER_DSB_NXS handler.
+ (md_begin): Add content of aarch64_barrier_dsb_nxs_options to
+ aarch64_barrier_opt_hsh hash.
+ * testsuite/gas/aarch64/system-4-invalid.d: New test.
+ * testsuite/gas/aarch64/system-4-invalid.l: New test.
+ * testsuite/gas/aarch64/system-4-invalid.s: New test.
+ * testsuite/gas/aarch64/system-4.d: New test.
+ * testsuite/gas/aarch64/system-4.s: New test.
+
+2020-10-21 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
+
+ PR target/26763
+ * config/tc-arm.c (parse_address_main): Add new MVE addressing mode
+ check.
+ * testsuite/gas/arm/mve-vldr-vstr-bad.d: New test.
+ * testsuite/gas/arm/mve-vldr-vstr-bad.l: Likewise.
+ * testsuite/gas/arm/mve-vldr-vstr-bad.s: Likewise.
+
+2020-10-20 Dr. David Alan Gilbert <dgilbert@redhat.com>
+
+ * config/tc-arc.c (emit_insn0): Fix printf format.
+
+2020-10-20 Ganesh Gopalasubramanian <Ganesh.Gopalasubramanian@amd.com>
+
+ * config/tc-i386.c (cpu_arch): Add CPU_ZNVER3_FLAGS flags.
+ (i386_align_code): Add PROCESSOR_ZNVER cases.
+ * doc/c-i386.texi: Add znver3, snp, invlpgb and tlbsync.
+ * gas/i386/i386.exp: Add new znver3 test cases.
+ * gas/i386/arch-14-znver3.d: New.
+ * gas/i386/arch-14.d: New.
+ * gas/i386/arch-14.s: New.
+ * gas/i386/invlpgb.d: New.
+ * gas/i386/invlpgb64.d: New.
+ * gas/i386/invlpgb.s: New.
+ * gas/i386/snp.d: New.
+ * gas/i386/snp64.d: New.
+ * gas/i386/snp.s: New.
+ * gas/i386/tlbsync.d: New.
+ * gas/i386/tlbsync.s: New.
+ * gas/i386/x86-64-arch-4-znver3.d: New.
+ * gas/i386/x86-64-arch-4.d: New.
+ * gas/i386/x86-64-arch-4.s: New.
+
+2020-10-17 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR gas/25878
+ PR gas/26740
+ * testsuite/gas/i386/dwarf5-line-4.d: New file.
+ * testsuite/gas/i386/dwarf5-line-4.s: Likewise.
+ * testsuite/gas/i386/i386.exp: Run dwarf5-line-4.
+
+2020-10-17 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR gas/25878
+ PR gas/26740
+ * testsuite/gas/i386/dwarf5-line-3.s: Replace dwarf5-line-2.S
+ with dwarf5-line-3.S.
+ * testsuite/gas/i386/dwarf5-line-3.d: Updated.
+
+2020-10-17 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR gas/25878
+ PR gas/26740
+ * dwarf2dbg.c (allocate_filename_to_slot): Don't reuse the slot 1
+ here.
+ (dwarf2_where): Restore as_where.
+ (dwarf2_directive_filename): Clear the slot 1 if it was assigned
+ to the input file.
+ * testsuite/gas/i386/dwarf5-line-2.d: New file.
+ * testsuite/gas/i386/dwarf5-line-2.s: Likewise.
+ * testsuite/gas/i386/dwarf5-line-3.d: Likewise.
+ * testsuite/gas/i386/dwarf5-line-3.s: Likewise.
+ * testsuite/gas/i386/i386.exp: Run dwarf5-line-2 and
+ dwarf5-line-3.
+
+gas/ChangeLog:
+
+2020-10-16 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
+
+ * NEWS: Docs update.
+ * config/tc-aarch64.c (armv8.7-a): New arch.
+ * doc/c-aarch64.texi (-march=armv8.7-a): Update docs.
+
+2020-10-16 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
+
+ * testsuite/gas/aarch64/sysreg-6.d: New test.
+ * testsuite/gas/aarch64/sysreg-6.s: New test.
+
+2020-10-16 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR gas/25878
+ PR gas/26740
+ * dwarf2dbg.c (file_entry): Remove auto_assigned.
+ (assign_file_to_slot): Remove the auto_assign argument.
+ (allocate_filenum): Updated.
+ (allocate_filename_to_slot): Reuse the input file entry in the
+ file table.
+ (dwarf2_where): Replace as_where with as_where_physical.
+ * testsuite/gas/i386/dwarf5-line-1.d: New file.
+ * testsuite/gas/i386/dwarf5-line-1.s: Likewise.
+ * testsuite/gas/i386/i386.exp: Run dwarf5-line-1.
+
+2020-10-16 Lili Cui <lili.cui@intel.com>
+
+ * config/tc-i386.c (cpu_flags_match): Move Pseudo Prefix check
+ to ...
+ (match_template): Here.
+ * testsuite/gas/i386/avx-vnni-inval.l: New file.
+ * testsuite/gas/i386/avx-vnni-inval.s: Likewise.
+ * testsuite/gas/i386/avx-vnni.d: Delete invalid {vex2} test.
+ * testsuite/gas/i386/avx-vnni.s: Likewise.
+ * testsuite/gas/i386/i386.exp: Add AVX VNNI invalid tests.
+ * testsuite/gas/i386/x86-64-avx-vnni-inval.l: New file.
+ * testsuite/gas/i386/x86-64-avx-vnni-inval.s: Likewise.
+ * testsuite/gas/i386/x86-64-avx-vnni.d: Delete invalid {vex2} test.
+ * testsuite/gas/i386/x86-64-avx-vnni.s: Likewise.
+
+2020-10-14 H.J. Lu <hongjiu.lu@intel.com>
+ Lili Cui <lili.cui@intel.com>
+
+ * NEWS: Add Intel AVX VNNI.
+ * config/tc-i386.c (cpu_arch): Add .avx_vnni and noavx_vnni.
+ (cpu_flags_match): Support CpuVEX_PREFIX.
+ * doc/c-i386.texi: Document .avx_vnni, noavx_vnni and how to
+ encode Intel VNNI instructions with VEX prefix.
+ * testsuite/gas/i386/avx-vnni.d: New file.
+ * testsuite/gas/i386/avx-vnni.s: Likewise.
+ * testsuite/gas/i386/x86-64-avx-vnni.d: Likewise.
+ * testsuite/gas/i386/x86-64-avx-vnni.s: Likewise.
+ * testsuite/gas/i386/i386.exp: Run AVX VNNI tests.
+
+2020-10-14 Lili Cui <lili.cui@intel.com>
+
+ * NEWS: Add Intel HRESET.
+ * config/tc-i386.c (cpu_arch): Add .hreset.
+ (cpu_noarch): Likewise.
+ * doc/c-i386.texi: Document .hreset, nohreset.
+ * testsuite/gas/i386/i386.exp: Run HRESET tests.
+ * testsuite/gas/i386/hreset.d: New file.
+ * testsuite/gas/i386/x86-64-hreset.d: Likewise.
+ * testsuite/gas/i386/hreset.s: Likewise.
+
+2020-10-14 Lili Cui <lili.cui@intel.com>
+
+ * NEWS: Add Intel UINTR.
+ * config/tc-i386.c (cpu_arch): Add .uintr.
+ (cpu_noarch): Likewise.
+ * doc/c-i386.texi: Document .uintr and nouintr.
+ * testsuite/gas/i386/i386.exp: Run UINTR tests.
+ * testsuite/gas/i386/x86-64-uintr.d: Likewise.
+ * testsuite/gas/i386/x86-64-uintr.s: Likewise.
+
+2020-10-14 H.J. Lu <hongjiu.lu@intel.com>
+
+ * config/tc-i386.c (load_insn_p): Check opcodeprefix == 0 for
+ base_opcode == 0xfc7.
+ (match_template): Likewise.
+ (process_suffix): Check opcodeprefix == PREFIX_0XF2 for CRC32.
+ (check_byte_reg): Likewise.
+ (output_insn): Don't add the 0xf3 prefix twice for PadLock
+ instructions. Don't add prefix from non-VEX/EVEX base_opcode.
+
+2020-10-13 H.J. Lu <hongjiu.lu@intel.com>
+
+ * config/tc-i386.c (build_vex_prefix): Replace vexopcode with
+ opcodeprefix.
+ (build_evex_prefix): Likewise.
+ (is_any_vex_encoding): Don't check vexopcode.
+ (output_insn): Handle opcodeprefix.
+
+2020-10-09 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR gas/26703
+ * config/tc-i386.c (xstate): Add xstate_mask.
+ (md_assemble): Check i.types[j], instead of i.tm.operand_types[j],
+ for xstate. Set xstate_mask, instead of xstate_zmm, for RegMask.
+ (output_insn): Update for GNU_PROPERTY_X86_ISA_1_V[234]. Update
+ xstate for mask register and VSIB.
+ * testsuite/gas/i386/i386.exp: Run more GNU_PROPERTY tests.
+ * testsuite/gas/i386/property-1.s: Updated to the current
+ GNU_PROPERTY_X86_ISA_1_USED value.
+ * testsuite/gas/i386/property-2.s: Only keep cmove.
+ * testsuite/gas/i386/property-3.s: Changed to addsubpd.
+ * testsuite/gas/i386/property-1.d: Updated.
+ * testsuite/gas/i386/property-2.d: Likewise.
+ * testsuite/gas/i386/property-3.d: Likewise.
+ * testsuite/gas/i386/property-4.d: Likewise.
+ * testsuite/gas/i386/property-5.d: Likewise.
+ * testsuite/gas/i386/property-6.d: Likewise.
+ * testsuite/gas/i386/x86-64-property-1.d: Likewise.
+ * testsuite/gas/i386/x86-64-property-2.d: Likewise.
+ * testsuite/gas/i386/x86-64-property-3.d: Likewise.
+ * testsuite/gas/i386/x86-64-property-4.d: Likewise.
+ * testsuite/gas/i386/x86-64-property-5.d: Likewise.
+ * testsuite/gas/i386/x86-64-property-6.d: Likewise.
+ * testsuite/gas/i386/x86-64-property-7.d: Likewise.
+ * testsuite/gas/i386/x86-64-property-8.d: Likewise.
+ * testsuite/gas/i386/x86-64-property-9.d: Likewise.
+ * testsuite/gas/i386/property-11.d: New file.
+ * testsuite/gas/i386/property-11.s: Likewise.
+ * testsuite/gas/i386/property-12.d: Likewise.
+ * testsuite/gas/i386/property-12.s: Likewise.
+ * testsuite/gas/i386/property-13.d: Likewise.
+ * testsuite/gas/i386/property-13.s: Likewise.
+ * testsuite/gas/i386/x86-64-property-11.d: Likewise.
+ * testsuite/gas/i386/x86-64-property-12.d: Likewise.
+ * testsuite/gas/i386/x86-64-property-13.d: Likewise.
+ * testsuite/gas/i386/x86-64-property-14.d: Likewise.
+ * testsuite/gas/i386/x86-64-property-14.s: Likewise.
+
+2020-10-08 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
+
+ * NEWS: Docs update.
+ * testsuite/gas/aarch64/brbe-invalid.d: New test.
+ * testsuite/gas/aarch64/brbe-invalid.l: New test.
+ * testsuite/gas/aarch64/brbe-invalid.s: New test.
+ * testsuite/gas/aarch64/brbe.d: New test.
+ * testsuite/gas/aarch64/brbe.s: New test.
+
+2020-10-08 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
+
+ * NEWS: Docs update.
+ * testsuite/gas/aarch64/csre-invalid.d: New test.
+ * testsuite/gas/aarch64/csre-invalid.l: New test.
+ * testsuite/gas/aarch64/csre-invalid.s: New test.
+ * testsuite/gas/aarch64/csre.d: New test.
+ * testsuite/gas/aarch64/csre.s: New test.
+
+2020-10-06 Alex Coplan <alex.coplan@arm.com>
+
+ PR 26699
+ * config/tc-aarch64.c (asm_barrier_opt): Delete.
+ (parse_barrier): Fix bogus type punning.
+ * testsuite/gas/aarch64/system.d: Update disassembly.
+ * testsuite/gas/aarch64/system.s: Add isb sy test.
+
+2020-10-06 Sergey Belyashav <sergey.belyashov@gmail.com>
+
+ PR 26692
+ * config/tc-z80.c (md_begin): Ensure that xpressions are empty
+ before using them.
+ (unify_indexed): Likewise.
+ (z80_start_line_hook): Improve hash sign handling when SDCC
+ compatibility mode enabled.
+ (md_parse_exp_not_indexed): Improve indirect addressing
+ detection.
+ (md_pseudo_table): Accept hd64 as an alias of z810.
+
+2020-10-06 Alan Modra <amodra@gmail.com>
+
+ * testsuite/gas/elf/sh-link-zero.s: Don't start directives in
+ first column. Don't use numeric labels.
+
+2020-10-05 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
+
+ * config/tc-arm.c: Update Cortex-X1 feature flags.
+
+2020-10-05 Kamil Rytarowski <n54@gmx.com>
+
+ * configure.tgt (aarch64*-*-netbsd*): Add target.
+
+2020-10-05 Samanta Navarro <ferivoz@riseup.net>
+
+ * doc/as.texi: Fix spelling mistakes.
+ * doc/c-wasm32.texi: Likewise.
+
+2020-10-05 T.K. Chia <u1049321969@caramail.com>
+
+ PR gas/26694
+ * NEWS: Updated for i386 lcall and ljmp change.
+ * config/tc-i386.c (output_interseg_jump): Allow non-absolute
+ segment operand for immediate lcall and ljmp.
+ * testsuite/gas/i386/jump.d,
+ * testsuite/gas/i386/jump.s,
+ * testsuite/gas/i386/jump16.d,
+ * testsuite/gas/i386/jump16.e,
+ * testsuite/gas/i386/jump16.s: Add tests for non-absolute
+ segment operand for immediate ljmp.
+
+2020-10-05 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR binutils/26704
+ * testsuite/gas/i386/noreg64-data16.d: Expect sysretl instead of
+ sysret.
+ * testsuite/gas/i386/noreg64.d: Likewise.
+ * testsuite/gas/i386/x86-64-intel64.d: Likewise.
+ * testsuite/gas/i386/x86-64-opcode.d: Likewise.
+
+2020-10-05 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR binutils/26705
+ * testsuite/gas/i386/x86-64-suffix.s: Add "mov %rsp,%rbp" before
+ sysretq.
+ * testsuite/gas/i386/x86-64-suffix-intel.d: Updated.
+ * testsuite/gas/i386/x86-64-suffix.d: Likewise.
+
+2020-10-05 Nick Clifton <nickc@redhat.com>
+
+ PR 26253
+ * config/obj-elf.c (obj_elf_section): Accept a numeric value for
+ the "o" section flag. Interpret it as a section index. Allow an
+ index of zero.
+ * doc/as.texi: Document the new behaviour.
+ * NEWS: Mention the new feature. Tidy entries.
+ * testsuite/gas/elf/sh-link-zero.s: New test.
+ * testsuite/gas/elf/sh-link-zero.d: New test driver.
+ * testsuite/gas/elf/elf.exp: Run the new test.
+ * testsuite/gas/elf/section21.l: Updated expected assembler
+ output.
+
+2020-10-05 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
+
+ * config/tc-aarch64.c: Update Cortex-X1 feature flags.
+
+2020-10-03 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR gas/26685
+ * config/tc-i386.c (process_suffix): Also check the register
+ operand for the address size prefix if the memory operand has
+ no real registers.
+ * testsuite/gas/i386/enqcmd-16bit.d: New file.
+ * testsuite/gas/i386/enqcmd-16bit.s: Likewise.
+ * testsuite/gas/i386/movdir-16bit.d: Likewise.
+ * testsuite/gas/i386/movdir-16bit.s: Likewise.
+ * testsuite/gas/i386/enqcmd.s: Add tests with symbol and DISP.
+ * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
+ * testsuite/gas/i386/x86-64-movdir.s: Likewise.
+ * testsuite/gas/i386/movdir.s: Add tests with symbol and DISP.
+ Remove the .code16 test.
+ * testsuite/gas/i386/i386.exp: Run movdir-16bit and enqcmd-16bit.
+ * testsuite/gas/i386/x86-64-enqcmd-intel.d: Updated.
+ * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
+ * testsuite/gas/i386/x86-64-movdir-intel.d: Likewise.
+ * testsuite/gas/i386/x86-64-movdir.d: Likewise.
+ * testsuite/gas/i386/enqcmd-intel.d: Likewise.
+ * testsuite/gas/i386/enqcmd.d: Likewise.
+ * testsuite/gas/i386/movdir-intel.d: Likewise.
+ * testsuite/gas/i386/movdir.d: Likewise.
+ * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
+ * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
+ * testsuite/gas/i386/x86-64-movdir-intel.d: Likewise.
+ * testsuite/gas/i386/x86-64-movdir.d: Likewise.
+
+2020-10-02 Nick Clifton <nickc@redhat.com>
+
+ * testsuite/gas/arm/mve-vcvtne-it.d: Allow for padding inserted by
+ PE based targets.
+
+2020-10-01 Nick Clifton <nickc@redhat.com>
+
+ * config/obj-elf (elf_pseudo_table): Add attach_to_group.
+ (obj_elf_attach_to_group): New function.
+ * doc/as.texi: Document the new directive.
+ * NEWS: Mention the new feature.
+ * testsuite/gas/elf/attach-1.s: New test.
+ * testsuite/gas/elf/attach-1.d: New test driver.
+ * testsuite/gas/elf/attach-2.s: New test.
+ * testsuite/gas/elf/attach-2.d: New test driver.
+ * testsuite/gas/elf/attach-err.s: New test.
+ * testsuite/gas/elf/attach-err.d: New test driver.
+ * testsuite/gas/elf/attach-err.err: New test error output.
+ * testsuite/gas/elf/elf.exp: Run the new tests.
+
+2020-09-16 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR gas/26685
+ * config/tc-i386.c (process_suffix): Check the register operand
+ for the address size prefix if the memory operand is symbol(%rip).
+ * testsuite/gas/i386/x86-64-enqcmd.s: Add tests with RIP-relative
+ addressing.
+ * testsuite/gas/i386/x86-64-movdir.s: Likewise.
+ * testsuite/gas/i386/x86-64-enqcmd-intel.d: Updated.
+ * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
+ * testsuite/gas/i386/x86-64-movdir-intel.d: Likewise.
+ * testsuite/gas/i386/x86-64-movdir.d: Likewise.
+
+2020-09-30 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
+
+ * config/tc-aarch64.c: Add Cortex-A78 and Cortex-A78AE cores.
+ * doc/c-aarch64.texi: Update docs.
+ * NEWS: Update news.
+
+2020-09-30 Alex Coplan <alex.coplan@arm.com>
+
+ * NEWS: Mention recent Arm processor support.
+
+2020-09-30 Alex Coplan <alex.coplan@arm.com>
+
+ * config/tc-aarch64.c (aarch64_cpus): Add neoverse-n2.
+ * doc/c-aarch64.texi: Document support for Neoverse N2.
+
+2020-09-30 Alan Modra <amodra@gmail.com>
+
+ * config/obj-elf.c (obj_elf_change_section): Rename variable to
+ avoid shadowing warning.
+ * symbols.c (symbol_entry_find): Init all symbol_flags fields.
+
+2020-09-30 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
+
+ * config/tc-arm.c: Add cortex-a78 and cortex-a78ae cores.
+ * doc/c-arm.texi: Update docs.
+ * NEWS: Update news.
+ * testsuite/gas/arm/cpu-cortex-a78.d: New test.
+ * testsuite/gas/arm/cpu-cortex-a78ae.d: New test.
+
+2020-09-29 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
+
+ * NEWS: TRBE, ETE, ETMv4 and Cortex-X1 news updates.
+
+2020-09-28 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
+
+ * config/tc-arm.c: (arm_cpus): Add Cortex-X1.
+ * doc/c-arm.texi: Document -mcpu=cortex-x1.
+ * testsuite/gas/arm/cpu-cortex-x1.d: New test.
+
+2020-09-28 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
+
+ * testsuite/gas/aarch64/etm-ro-invalid.d: New test.
+ * testsuite/gas/aarch64/etm-ro-invalid.l: New test.
+ * testsuite/gas/aarch64/etm-ro-invalid.s: New test.
+ * testsuite/gas/aarch64/etm-ro.s: New test.
+ * testsuite/gas/aarch64/etm-wo-invalid.d: New test.
+ * testsuite/gas/aarch64/etm-wo-invalid.l: New test.
+ * testsuite/gas/aarch64/etm-wo-invalid.s: New test.
+ * testsuite/gas/aarch64/etm-wo.s: New test.
+ * testsuite/gas/aarch64/etm.s: New test.
+ * testsuite/gas/aarch64/sysreg.d: system register s2_1_c0_c3_0
+ disassembled now to trcstatr.
+
+2020-09-28 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
+
+ * config/tc-aarch64.c: (aarch64_cpus): Add Cortex-X1.
+ * doc/c-aarch64.texi: Document -mcpu=cortex-x1.
+
+2020-09-28 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
+
+ * testsuite/gas/aarch64/ete.d: New test.
+ * testsuite/gas/aarch64/ete.s: New test.
+
+2020-09-28 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
+
+ * testsuite/gas/aarch64/trbe-invalid.d: New test.
+ * testsuite/gas/aarch64/trbe-invalid.l: New test.
+ * testsuite/gas/aarch64/trbe-invalid.s: New test.
+ * testsuite/gas/aarch64/trbe.d: New test.
+ * testsuite/gas/aarch64/trbe.s: New test.
+
+2020-09-28 Alex Coplan <alex.coplan@arm.com>
+
+ * config/tc-arm.c (arm_cpus): Add FP16 to Neoverse V1.
+
+2020-09-28 Alex Coplan <alex.coplan@arm.com>
+
+ * config/tc-aarch64.c (aarch64_cpus): Group Neoverse cores together,
+ add missing F16 bit to Neoverse V1.
+
+2020-09-26 Alan Modra <amodra@gmail.com>
+
+ * config/tc-csky.c (parse_type_ctrlreg): Don't mask mach_flag
+ for csky_get_control_regno.
+ (csky_get_reg_val): Likewise when calling csky_get_general_regno.
+
+2020-09-24 Jim Wilson <jimw@sifive.com>
+
+ PR 26400
+ * config/tc-riscv.c (append_insn): If in absolute section, emit
+ error before add_relaxed_insn call.
+ * testsuite/gas/riscv/absolute-sec.d: New.
+ * testsuite/gas/riscv/absolute-sec.l: New.
+ * testsuite/gas/riscv/absolute-sec.s: New.
+
+2020-09-23 Mark Wielaard <mark@klomp.org>
+
+ * testsuite/gas/elf/dwarf-5-cu.d: Adjust expected output.
+
+2020-09-24 Alex Coplan <alex.coplan@arm.com>
+
+ * config/tc-arm.c (arm_cpus): Add Neoverse V1.
+ * doc/c-arm.texi: Document Neoverse V1 support.
+
+2020-09-24 Alex Coplan <alex.coplan@arm.com>
+
+ * config/tc-aarch64.c (aarch64_cpu_option_table): Add Neoverse V1.
+ * doc/c-aarch64.texi: Document Neoverse V1 support.
+
+2020-09-24 Alex Coplan <alex.coplan@arm.com>
+
+ * config/tc-arm.c (arm_cpus): Add Neoverse N2.
+ * doc/c-arm.texi: Document -mcpu=neoverse-n2.
+
+2020-09-24 Lili Cui <lili.cui@intel.com>
+
+ * NEWS: Add TDX.
+ * config/tc-i386.c (cpu_arch): Add .tdx.
+ (cpu_noarch): Likewise.
+ * doc/c-i386.texi: Document tdx.
+ * testsuite/gas/i386/i386.exp: Run tdx tests.
+ * testsuite/gas/i386/tdx.d: Likewise.
+ * testsuite/gas/i386/tdx.s: Likewise.
+ * testsuite/gas/i386/x86-64-tdx.d: Likewise.
+ * testsuite/gas/i386/x86-64-tdx.s: Likewise.
+
+2020-09-17 Cooper Qu <cooper.qu@linux.alibaba.com>
+
+ * config/tc-csky.c (parse_type_ctrlreg): Use function
+ csky_get_control_regno to operand.
+ (csky_get_reg_val): Likewise.
+ (is_reg_sp_with_bracket): Use function csky_get_reg_val
+ to parse operand.
+ (is_reg_sp): Refine.
+ (is_oimm_within_range): Fix, report error when operand
+ is not constant.
+ (parse_type_cpreg): Refine.
+ (parse_type_cpcreg): Refine.
+ (get_operand_value): Add handle of OPRND_TYPE_IMM5b_LS.
+ (md_assemble): Fix no error reporting somtimes when
+ operands number are not fit.
+ (csky_addc64): Refine.
+ (csky_subc64): Refine.
+ (csky_or64): Refine.
+ (v1_work_fpu_fo): Refine.
+ (v1_work_fpu_read): Refine.
+ (v1_work_fpu_writed): Refine.
+ (v1_work_fpu_readd): Refine.
+ (v2_work_addc): New function, strengthen the operands legality
+ check of addc.
+ * testsuite/gas/csky/all.d : Use register number format when
+ disassemble register name by default.
+ * testsuite/gas/csky/cskyv2_all.d : Likewise.
+ * testsuite/gas/csky/trust.d: Likewise.
+ * testsuite/gas/csky/cskyv2_ck860.d : Fix.
+ * testsuite/gas/csky/trust.s : Fix.
+
+2020-09-23 Lili Cui <lili.cui@intel.com>
+
+ * NEWS: Add Key Locker.
+ * config/tc-i386.c (cpu_arch): Add .kl and .wide_kl.
+ (cpu_noarch): Likewise.
+ * doc/c-i386.texi: Document kl and wide_kl.
+ * testsuite/gas/i386/i386.exp: Run keylocker tests.
+ * testsuite/gas/i386/keylocker-intel.d: New test.
+ * testsuite/gas/i386/keylocker.d: Likewise.
+ * testsuite/gas/i386/keylocker.s: Likewise.
+ * testsuite/gas/i386/x86-64-keylocker-intel.d: Likewise.
+ * testsuite/gas/i386/x86-64-keylocker.d: Likewise.
+ * testsuite/gas/i386/x86-64-keylocker.s: Likewise.
+ * testsuite/gas/i386/x86-64-property-10.d: Likewise.
+ * testsuite/gas/i386/property-10.d: Likewise.
+ * testsuite/gas/i386/property-10.s: Likewise.
+
+2020-09-21 Alan Modra <amodra@gmail.com>
+
+ PR 26569
+ * config/tc-riscv.c (append_insn): Don't tie off frags at CALL
+ relocs.
+ (riscv_call): Tie them off after the jalr.
+ (md_apply_fix): Zero fx_size of RELAX fixup.
+
+2020-09-018 David Faust <david.faust@oracle.com>
+
+ * testsuite/gas/bpf/alu-xbpf.d: New file.
+ * testsuite/gas/bpf/alu-xbpf.s: Likewise.
+ * testsuite/gas/bpf/alu32-xbpf.d: Likewise.
+ * testsuite/gas/bpf/alu32-xbpf.d: Likewise.
+ * testuiste/gas/bpf/bpf.exp: Run new tests.
+
+2020-09-18 Tucker <tuckkern+sourceware@gmail.com>
+
+ PR 26556
+ * read.c (bss_alloc): Convert size parameter from octets to
+ bytes.
+
+2020-09-17 Alan Modra <amodra@gmail.com>
+
+ * testsuite/gas/i386/i386.exp: Return early if not x86.
+
2020-09-16 Alan Modra <amodra@gmail.com>
* config/obj-elf.c (obj_elf_visibility, elf_frob_symbol): Adjust
add_line_strp and set symbol offset for DWARF2_LINE_VERSION 5.
(out_debug_line): Call out_dir_and_file_list with line_seg and
sizeof_offset.
- * gas/testsuite/gas/elf/dwarf-5-file0.d: Expect indirect line
+ * testsuite/gas/elf/dwarf-5-file0.d: Expect indirect line
strings.
2020-09-07 Mark Wielaard <mark@klomp.org>
* dwarf2dbg.c (dwarf2_directive_filename): Initialize with_md5 to
FALSE.
- * gas/testsuite/gas/elf/dwarf-5-file0.s: Add a random bignum.
+ * testsuite/gas/elf/dwarf-5-file0.s: Add a random bignum.
2020-09-01 Mark Wielaard <mark@klomp.org>
2020-08-28 Cooper Qu <cooper.qu@linux.alibaba.com>
- * gas/config/tc-csky.c (md_begin): Set attributes.
+ * config/tc-csky.c (md_begin): Set attributes.
(isa_flag): Change type to unsigned 64 bits.
(struct csky_cpu_info): Likewise.
(struct csky_macro_info): Likewise.
2020-08-25 Alan Modra <amodra@gmail.com>
PR 26501
- * gas/config/tc-tic54x.c (tic54x_undefined_symbol): Properly treat
+ * config/tc-tic54x.c (tic54x_undefined_symbol): Properly treat
misc_symbol_hash entries without values.
2020-08-25 Alan Modra <amodra@gmail.com>
PR 26500
- * tc-tic4x.c (tic4x_inst_make): Don't die on terminating insn
- with name = "".
+ * config/tc-tic4x.c (tic4x_inst_make): Don't die on terminating
+ insn with name = "".
2020-08-25 Alan Modra <amodra@gmail.com>
(csky_cpus): Add item for CK860.
(md_begin): Enable DSP for CK810 and CK807 by default.
(md_apply_fix): Fix CKCORE_TLS_IE32 relocation failure.
- * gas/testsuite/gas/csky/cskyv2_all.d: Change 'sync 0'
- to 'sync'.
- * gas/testsuite/gas/csky/cskyv2_all.s: Likewise.
- * gas/testsuite/gas/csky/cskyv2_ck860.d: New.
- * gas/testsuite/gas/csky/cskyv2_ck860.s: New.
- * gas/testsuite/gas/csky/enhance_dsp.d: Change plsli.u16
- to plsli.16.
- * gas/testsuite/gas/csky/enhance_dsp.s: Likewise.
+ * testsuite/gas/csky/cskyv2_all.d: Change 'sync 0' to 'sync'.
+ * testsuite/gas/csky/cskyv2_all.s: Likewise.
+ * testsuite/gas/csky/cskyv2_ck860.d: New.
+ * testsuite/gas/csky/cskyv2_ck860.s: New.
+ * testsuite/gas/csky/enhance_dsp.d: Change plsli.u16 to plsli.16.
+ * testsuite/gas/csky/enhance_dsp.s: Likewise.
2020-08-24 Alan Modra <amodra@gmail.com>
2020-08-04 Christian Groessler <chris@groessler.org>
- * gas/testsuite/gas/z8k/inout.d: Adapt to correct encoding of
+ * testsuite/gas/z8k/inout.d: Adapt to correct encoding of
"sout/soutb #imm,reg"
2020-08-04 H.J. Lu <hongjiu.lu@intel.com>
2020-08-02 Mark Wielaard <mark@klomp.org>
- * gas/dwarf2dbg.c (out_dir_and_file_list): For DWARF5 emit at
+ * dwarf2dbg.c (out_dir_and_file_list): For DWARF5 emit at
least one directory if there is at least one file. Use dirs[1]
if dirs[0] is not set, or if there is no dirs[1] the current
working directory. Use files[1] filename, when files[0] filename
* dwarf2dbg.c (out_debug_info): Emit unit type and abbrev offset
for DWARF5.
- * gas/testsuite/gas/elf/dwarf-4-cu.d: New file.
- * gas/testsuite/gas/elf/dwarf-4-cu.s: Likewise.
- * gas/testsuite/gas/elf/dwarf-5-cu.d: Likewise.
- * gas/testsuite/gas/elf/dwarf-5-cu.s: Likewise.
+ * testsuite/gas/elf/dwarf-4-cu.d: New file.
+ * testsuite/gas/elf/dwarf-4-cu.s: Likewise.
+ * testsuite/gas/elf/dwarf-5-cu.d: Likewise.
+ * testsuite/gas/elf/dwarf-5-cu.s: Likewise.
* testsuite/gas/elf/elf.exp: Run dwarf-4-cu and dwarf-5-cu.
2020-08-02 Mark Wielaard <mark@klomp.org>
2020-06-29 H.J. Lu <hongjiu.lu@intel.com>
- * tc-i386.c (build_vex_prefix): Support VEX base opcode length > 1.
+ * config/tc-i386.c (build_vex_prefix): Support VEX base opcode
+ length > 1.
(md_assemble): Don't process ImmExt without operands.
2020-06-29 Hans-Peter Nilsson <hp@bitrange.com>
2020-05-27 Simon Cook <simon.cook@embecosm.com>
- * config/tc-riscv.c (riscv_init_csr_hash): NULL initilize next
- pointer when creating struct riscv_csr_extra.
+ * config/tc-riscv.c (riscv_init_csr_hash): NULL initilize next
+ pointer when creating struct riscv_csr_extra.
2020-05-26 H.J. Lu <hongjiu.lu@intel.com>
-mpriv-spec=1.11.
* testsuite/gas/riscv/priv-reg-fail-fext.l: Likewise. There are some
version warnings for the test case.
- * gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.d: Likewise.
- * gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.l: Likewise.
- * gas/testsuite/gas/riscv/priv-reg-fail-read-only-02.d: Likewise.
- * gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.d: Likewise.
- * gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.l: Likewise.
- * gas/testsuite/gas/riscv/priv-reg-fail-version-1p9.d: New test case.
+ * testsuite/gas/riscv/priv-reg-fail-read-only-01.d: Likewise.
+ * testsuite/gas/riscv/priv-reg-fail-read-only-01.l: Likewise.
+ * testsuite/gas/riscv/priv-reg-fail-read-only-02.d: Likewise.
+ * testsuite/gas/riscv/priv-reg-fail-rv32-only.d: Likewise.
+ * testsuite/gas/riscv/priv-reg-fail-rv32-only.l: Likewise.
+ * testsuite/gas/riscv/priv-reg-fail-version-1p9.d: New test case.
Check whether the CSR is valid when privilege version 1.9 is choosed.
- * gas/testsuite/gas/riscv/priv-reg-fail-version-1p9.l: Likewise.
- * gas/testsuite/gas/riscv/priv-reg-fail-version-1p9p1.d: New test case.
+ * testsuite/gas/riscv/priv-reg-fail-version-1p9.l: Likewise.
+ * testsuite/gas/riscv/priv-reg-fail-version-1p9p1.d: New test case.
Check whether the CSR is valid when privilege version 1.9.1 is choosed.
- * gas/testsuite/gas/riscv/priv-reg-fail-version-1p9p1.l: Likewise.
- * gas/testsuite/gas/riscv/priv-reg-fail-version-1p10.d: New test case.
+ * testsuite/gas/riscv/priv-reg-fail-version-1p9p1.l: Likewise.
+ * testsuite/gas/riscv/priv-reg-fail-version-1p10.d: New test case.
Check whether the CSR is valid when privilege version 1.10 is choosed.
- * gas/testsuite/gas/riscv/priv-reg-fail-version-1p10.l: Likewise.
- * gas/testsuite/gas/riscv/priv-reg-fail-version-1p11.d: New test case.
+ * testsuite/gas/riscv/priv-reg-fail-version-1p10.l: Likewise.
+ * testsuite/gas/riscv/priv-reg-fail-version-1p11.d: New test case.
Check whether the CSR is valid when privilege version 1.11 is choosed.
- * gas/testsuite/gas/riscv/priv-reg-fail-version-1p11.l: Likewise.
+ * testsuite/gas/riscv/priv-reg-fail-version-1p11.l: Likewise.
* config/tc-riscv.c (DEFAULT_RISCV_ISA_SPEC): Default configure option
setting. You can set it by configure option --with-priv-spec.
(riscv_set_default_priv_spec): New function used to set the default
* testsuite/gas/i386/solaris/x86-64-branch-3.d: New file.
* testsuite/gas/i386/solaris/x86-64-jump.d: Incorporate changes to
testsuite/gas/i386/x86-64-jump.d.
- * gas/testsuite/gas/i386/solaris/x86-64-mpx-branch-1.d:
+ * testsuite/gas/i386/solaris/x86-64-mpx-branch-1.d:
Incorporate changes to
gas/testsuite/gas/i386/x86-64-mpx-branch-1.d.
* testsuite/gas/i386/solaris/x86-64-mpx-branch-2.d : Incorporate
2020-02-01 Anthony Green <green@moxielogic.com>
- * config/tc-moxie.c (md_begin): Don't force big-endian mode.
+ * config/tc-moxie.c (md_begin): Don't force big-endian mode.
2020-01-31 Sandra Loosemore <sandra@codesourcery.com>
projects / binutils-gdb.git / blobdiff