+2010-06-14 Alan Modra <amodra@gmail.com>
+
+ * config/tc-ppc.c (md_assemble): Emit APUinfo section for
+ PPC_OPCODE_E500.
+
+2010-06-11 Jan Beulich <jbeulich@novell.com>
+
+ * config/tc-i386.c (md_parse_option): Ignore impossible processor
+ types.
+ (show_arch): New parameter 'check'.
+ (md_show_usage): Adjust calls to show_arch().
+
+2010-06-10 H.J. Lu <hongjiu.lu@intel.com>
+
+ * config/tc-i386.c (update_code_flag): New.
+ (set_code_flag): Use it.
+ (i386_target_format): Replace set_code_flag with update_code_flag.
+
+2010-06-10 Tristan Gingold <gingold@adacore.com>
+
+ * config/obj-som.h: Includes som/reloc.h
+
+2010-06-10 Jan Beulich <jbeulich@novell.com>
+
+ * config/tc-i386.c (cpu_arch): Add comment.
+ (i386_target_format): Set cpu_arch_isa_flags and cpu_arch_tune_flags
+ from the generic entries of cpu_arch[].
+
2010-06-08 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
- * config/tc-arm.c (operand_parse_code): Add OP_RRnpctw enum
+ * config/tc-arm.c (operand_parse_code): Add OP_RRnpctw enum
value.
(parse_operands): Add support for OP_RRnpctw.
- (insns): Update floating-point load/store multiples so the
+ (insns): Update floating-point load/store multiples so the
first register is of type OP_RRnpctw.
2010-06-08 Quentin Neill <quentin.neill@amd.com>