+2020-10-26 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR gas/26778
+ * * dwarf2dbg.c (num_of_auto_assigned): New.
+ (allocate_filenum): Increment num_of_auto_assigned.
+ (dwarf2_directive_filename): Clear the slots auto-assigned
+ before the first .file <NUMBER> directive was seen.
+ * testsuite/gas/i386/dwarf4-line-1.d: New file.
+ * testsuite/gas/i386/dwarf4-line-1.s: Likewise.
+ * testsuite/gas/i386/i386.exp: Run dwarf4-line-1.
+
+2020-10-26 Cooper Qu <cooper.qu@linux.alibaba.com>
+
+ * config/tc-csky.c (dump_literals): Fix the literal dump
+ of big vector constant.
+
+2020-10-26 Cooper Qu <cooper.qu@linux.alibaba.com>
+
+ * testsuite/gas/csky/enhance_dsp.s : Change plsl.u16 to plsl.16.
+ * testsuite/gas/csky/enhance_dsp.d : Change plsl.u16 to plsl.16.
+
+2020-10-26 Cooper Qu <cooper.qu@linux.alibaba.com>
+
+ * config/tc-csky.c (md_begin): Add version flag in eflag.
+
+2020-10-26 Cooper Qu <cooper.qu@linux.alibaba.com>
+
+ * config/tc-csky.c (get_operand_value): Add handler for
+ OPRND_TYPE_IMM5b_VSH and OPRND_TYPE_VREG_WITH_INDEX.
+ * testsuite/gas/csky/csky_vdsp.d : Fix the disassembling for
+ vector register.
+
+2020-10-26 Lili Cui <lili.cui@intel.com>
+
+ * testsuite/gas/i386/avx-vnni.d: Change psuedo prefix from
+ {vex3} to {vex}
+ * testsuite/gas/i386/x86-64-avx-vnni.d: Likewise.
+
+2020-10-21 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
+
+ PR target/26763
+ * config/tc-arm.c (parse_address_main): Add new MVE addressing mode
+ check.
+ * testsuite/gas/arm/mve-vldr-vstr-bad.d: New test.
+ * testsuite/gas/arm/mve-vldr-vstr-bad.l: Likewise.
+ * testsuite/gas/arm/mve-vldr-vstr-bad.s: Likewise.
+
+2020-10-20 Dr. David Alan Gilbert <dgilbert@redhat.com>
+
+ * config/tc-arc.c (emit_insn0): Fix printf format.
+
+2020-10-20 Ganesh Gopalasubramanian <Ganesh.Gopalasubramanian@amd.com>
+
+ * config/tc-i386.c (cpu_arch): Add CPU_ZNVER3_FLAGS flags.
+ (i386_align_code): Add PROCESSOR_ZNVER cases.
+ * doc/c-i386.texi: Add znver3, snp, invlpgb and tlbsync.
+ * gas/i386/i386.exp: Add new znver3 test cases.
+ * gas/i386/arch-14-znver3.d: New.
+ * gas/i386/arch-14.d: New.
+ * gas/i386/arch-14.s: New.
+ * gas/i386/invlpgb.d: New.
+ * gas/i386/invlpgb64.d: New.
+ * gas/i386/invlpgb.s: New.
+ * gas/i386/snp.d: New.
+ * gas/i386/snp64.d: New.
+ * gas/i386/snp.s: New.
+ * gas/i386/tlbsync.d: New.
+ * gas/i386/tlbsync.s: New.
+ * gas/i386/x86-64-arch-4-znver3.d: New.
+ * gas/i386/x86-64-arch-4.d: New.
+ * gas/i386/x86-64-arch-4.s: New.
+
+2020-10-17 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR gas/25878
+ PR gas/26740
+ * testsuite/gas/i386/dwarf5-line-4.d: New file.
+ * testsuite/gas/i386/dwarf5-line-4.s: Likewise.
+ * testsuite/gas/i386/i386.exp: Run dwarf5-line-4.
+
+2020-10-17 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR gas/25878
+ PR gas/26740
+ * testsuite/gas/i386/dwarf5-line-3.s: Replace dwarf5-line-2.S
+ with dwarf5-line-3.S.
+ * testsuite/gas/i386/dwarf5-line-3.d: Updated.
+
+2020-10-17 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR gas/25878
+ PR gas/26740
+ * dwarf2dbg.c (allocate_filename_to_slot): Don't reuse the slot 1
+ here.
+ (dwarf2_where): Restore as_where.
+ (dwarf2_directive_filename): Clear the slot 1 if it was assigned
+ to the input file.
+ * testsuite/gas/i386/dwarf5-line-2.d: New file.
+ * testsuite/gas/i386/dwarf5-line-2.s: Likewise.
+ * testsuite/gas/i386/dwarf5-line-3.d: Likewise.
+ * testsuite/gas/i386/dwarf5-line-3.s: Likewise.
+ * testsuite/gas/i386/i386.exp: Run dwarf5-line-2 and
+ dwarf5-line-3.
+
+2020-10-16 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR gas/25878
+ PR gas/26740
+ * dwarf2dbg.c (file_entry): Remove auto_assigned.
+ (assign_file_to_slot): Remove the auto_assign argument.
+ (allocate_filenum): Updated.
+ (allocate_filename_to_slot): Reuse the input file entry in the
+ file table.
+ (dwarf2_where): Replace as_where with as_where_physical.
+ * testsuite/gas/i386/dwarf5-line-1.d: New file.
+ * testsuite/gas/i386/dwarf5-line-1.s: Likewise.
+ * testsuite/gas/i386/i386.exp: Run dwarf5-line-1.
+
+2020-10-16 Lili Cui <lili.cui@intel.com>
+
+ * config/tc-i386.c (cpu_flags_match): Move Pseudo Prefix check
+ to ...
+ (match_template): Here.
+ * testsuite/gas/i386/avx-vnni-inval.l: New file.
+ * testsuite/gas/i386/avx-vnni-inval.s: Likewise.
+ * testsuite/gas/i386/avx-vnni.d: Delete invalid {vex2} test.
+ * testsuite/gas/i386/avx-vnni.s: Likewise.
+ * testsuite/gas/i386/i386.exp: Add AVX VNNI invalid tests.
+ * testsuite/gas/i386/x86-64-avx-vnni-inval.l: New file.
+ * testsuite/gas/i386/x86-64-avx-vnni-inval.s: Likewise.
+ * testsuite/gas/i386/x86-64-avx-vnni.d: Delete invalid {vex2} test.
+ * testsuite/gas/i386/x86-64-avx-vnni.s: Likewise.
+
+2020-10-14 H.J. Lu <hongjiu.lu@intel.com>
+ Lili Cui <lili.cui@intel.com>
+
+ * NEWS: Add Intel AVX VNNI.
+ * config/tc-i386.c (cpu_arch): Add .avx_vnni and noavx_vnni.
+ (cpu_flags_match): Support CpuVEX_PREFIX.
+ * doc/c-i386.texi: Document .avx_vnni, noavx_vnni and how to
+ encode Intel VNNI instructions with VEX prefix.
+ * testsuite/gas/i386/avx-vnni.d: New file.
+ * testsuite/gas/i386/avx-vnni.s: Likewise.
+ * testsuite/gas/i386/x86-64-avx-vnni.d: Likewise.
+ * testsuite/gas/i386/x86-64-avx-vnni.s: Likewise.
+ * testsuite/gas/i386/i386.exp: Run AVX VNNI tests.
+
+2020-10-14 Lili Cui <lili.cui@intel.com>
+
+ * NEWS: Add Intel HRESET.
+ * config/tc-i386.c (cpu_arch): Add .hreset.
+ (cpu_noarch): Likewise.
+ * doc/c-i386.texi: Document .hreset, nohreset.
+ * testsuite/gas/i386/i386.exp: Run HRESET tests.
+ * testsuite/gas/i386/hreset.d: New file.
+ * testsuite/gas/i386/x86-64-hreset.d: Likewise.
+ * testsuite/gas/i386/hreset.s: Likewise.
+
+2020-10-14 Lili Cui <lili.cui@intel.com>
+
+ * NEWS: Add Intel UINTR.
+ * config/tc-i386.c (cpu_arch): Add .uintr.
+ (cpu_noarch): Likewise.
+ * doc/c-i386.texi: Document .uintr and nouintr.
+ * testsuite/gas/i386/i386.exp: Run UINTR tests.
+ * testsuite/gas/i386/x86-64-uintr.d: Likewise.
+ * testsuite/gas/i386/x86-64-uintr.s: Likewise.
+
+2020-10-14 H.J. Lu <hongjiu.lu@intel.com>
+
+ * config/tc-i386.c (load_insn_p): Check opcodeprefix == 0 for
+ base_opcode == 0xfc7.
+ (match_template): Likewise.
+ (process_suffix): Check opcodeprefix == PREFIX_0XF2 for CRC32.
+ (check_byte_reg): Likewise.
+ (output_insn): Don't add the 0xf3 prefix twice for PadLock
+ instructions. Don't add prefix from non-VEX/EVEX base_opcode.
+
+2020-10-13 H.J. Lu <hongjiu.lu@intel.com>
+
+ * config/tc-i386.c (build_vex_prefix): Replace vexopcode with
+ opcodeprefix.
+ (build_evex_prefix): Likewise.
+ (is_any_vex_encoding): Don't check vexopcode.
+ (output_insn): Handle opcodeprefix.
+
+2020-10-09 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR gas/26703
+ * config/tc-i386.c (xstate): Add xstate_mask.
+ (md_assemble): Check i.types[j], instead of i.tm.operand_types[j],
+ for xstate. Set xstate_mask, instead of xstate_zmm, for RegMask.
+ (output_insn): Update for GNU_PROPERTY_X86_ISA_1_V[234]. Update
+ xstate for mask register and VSIB.
+ * testsuite/gas/i386/i386.exp: Run more GNU_PROPERTY tests.
+ * testsuite/gas/i386/property-1.s: Updated to the current
+ GNU_PROPERTY_X86_ISA_1_USED value.
+ * testsuite/gas/i386/property-2.s: Only keep cmove.
+ * testsuite/gas/i386/property-3.s: Changed to addsubpd.
+ * testsuite/gas/i386/property-1.d: Updated.
+ * testsuite/gas/i386/property-2.d: Likewise.
+ * testsuite/gas/i386/property-3.d: Likewise.
+ * testsuite/gas/i386/property-4.d: Likewise.
+ * testsuite/gas/i386/property-5.d: Likewise.
+ * testsuite/gas/i386/property-6.d: Likewise.
+ * testsuite/gas/i386/x86-64-property-1.d: Likewise.
+ * testsuite/gas/i386/x86-64-property-2.d: Likewise.
+ * testsuite/gas/i386/x86-64-property-3.d: Likewise.
+ * testsuite/gas/i386/x86-64-property-4.d: Likewise.
+ * testsuite/gas/i386/x86-64-property-5.d: Likewise.
+ * testsuite/gas/i386/x86-64-property-6.d: Likewise.
+ * testsuite/gas/i386/x86-64-property-7.d: Likewise.
+ * testsuite/gas/i386/x86-64-property-8.d: Likewise.
+ * testsuite/gas/i386/x86-64-property-9.d: Likewise.
+ * testsuite/gas/i386/property-11.d: New file.
+ * testsuite/gas/i386/property-11.s: Likewise.
+ * testsuite/gas/i386/property-12.d: Likewise.
+ * testsuite/gas/i386/property-12.s: Likewise.
+ * testsuite/gas/i386/property-13.d: Likewise.
+ * testsuite/gas/i386/property-13.s: Likewise.
+ * testsuite/gas/i386/x86-64-property-11.d: Likewise.
+ * testsuite/gas/i386/x86-64-property-12.d: Likewise.
+ * testsuite/gas/i386/x86-64-property-13.d: Likewise.
+ * testsuite/gas/i386/x86-64-property-14.d: Likewise.
+ * testsuite/gas/i386/x86-64-property-14.s: Likewise.
+
+2020-10-06 Alex Coplan <alex.coplan@arm.com>
+
+ PR 26699
+ * config/tc-aarch64.c (asm_barrier_opt): Delete.
+ (parse_barrier): Fix bogus type punning.
+ * testsuite/gas/aarch64/system.d: Update disassembly.
+ * testsuite/gas/aarch64/system.s: Add isb sy test.
+
+2020-10-06 Sergey Belyashav <sergey.belyashov@gmail.com>
+
+ PR 26692
+ * config/tc-z80.c (md_begin): Ensure that xpressions are empty
+ before using them.
+ (unify_indexed): Likewise.
+ (z80_start_line_hook): Improve hash sign handling when SDCC
+ compatibility mode enabled.
+ (md_parse_exp_not_indexed): Improve indirect addressing
+ detection.
+ (md_pseudo_table): Accept hd64 as an alias of z810.
+
+2020-10-06 Alan Modra <amodra@gmail.com>
+
+ * testsuite/gas/elf/sh-link-zero.s: Don't start directives in
+ first column. Don't use numeric labels.
+
2020-10-05 Kamil Rytarowski <n54@gmx.com>
* configure.tgt (aarch64*-*-netbsd*): Add target.
projects / binutils-gdb.git / blobdiff