+2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
+
+ * config/tc-arm.c (struct asm_opcode): Make avalue a full int.
+ (BAD_ODD, BAD_EVEN, BAD_SIMD_TYPE): New errors.
+ (enum operand_parse_code): Handle new operands.
+ (parse_operands): Likewise.
+ (M_MNEM_vabav, M_MNEM_vmladav, M_MNEM_vmladava, M_MNEM_vmladavx,
+ M_MNEM_vmladavax, M_MNEM_vmlsdav, M_MNEM_vmlsdava, M_MNEM_vmlsdavx,
+ M_MNEM_vmlsdavax): Define new encodings.
+ (NEON_SHAPE_DEF): Add new shape.
+ (neon_check_type): Use BAD_SIMD_TYPE.
+ (mve_encode_rqq): New encoding helper function.
+ (do_mve_vabav, do_mve_vmladav): New encoding functions.
+ (mCEF): New MACRO.
+ * testsuite/gas/arm/mve-vabav-bad.d: New test.
+ * testsuite/gas/arm/mve-vabav-bad.l: New test.
+ * testsuite/gas/arm/mve-vabav-bad.s: New test.
+ * testsuite/gas/arm/mve-vmladav-bad.d: New test.
+ * testsuite/gas/arm/mve-vmladav-bad.l: New test.
+ * testsuite/gas/arm/mve-vmladav-bad.s: New test.
+ * testsuite/gas/arm/mve-vmlav-bad.d: New test.
+ * testsuite/gas/arm/mve-vmlav-bad.l: New test.
+ * testsuite/gas/arm/mve-vmlav-bad.s: New test.
+ * testsuite/gas/arm/mve-vmlsdav-bad.d: New test.
+ * testsuite/gas/arm/mve-vmlsdav-bad.l: New test.
+ * testsuite/gas/arm/mve-vmlsdav-bad.s: New test.
+
+2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
+
+ * config/tc-arm.c (do_neon_abs_neg): Make it accept MVE variant.
+ (insns): Change vabs and vneg entries to accept MVE variants.
+ * testsuite/gas/arm/mve-vabsneg-bad-1.d: New test.
+ * testsuite/gas/arm/mve-vabsneg-bad-1.l: New test.
+ * testsuite/gas/arm/mve-vabsneg-bad-1.s: New test.
+ * testsuite/gas/arm/mve-vabsneg-bad-2.d: New test.
+ * testsuite/gas/arm/mve-vabsneg-bad-2.l: New test.
+ * testsuite/gas/arm/mve-vabsneg-bad-2.s: New test.
+
+2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
+
+ * config/tc-arm.c (enum it_instruction_type): Rename to...
+ (enum pred_instruction_type): ... this. Include VPT types.
+ (it_insn_type): Rename to ...
+ (pred_insn_type): .. this.
+ (arm_it): Change comment.
+ (enum arm_reg_type): Add new value.
+ (reg_expected_msgs): New entry.
+ (asm_opcode): Add mayBeVecPred member.
+ (BAD_SYNTAX, BAD_NOT_VPT, BAD_OUT_VPT, BAD_VPT_COND, MVE_NOT_IT,
+ MVE_NOT_VPT, MVE_BAD_PC, MVE_BAD_SP): New diagnostic MACROS.
+ (arm_vcond_hsh): New table for vector condition codes.
+ (now_it): Rename to ...
+ (now_pred): ... this.
+ (now_it_compatible): Rename to ...
+ (now_pred_compatible): ... this.
+ (in_it_block): Rename to ...
+ (in_pred_block): ... this.
+ (handle_it_state): Rename to ...
+ (handle_pred_state): ... this. And change it to accept VPT blocks.
+ (set_it_insn_type): Rename to ...
+ (set_pred_insn_type): ... this.
+ (set_it_insn_type_nonvoid): Rename to ...
+ (set_pred_insn_type_nonvoid): ... this.
+ (set_it_insn_type_last): Rename to ...
+ (set_pred_insn_type_last): ... this.
+ (record_feature_use): Moved.
+ (mark_feature_used): Likewise.
+ (parse_typed_reg_or_scalar): Add new case for REG_TYPE_MQ.
+ (emit_insn): Use renamed functions and variables.
+ (enum operand_parse_code): Add new operands.
+ (parse_operands): Handle new operands.
+ (do_scalar_fp16_v82_encode): Change predication detection.
+ (do_it): Use renamed functions and variables.
+ (do_t_add_sub): Likewise.
+ (do_t_arit3): Likewise.
+ (do_t_arit3c): Likewise.
+ (do_t_blx): Likewise.
+ (do_t_branch): Likewise.
+ (do_t_bkpt_hlt1): Likewise.
+ (do_t_branch23): Likewise.
+ (do_t_bx): Likewise.
+ (do_t_bxj): Likewise.
+ (do_t_cond): Likewise.
+ (do_t_csdb): Likewise.
+ (do_t_cps): Likewise.
+ (do_t_cpsi): Likewise.
+ (do_t_cbz): Likewise.
+ (do_t_it): Likewise.
+ (do_mve_vpt): New function to handle VPT blocks.
+ (encode_thumb2_multi): Use renamed functions and variables.
+ (do_t_ldst): Use renamed functions and variables.
+ (do_t_mov_cmp): Likewise.
+ (do_t_mvn_tst): Likewise.
+ (do_t_mul): Likewise.
+ (do_t_nop): Likewise.
+ (do_t_neg): Likewise.
+ (do_t_rsb): Likewise.
+ (do_t_setend): Likewise.
+ (do_t_shift): Likewise.
+ (do_t_smc): Likewise.
+ (do_t_tb): Likewise.
+ (do_t_udf): Likewise.
+ (do_t_loloop): Likewise.
+ (do_neon_cvt_1): Likewise.
+ (do_vfp_nsyn_cvt_fpv8): Likewise.
+ (do_vsel): Likewise.
+ (do_vmaxnm): Likewise.
+ (do_vrint_1): Likewise.
+ (do_crypto_2op_1): Likewise.
+ (do_crypto_3op_1): Likewise.
+ (do_crc32_1): Likewise.
+ (it_fsm_pre_encode): Likewise.
+ (it_fsm_post_encode): Likewise.
+ (force_automatic_it_block_close): Likewise.
+ (check_it_blocks_finished): Likewise.
+ (check_pred_blocks_finished): Likewise.
+ (arm_cleanup): Likewise.
+ (now_it_add_mask): Rename to ...
+ (now_pred_add_mask): ... this. And use new variables and functions.
+ (NEON_ENC_TAB): Add entries for vabdl, vaddl and vsubl.
+ (N_I_MVE, N_F_MVE, N_SU_MVE): New MACROs.
+ (neon_check_type): Generalize error message.
+ (mve_encode_qqr): New MVE generic encoding function.
+ (neon_dyadic_misc): Change to accept MVE variants.
+ (do_neon_dyadic_if_su): Likewise.
+ (do_neon_addsub_if_i): Likewise.
+ (do_neon_dyadic_long): Likewise.
+ (vfp_or_neon_is_neon): Add extra checks.
+ (check_simd_pred_availability): Helper function to check SIMD
+ instruction availability with respect to predication.
+ (enum opcode_tag): New suffix value.
+ (opcode_lookup): Change to handle VPT blocks.
+ (new_automatic_it_block): Rename to ...
+ (close_automatic_it_block): ...this.
+ (TxCE, TxC3, TxC3w, TUE, TUEc, TUF, CE, C3, ToC, ToU,
+ toC, toU, CL, cCE, cCL, C3E, xCM_, UE, UF, NUF, nUF,
+ NCE_tag, NCE, NCEF, nCE_tag, nCE, nCEF): Add default value for new
+ field.
+ (mCEF, mnCEF, mnCE, MNUF, mnUF, mToC, MNCE, MNCEF): New MACROs.
+ (insns): Redefine vadd, vsub, cabd, vabdl, vaddl, vsubl to accept MVE
+ variants. Add entries for vscclrm, and vpst.
+ (md_begin): Add arm_vcond_hsh initialization.
+ * config/tc-arm.h (enum it_state): Rename to...
+ (enum pred_state): ...this.
+ (struct current_it): Rename to...
+ (struct current_pred): ...this.
+ (enum pred_type): New enum.
+ (struct arm_segment_info_type): Use current_pred.
+ * testsuite/gas/arm/armv8_3-a-fp-bad.l: Update error message.
+ * testsuite/gas/arm/armv8_3-a-simd-bad.l: Update error message.
+ * testsuite/gas/arm/dotprod-illegal.l: Update error message.
+ * testsuite/gas/arm/mve-vaddsubabd-bad-1.d: New test.
+ * testsuite/gas/arm/mve-vaddsubabd-bad-1.l: New test.
+ * testsuite/gas/arm/mve-vaddsubabd-bad-1.s: New test.
+ * testsuite/gas/arm/mve-vaddsubabd-bad-2.d: New test.
+ * testsuite/gas/arm/mve-vaddsubabd-bad-2.l: New test.
+ * testsuite/gas/arm/mve-vaddsubabd-bad-2.s: New test.
+ * testsuite/gas/arm/mve-vpst-bad.d: New test.
+ * testsuite/gas/arm/mve-vpst-bad.l: New test.
+ * testsuite/gas/arm/mve-vpst-bad.s: New test.
+ * testsuite/gas/arm/neon-ldst-es-bad.l: Updated error message.
+
+2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
+
+ * config/tc-arm.c (mve_ext, mve_fp_ext): New features.
+ (armv8_1m_main_ext_table): Add new extensions.
+ (aeabi_set_public_attributes): Translate new features to new build attributes.
+ (arm_convert_symbolic_attribute): Add Tag_MVE_arch.
+ * doc/c-arm.texi: Document new extensions and new build attribute.
+
+2019-05-15 John Darrington <john@darrington.wattle.id.au>
+
+ * config/tc-s12z.c (register_prefix): New variable. (md_show_usage,
+ md_parse_option): parse the new option.
+ (lex_reg_name): Scan the prefix if one is set.
+ * doc/c-s12z.texi (S12Z-Opts): Document the new option.
+ * testsuite/gas/s12z/reg-prefix.d: New file.
+ * testsuite/gas/s12z/reg-prefix.s: New file.
+ * testsuite/gas/s12z/s12z.exp: Add them.
+
+2019-05-14 John Darrington <john@darrington.wattle.id.au>
+
+ * doc/as.texi (Machine Dependencies): Fix misaligned menu entry.
+
+2019-05-15 Alan Modra <amodra@gmail.com>
+
+ * config/tc-csky.c (md_convert_frag): Initialise trailing
+ padding for COND_JUMP_PIC.
+
+2019-05-15 Alan Modra <amodra@gmail.com>
+
+ * dwarf2dbg.c: Whitespace fixes.
+ (get_filenum): Don't strdup "file". Adjust error message.
+ (dwarf2_directive_filename): Use an unsigned type for "num".
+ Catch truncation of file number and overflow of get_filenum
+ XRESIZEVEC multiplication. Delete dead code.
+
+2019-05-15 Alan Modra <amodra@gmail.com>
+
+ PR 24538
+ * config/tc-tic54x.c (tic54x_start_line_hook): Do skip end of line
+ chars in setting endp.
+
+2019-05-14 Nick Clifton <nickc@redhat.com>
+
+ PR 24538
+ * config/tc-i386-intel.c (i386_intel_simplify_register): Reject
+ illegal register numbers.
+
+2019-05-10 Nick Clifton <nickc@redhat.com>
+
+ PR 24538
+ * macro.c (get_any_string): Increase size of buffer used to hold
+ decimal value of expression result.
+ * dw2gencfi.c (get_debugseg_name): Handle an empty name.
+ * dwarf2dbg.c (get_filenum): Catch integer wraparound when
+ extending allocate file array.
+ (dwarf2_directive_filename): Add extra checks of the computed file
+ number.
+ * config/tc-arm.c (arm_tc_equal_in_insn): Insert copy of name into
+ warning hash table.
+ (s_arm_eabi_attribute): Check for obj_elf_vendor_attribute
+ returning -1.
+ * config/tc-i386.c (i386_output_nops): Catch an attempt to
+ generate nops of negative lengths.
+ * as.h (MAX_LITTLENUMS): Move definition to here from...
+ * config/atof-ieee.c: ...here.
+ * config/tc-aarch64.c: ...here.
+ * config/tc-arc.c: ...here.
+ * config/tc-arm.c: ...here.
+ * config/tc-epiphany.c: ...here.
+ * config/tc-i386.c: ...here.
+ * config/tc-ia64.c: ...here. (And correct the value).
+ * config/tc-m32c.c: ...here.
+ * config/tc-m32r.c: ...here.
+ * config/tc-metag.c: ...here.
+ * config/tc-microblaze.c: ...here.
+ * config/tc-nds32.c: ...here.
+ * config/tc-or1k.c: ...here.
+ * config/tc-score.c: ...here.
+ * config/tc-score7.c: ...here.
+ * config/tc-tic4x.c: ...here.
+ * config/tc-tilegx.c: ...here.
+ * config/tc-tilepro.c: ...here.
+ * config/tc-visium.c: ...here.
+ * config/tc-sh.c (md_assemble): Add check for an instruction with
+ no opcodes.
+ * config/tc-mips.c (mips_lookup_insn): Add check for very short
+ instruction name.
+ * config/tc-tic54x.c: Use unsigned chars to access is_end_of_line
+ array.
+ (tic54x_start_line_hook): Check for an empty line.
+ (next_line_shows_parallel): Do not walk off the end of the string.
+ (tic54x_macro_start): Check for too much macro nesting.
+ (tic54x_start_label): Add label_start parameter. Use this
+ parameter to check the first character of the label.
+
+ * config/tc-tic54x.h (TC_START_LABEL_WITHOUT_COLON): Pass
+ line_start variable to tic54x_start_label.
+
+2019-05-10 Faraz Shahbazker <fshahbazker@wavecomp.com>
+
+ * config/tc-mips.c (macro) <M_ADD_I, M_SUB_I, M_DADD_I, M_DSUB_I>:
+ Add expansions for MIPS r6.
+ * testsuite/gas/mips/add.s: Enable tests for R6.
+ * testsuite/gas/mips/daddi.s: Annotate to test DADD for R6.
+ * testsuite/gas/mips/mipsr6@add.d: Likewise.
+ * gas/testsuite/gas/mips/mipsr6@dadd.d: New test.
+ * gas/testsuite/gas/mips/mips.exp: Run the new test.
+
+2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
+
+ * testsuite/gas/aarch64/sve2.d: Remove file format restriction.
+
+2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
+
+ * testsuite/gas/aarch64/illegal-sve2-aes.d: New test.
+ * testsuite/gas/aarch64/illegal-sve2-bitperm.d: New test.
+ * testsuite/gas/aarch64/illegal-sve2-sha3.d: Test new instructions.
+ * testsuite/gas/aarch64/illegal-sve2-sm4.d: Test new instructions.
+ * testsuite/gas/aarch64/illegal-sve2-sve1ext.d: Test new instructions.
+ * testsuite/gas/aarch64/illegal-sve2-sve1ext.l: Test new instructions.
+ * testsuite/gas/aarch64/illegal-sve2.d: Test new instructions.
+ * testsuite/gas/aarch64/illegal-sve2.l: Test new instructions.
+ * testsuite/gas/aarch64/illegal-sve2.s: Test new instructions.
+ * testsuite/gas/aarch64/sve1-extended-sve2.s: New test.
+ * testsuite/gas/aarch64/sve2.d: Test new instructions.
+ * testsuite/gas/aarch64/sve2.s: Test new instructions.
+
+2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
+
+ * config/tc-aarch64.c (parse_operands): Handle new SVE_SHLIMM_UNPRED_22
+ operand.
+
+2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
+
+ * config/tc-aarch64.c (parse_operands): Handle new SVE_Zm4_11_INDEX
+ operand.
+
+2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
+
+ * config/tc-aarch64.c (parse_operands): Handle new SVE_SHRIMM_UNPRED_22
+ operand.
+
+2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
+
+ * config/tc-aarch64.c (REG_ZR): Macro specifying zero register.
+ (parse_address_main): Account for new addressing mode [Zn.S, Xm].
+ (parse_operands): Handle new SVE_ADDR_ZX operand.
+
+2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
+
+ * config/tc-aarch64.c (parse_operands): Handle new SVE_Zm3_11_INDEX
+ operand.
+
+2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
+
+ * config/tc-aarch64.c (parse_operands): Handle new SVE_IMM_ROT3 operand.
+
+2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
+
+ * config/tc-aarch64.c: Add command line architecture feature flags
+ "sve2", "sve2-sm4", "sve2-aes", "sve2-sha3", "bitperm".
+ * doc/c-aarch64.texi: Document new architecture feature flags.
+
+2019-05-08 Alan Modra <amodra@gmail.com>
+
+ * testsuite/gas/elf/dwarf2-1.s,
+ * testsuite/gas/elf/dwarf2-2.s,
+ * testsuite/gas/elf/dwarf2-5.s,
+ * testsuite/gas/elf/dwarf2-7.s,
+ * testsuite/gas/elf/dwarf2-8.s,
+ * testsuite/gas/elf/dwarf2-9.s,
+ * testsuite/gas/elf/dwarf2-10.s,
+ * testsuite/gas/elf/dwarf2-11.s,
+ * testsuite/gas/elf/dwarf2-12.s,
+ * testsuite/gas/elf/dwarf2-13.s,
+ * testsuite/gas/elf/dwarf2-14.s,
+ * testsuite/gas/elf/dwarf2-15.s,
+ * testsuite/gas/elf/dwarf2-16.s,
+ * testsuite/gas/elf/dwarf2-17.s,
+ * testsuite/gas/elf/dwarf2-18.s,
+ * testsuite/gas/elf/dwarf2-19.s: Double size of align and simulated
+ instructions.
+ * testsuite/gas/elf/dwarf2-1.d,
+ * testsuite/gas/elf/dwarf2-2.d,
+ * testsuite/gas/elf/dwarf2-5.d,
+ * testsuite/gas/elf/dwarf2-7.d,
+ * testsuite/gas/elf/dwarf2-8.d,
+ * testsuite/gas/elf/dwarf2-9.d,
+ * testsuite/gas/elf/dwarf2-10.d,
+ * testsuite/gas/elf/dwarf2-11.d,
+ * testsuite/gas/elf/dwarf2-12.d,
+ * testsuite/gas/elf/dwarf2-13.d,
+ * testsuite/gas/elf/dwarf2-14.d,
+ * testsuite/gas/elf/dwarf2-15.d,
+ * testsuite/gas/elf/dwarf2-16.d,
+ * testsuite/gas/elf/dwarf2-17.d,
+ * testsuite/gas/elf/dwarf2-18.d,
+ * testsuite/gas/elf/dwarf2-19.d: Use xfail rather than notarget.
+ Remove avr, pru, tile, xtensa from xfails. Update expected output.
+ * testsuite/gas/elf/elf.exp: Sort targets.
+ (dump_opts): Pass {as -mno-relax} for riscv, {as -mno-link-relax}
+ for avr and pru, and {as --no-link-relax} for xtensa to dwarf tests.
+ * testsuite/gas/elf/section2.e-miwmmxt: Delete unused file.
+
+2019-05-08 Alan Modra <amodra@gmail.com>
+
+ * config/tc-xtensa.c (opt_linkrelax): New variable.
+ (md_parse_option): Set it here.
+ (md_begin): Copy opt_linkrelax to linkrelax.
+
+2019-05-07 Alexandre Oliva <aoliva@redhat.com>
+
+ * testsuite/gas/elf/dwarf2-18.d: Xfail mep-*.
+ * testsuite/gas/elf/dwarf2-19.d: Likewise.
+
+2019-05-07 Alan Modra <amodra@gmail.com>
+
+ * symbols.c (use_complex_relocs_for): Formatting. Factor out
+ X_add_symbol tests.
+
+2019-05-06 Andrew Bennett <andrew.bennett@imgtec.com>
+ Faraz Shahbazker <fshahbazker@wavecomp.com>
+
+ * config/tc-mips.c (mips_set_ase): Handle ASE_EVA_R6.
+ (macro) <M_LLWPE_AB, M_SCWPE_AB>: New cases.
+ (mips_after_parse_args): Translate EVA to EVA_R6.
+ * testsuite/gas/mips/ase-errors-1.s: Add new instructions.
+ * testsuite/gas/mips/eva.s: Likewise.
+ * testsuite/gas/mips/ase-errors-1.l: Check errors for
+ new instructions.
+ * testsuite/gas/mips/mipsr6@eva.d: Check new test cases.
+
+2019-05-06 Alan Modra <amodra@gmail.com>
+
+ * symbols.c (symbol_relc_make_sym): Do not access sym->sy_value
+ directly.
+
+2019-05-06 Alan Modra <amodra@gmail.com>
+
+ * config/tc-ppc.c (ppc_fix_adjustable): Exclude all GOT and PLT
+ relocs, and VLE sdarel relocs.
+ * testsuite/gas/ppc/power4.d: Adjust.
+
+2019-05-05 Alexandre Oliva <aoliva@redhat.com>
+
+ * dwarf2dbg.c (set_or_check_view): Skip heads when assigning
+ views of prior locs.
+ (dwarf2_gen_line_info_1): Skip heads.
+ (size_inc_line_addr, emit_inc_line_addr): Drop
+ DW_LNS_advance_pc for zero addr delta.
+ (dwarf2_finish): Assign views for heads of segments.
+ * testsuite/gas/elf/dwarf2-19.d: New.
+ * testsuite/gas/elf/dwarf2-19.s: New.
+ * testsuite/gas/elf/elf.exp: Test it.
+
+2019-05-04 Alan Modra <amodra@gmail.com>
+
+ * config/tc-m32c.c (insn_size): Delete static var.
+ (md_begin): Don't set it.
+ (m32c_md_end): Delete.
+ (md_assemble): Add insn_size auto var.
+ * config/tc-m32c.h (md_end): Don't define.
+ (m32c_md_end): Delete.
+ (NOP_OPCODE, HANDLE_ALIGN, MAX_MEM_FOR_RS_ALIGN_CODE): Define.
+ * testsuite/gas/all/align.d: Remove m32c from notarget list.
+ * testsuite/gas/all/incbin.d: Likewise.
+ * testsuite/gas/elf/dwarf2-11.d: Likewise.
+ * testsuite/gas/macros/semi.d: Likewise.
+ * testsuite/gas/all/gas.exp (do_comment): Similarly.
+
+2019-05-02 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR gas/24485
+ * config/tc-i386.c (process_suffix): Issue a warning to IRET
+ without a suffix for .code16gcc.
+ * testsuite/gas/i386/jump16.s: Add tests for iretX.
+ * testsuite/gas/i386/jump16.d: Updated.
+ * testsuite/gas/i386/jump16.e: New file.
+
+2019-05-01 Sudakshina Das <sudi.das@arm.com>
+
+ * config/tc-aarch64.c (parse_operands): Add case for
+ AARCH64_OPND_TME_UIMM16.
+ (aarch64_features): Add "tme".
+ * doc/c-aarch64.texi: Document the same.
+ * testsuite/gas/aarch64/tme-invalid.d: New test.
+ * testsuite/gas/aarch64/tme-invalid.l: New test.
+ * testsuite/gas/aarch64/tme-invalid.s: New test.
+ * testsuite/gas/aarch64/tme.d: New test.
+ * testsuite/gas/aarch64/tme.s: New test.
+
+2019-04-29 John Darrington <john@darrington.wattle.id.au>
+
+ * testsuite/gas/s12z/truncated.d: New file.
+ * testsuite/gas/s12z/truncated.s: New file.
+ * testsuite/gas/s12z/s12z.exp: Add new test.
+
+2019-04-26 Andrew Bennett <andrew.bennett@imgtec.com>
+ Faraz Shahbazker <fshahbazker@wavecomp.com>
+
+ * config/tc-mips.c (macro) <M_LLWP_AB, M_LLDP_AB, M_SCWP_AB,
+ M_SCDP_AB>: New cases and expansions for paired instructions.
+ * testsuite/gas/mips/llpscp-32.s: New test source.
+ * testsuite/gas/mips/llpscp-64.s: Likewise.
+ * testsuite/gas/mips/llpscp-32.d: New test.
+ * testsuite/gas/mips/llpscp-64.d: Likewise.
+ * testsuite/gas/mips/mips.exp: Run the new tests.
+ * testsuite/gas/mips/r6.s: Add new instructions to test source.
+ * testsuite/gas/mips/r6-64.s: Likewise.
+ * testsuite/gas/mips/r6-64-n32.d: Check new instructions.
+ * testsuite/gas/mips/r6-64-n64.d: Likewise.
+ * testsuite/gas/mips/r6-n32.d: Likewise.
+ * testsuite/gas/mips/r6-n64.d: Likwwise.
+ * testsuite/gas/mips/r6.d: Likewise.
+
+2019-04-26 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR gas/24485
+ * config/tc-i386.c (process_suffix): Don't add DATA_PREFIX_OPCODE
+ to IRET for .code16gcc.
+ * testsuite/gas/i386/jump16.s: Add IRET tests.
+ * testsuite/gas/i386/jump16.d: Updated.
+
+2019-04-25 Alexandre Oliva <aoliva@redhat.com>
+ Alan Modra <amodra@gmail.com>
+
+ PR gas/24444
+ * frags.c (frag_gtoffset_p): New.
+ * frags.h (frag_gtoffset_p): Declare it.
+ * expr.c (resolve_expression): Use it.
+
+2019-04-24 Alan Modra <amodra@gmail.com>
+
+ PR 24444
+ * symbols.c (resolve_symbol_value): When handling symbols
+ marked as sy_flags.resolved, return correct value for the
+ case of expression symbols left as an O_symbol expression.
+ Merge O_symbol code handling undefined and common symbols with
+ code handling special cases of expression symbols. Use
+ seg_left to test for undefined and common symbols. Don't
+ leave an O_symbol expression when X_add_symbol resolves to
+ the absolute_section. Init final_val later.
+ * testsuite/gas/mmix/basep-7.d: Adjust expected output.
+
+2019-04-24 John Darrington <john@darrington.wattle.id.au>
+
+ * testsuite/gas/s12z/bit-manip-invalid.s: Extend test for BSET
+ and BCLR instructions with an invalid mode.
+ * testsuite/gas/s12z/bit-manip-invalid.d: ditto.
+
+2019-04-19 Nick Clifton <nickc@redhat.com>
+
+ PR 24464
+ * config/tc-rx.h (md_relax_frag): Pass the max_iterations variable
+ to the relaxation function.
+ * config/tc-rx.c (rx_relax_frag): Add new parameter - the maximum
+ number of iterations. Make sure that our internal iteration limit
+ does not exceed this external iteration limit.
+
+2019-04-18 Matthew Fortune <matthew.fortune@mips.com>
+
+ * config/tc-mips.c (match_non_zero_reg_operand): Update
+ warning message.
+ * testsuite/gas/mips/r6-branch-constraints.l: Likewise.
+
+2019-04-18 Jozef Lawrynowicz <jozef.l@mittosystems.com>
+
+ * config/tc-msp430.c (msp430_make_init_symbols): Define
+ __crt0_run_{preinit,init,fini}_array symbols if
+ .{preinit,init,fini}_array sections exist.
+ * testsuite/gas/msp430/fini-array.d: New test.
+ * testsuite/gas/msp430/init-array.d: New test.
+ * testsuite/gas/msp430/preinit-array.d: New test.
+ * testsuite/gas/msp430/fini-array.s: New test source.
+ * testsuite/gas/msp430/init-array.s: New test source.
+ * testsuite/gas/msp430/preinit-array.s: New test source.
+ * testsuite/gas/msp430/msp430.exp: Add new tests to driver.
+
+2019-04-17 Jozef Lawrynowicz <jozef.l@mittosystems.com>
+
+ * config/tc-msp430.c (msp430_make_init_symbols): Define __crt0_init_bss
+ symbol when .lower.bss or .either.bss sections exist.
+ Define __crt0_movedata when .lower.data or .either.data sections exist.
+ * testsuite/gas/msp430/either-data-bss-sym.d: New test.
+ * testsuite/gas/msp430/low-data-bss-sym.d: New test.
+ * testsuite/gas/msp430/either-data-bss-sym.s: New test source.
+ * testsuite/gas/msp430/low-data-bss-sym.s: New test source.
+ * testsuite/gas/msp430/msp430.exp: Run new tests.
+ Enable large code model when running -mdata-region={upper,either}
+ tests.
+
+2019-04-17 Jozef Lawrynowicz <jozef.l@mittosystems.com>
+
+ * config/tc-msp430.c (options): New OPTION_UNKNOWN_INTR_NOPS,
+ OPTION_NO_UNKNOWN_INTR_NOPS and do_unknown_interrupt_nops.
+ (md_parse_option): Handle OPTION_UNKNOWN_INTR_NOPS and
+ OPTION_NO_UNKNOWN_INTR_NOPS by setting do_unknown_interrupt_nops
+ accordingly.
+ (md_show_usage): Likewise.
+ (md_shortopts): Add "mu" for OPTION_UNKNOWN_INTR_NOPS and
+ "mU" for OPTION_NO_UNKNOWN_INTR_NOPS.
+ (md_longopts): Likewise.
+ (warn_eint_nop): Update comment.
+ (warn_unsure_interrupt): Don't warn if prev_insn_is_nop or
+ prev_insn_is_dint or we are assembling for 430 ISA.
+ (msp430_operands): Only call warn_unsure_interrupt if
+ do_unknown_interrupt_nops == TRUE.
+ * testsuite/gas/msp430/nop-unknown-intr.s: New test source file.
+ * testsuite/gas/msp430/nop-unknown-intr-430.d: New test.
+ * testsuite/gas/msp430/nop-unknown-intr-430x.d: New test.
+ * testsuite/gas/msp430/nop-unknown-intr-430x-ignore.d: New test.
+ * testsuite/gas/msp430/nop-unknown-intr-430.l: Warning output for new
+ test.
+ * testsuite/gas/msp430/nop-unknown-intr-430x.l: Likewise.
+ * testsuite/gas/msp430/msp430.exp: Add new tests to driver.
+
+2019-04-16 Alan Modra <amodra@gmail.com>
+
+ * testsuite/gas/all/weakref1.d: xfail nds32.
+
+2019-04-16 Alan Modra <amodra@gmail.com>
+
+ * testsuite/gas/all/gas.exp: Remove ns32k xfails.
+ * testsuite/gas/all/weakref1u.d: Don't run for ns32k-*-*.
+
+2019-04-16 Alan Modra <amodra@gmail.com>
+
+ * write.h: Don't include bit_fix.h.
+ (struct fix): Rearrange some fields. Delete fx_im_disp and
+ fx_bit_fixP. Use bitfields for fx_size and fx_pcrel_adjust.
+ * write.c (fix_new_internal): Don't init fx_im_disp and fx_bit_fixP.
+ (fixup_segment): Don't exclude overflow checks on fx_bit_fixP.
+ (print_fixup): Don't print im_disp.
+ * config/tc-cris.c (md_apply_fix): Remove tests of fx_bit_fixP
+ and fx_im_disp.
+ * config/tc-dlx.c (md_apply_fix): Remove wrong debug code. Set
+ fx_no_overflow when fx_bit_fixP.
+ * config/tc-dlx.h: Include bit_fix.h.
+ (TC_FIX_TYPE, tc_fix_data, TC_INIT_FIX_DATA): Define.
+ * config/tc-ns32k.c (fix_new_ns32k, fix_new_ns32k_exp): Set
+ fx_no_overflow when bit_fixP.
+ * config/tc-ns32k.h (TC_FIX_TYPE): Add fx_bit_fixP and fx_im_disp.
+ (fix_im_disp, fix_bit_fixP): Adjust to suit.
+ (TC_INIT_FIX_DATA, TC_FIX_DATA_PRINT): Likewise.
+
+2019-04-16 Alan Modra <amodra@gmail.com>
+
+ * write.h (struct fix <fx_where>): Make unsigned.
+ (fix_new, fix_at_start, fix_new_exp): Adjust prototypes.
+ * write.c (fix_new, fix_new_exp, fix_at_start): Make "where" and
+ "size" parameters unsigned long.
+ (fix_new_internal): Likewise. Adjust error format string to suit.
+ * config/tc-mips.c (md_convert_frag): Remove cast of fx_where.
+ * config/tc-sparc.c (md_apply_fix): Likewise.
+ * config/tc-score.c (s3_convert_frag): Adjust for unsigned fx_where.
+ * config/tc-score7.c (s7_convert_frag): Likewise.
+
+2019-04-16 Alan Modra <amodra@gmail.com>
+
+ * frags.h (struct frag <fr_fix>): Use unsigned type.
+ * frags.c (frag_new): Assert that current size exceeds
+ old_frags_var_max_size.
+ * ehopt.c (get_cie_info): Adjust for unsigned fr_fix.
+ * listing.c (calc_hex): Likewise.
+ * write.c (cvt_frag_to_fill, write_relocs): Likewise.
+ * config/tc-arc.c (md_convert_frag): Likewise.
+ * config/tc-avr.c (avr_patch_gccisr_frag): Likewise.
+ * config/tc-mips.c (md_convert_frag): Likewise.
+ * config/tc-rl78.c (md_convert_frag): Likewise.
+ * config/tc-rx.c (md_convert_frag): Likewise.
+ * config/tc-sparc.c (md_apply_fix): Likewise.
+ * config/tc-xtensa.c (next_instrs_are_b_retw): Likewise.
+ (unrelaxed_frag_min_insn_count, unrelaxed_frag_has_b_j): Likewise.
+
+2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
+
+ * config/tc-arm.c (parse_sys_vldr_vstr): New function.
+ (OP_VLDR): New enum operand_parse_code enumerator.
+ (parse_operands): Add logic for OP_VLDR.
+ (do_t_vldr_vstr_sysreg): New function.
+ (do_vldr_vstr): Likewise.
+ (insns): Guard VLDR and VSTR by arm_ext_v4t for Thumb mode.
+ (md_apply_fix): Add bound check for VLDR and VSTR co-processor offset.
+ Add masking logic for BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM relocation.
+ * testsuite/gas/arm/archv8m_1m-cmse-main-bad.s: Add examples of bad
+ uses of VLDR and VSTR.
+ * testsuite/gas/arm/archv8m_1m-cmse-main-bad.l: Add error messages for
+ above bad uses.
+ * testsuite/gas/arm/archv8m_1m-cmse-main.s: Add examples of VLDR and
+ VSTR valid uses.
+ * testsuite/gas/arm/archv8m_1m-cmse-main.d: Add disassembly for the
+ above examples.
+
+2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
+
+ * config/tc-arm.c (arm_typed_reg_parse): Fix typo in comment.
+ (enum reg_list_els): New REGLIST_VFP_S_VPR and REGLIST_VFP_D_VPR
+ enumerators.
+ (parse_vfp_reg_list): Add new partial_match parameter. Set
+ *partial_match to TRUE if at least one element in the register list has
+ matched. Add support for REGLIST_VFP_S_VPR and REGLIST_VFP_D_VPR
+ register lists which expect VPR as last element in the list.
+ (s_arm_unwind_save_vfp_armv6): Adapt call to parse_vfp_reg_list to new
+ prototype.
+ (s_arm_unwind_save_vfp): Likewise.
+ (enum operand_parse_code): New OP_VRSDVLST enumerator.
+ (parse_operands): Adapt call to parse_vfp_reg_list to new prototype.
+ Handle new OP_VRSDVLST case.
+ (do_t_vscclrm): New function.
+ (insns): New entry for VSCCLRM instruction.
+ * testsuite/gas/arm/archv8m_1m-cmse-main-bad.s: Add invalid VSCCLRM
+ instructions.
+ * testsuite/gas/arm/archv8m_1m-cmse-main-bad.l: Add error expectations
+ for above instructions.
+ * testsuite/gas/arm/archv8m_1m-cmse-main.s: Add tests for VSCCLRM
+ instruction.
+ * testsuite/gas/arm/archv8m_1m-cmse-main.d: Add expected disassembly
+ for above instructions.
+
+2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
+
+ * config/tc-arm.c (enum reg_list_els): Define earlier and add
+ REGLIST_RN and REGLIST_CLRM enumerators.
+ (parse_reg_list): Add etype parameter to distinguish between regular
+ core register list and CLRM register list. Add logic to
+ recognize CLRM register list.
+ (parse_vfp_reg_list): Assert type is not for core register list.
+ (s_arm_unwind_save_core): Update call to parse_reg_list to new
+ prototype.
+ (enum operand_parse_code): Declare OP_CLRMLST enumerator.
+ (parse_operands): Update call to parse_reg_list to new prototype. Add
+ logic for OP_CLRMLST.
+ (encode_thumb2_ldmstm): Rename into ...
+ (encode_thumb2_multi): This. Add do_io parameter. Add logic to
+ encode CLRM and guard LDM/STM only code by do_io.
+ (do_t_ldmstm): Adapt to use encode_thumb2_multi.
+ (do_t_push_pop): Likewise.
+ (do_t_clrm): New function.
+ (insns): Define CLRM.
+ * testsuite/gas/arm/archv8m_1m-cmse-main-bad.d: New file.
+ * testsuite/gas/arm/archv8m_1m-cmse-main-bad.l: Likewise.
+ * testsuite/gas/arm/archv8m_1m-cmse-main-bad.s: Likewise.
+ * testsuite/gas/arm/archv8m_1m-cmse-main.d: Likewise.
+ * testsuite/gas/arm/archv8m_1m-cmse-main.s: Likewise.
+
+2019-04-15 Sudakshina Das <sudi.das@arm.com>
+ Andre Vieira <andre.simoesdiasvieira@arm.com>
+
+ * config/tc-arm.c (operand_parse_code): Add OP_LR and OP_oLR
+ for the LR operand and optional LR operand.
+ (parse_operands): Add switch cases for OP_LR and OP_oLR for
+ both type checking and value checking.
+ (encode_thumb32_addr_mode): New entries for DLS, WLS and LE.
+ (v8_1_loop_reloc): New helper function for handling labels
+ for the low overhead loop instructions.
+ (do_t_loloop): New function to encode DLS, WLS and LE.
+ (insns): New entries for WLS, DLS and LE.
+ (md_pcrel_from_section): New switch case
+ for BFD_RELOC_ARM_THUMB_LOOP12.
+ (md_appdy_fix): Likewise.
+ (tc_gen_reloc): Likewise.
+ * testsuite/gas/arm/armv8_1-m-tloop.s: New.
+ * testsuite/gas/arm/armv8_1-m-tloop.d: New.
+ * testsuite/gas/arm/armv8_1-m-tloop-bad.s: New.
+ * testsuite/gas/arm/armv8_1-m-tloop-bad.d: New.
+ * testsuite/gas/arm/armv8_1-m-tloop-bad.l: New.
+
+2019-04-15 Sudakshina Das <sudi.das@arm.com>
+ Andre Vieira <andre.simoesdiasvieira@arm.com>
+
+ * config/tc-arm.c (T16_32_TAB): New entriy for bfcsel.
+ (do_t_v8_1_branch): New switch case for bfcsel.
+ (toU): Define.
+ (insns): New instruction for bfcsel.
+ (md_pcrel_from_section): New switch case
+ for BFD_RELOC_THUMB_PCREL_BFCSEL.
+ (md_appdy_fix): Likewise
+ (tc_gen_reloc): Likewise.
+ * testsuite/gas/arm/armv8_1-m-bfcsel.d: New.
+ * testsuite/gas/arm/armv8_1-m-bfcsel.s: New.
+
+2019-04-15 Sudakshina Das <sudi.das@arm.com>
+
+ * config/tc-arm.c (md_pcrel_from_section): New switch case for
+ BFD_RELOC_ARM_THUMB_BF13.
+ (md_appdy_fix): Likewise.
+ (tc_gen_reloc): Likewise.
+
+2019-04-15 Sudakshina Das <sudi.das@arm.com>
+ Andre Vieira <andre.simoesdiasvieira@arm.com>
+
+ * config/tc-arm.c (T16_32_TAB): New entrie for bfl.
+ (do_t_v8_1_branch): New switch case for bfl.
+ (insns): New instruction for bfl.
+ * testsuite/gas/arm/armv8_1-m-bfl.d: New.
+ * testsuite/gas/arm/armv8_1-m-bfl.s: New.
+ * testsuite/gas/arm/armv8_1-m-bfl-bad.s: New.
+ * testsuite/gas/arm/armv8_1-m-bfl-bad.d: New.
+ * testsuite/gas/arm/armv8_1-m-bfl-bad.l: New.
+ * testsuite/gas/arm/armv8_1-m-bfl-rel.d: New.
+ * testsuite/gas/arm/armv8_1-m-bfl-rel.s: New.
+
+2019-04-15 Sudakshina Das <sudi.das@arm.com>
+
+ * config/tc-arm.c (md_pcrel_from_section): New switch case for
+ BFD_RELOC_ARM_THUMB_BF19.
+ (md_appdy_fix): Likewise.
+ (tc_gen_reloc): Likewise.
+
+2019-04-15 Sudakshina Das <sudi.das@arm.com>
+
+ * config/tc-arm.c (T16_32_TAB): New entries for bfx and bflx.
+ (do_t_v8_1_branch): New switch cases for bfx and bflx.
+ (insns): New instruction for bfx and bflx.
+ * testsuite/gas/arm/armv8_1-m-bf-exchange.d: New.
+ * testsuite/gas/arm/armv8_1-m-bf-exchange.s: New.
+ * testsuite/gas/arm/armv8_1-m-bf-exchange-bad.s: New
+ * testsuite/gas/arm/armv8_1-m-bf-exchange-bad.l: New
+ * testsuite/gas/arm/armv8_1-m-bf-exchange-bad.d: New
+
+2019-04-15 Sudakshina Das <sudi.das@arm.com>
+ Andre Vieira <andre.simoesdiasvieira@arm.com>
+
+ * config/tc-arm.c (T16_32_TAB): New entries for bf.
+ (do_t_branch_future): New.
+ (insns): New instruction for bf.
+ * testsuite/gas/arm/armv8_1-m-bf.d: New.
+ * testsuite/gas/arm/armv8_1-m-bf.s: New.
+ * testsuite/gas/arm/armv8_1-m-bf-bad.s: New.
+ * testsuite/gas/arm/armv8_1-m-bf-bad.l: New.
+ * testsuite/gas/arm/armv8_1-m-bf-bad.d: New.
+ * testsuite/gas/arm/armv8_1-m-bf-rel.d: New.
+ * testsuite/gas/arm/armv8_1-m-bf-rel.s: New.
+
+2019-04-15 Sudakshina Das <sudi.das@arm.com>
+
+ * config/tc-arm.c (md_pcrel_from_section): New switch case for
+ BFD_RELOC_ARM_THUMB_BF17.
+ (md_appdy_fix): Likewise.
+ (tc_gen_reloc): Likewise.
+
+2019-04-15 Sudakshina Das <sudi.das@arm.com>
+
+ * config/tc-arm.c (ARM_IT_MAX_RELOCS): New macro.
+ (arm_it): Member reloc renamed relocs and updated to an array.
+ Rest: Replace all occurrences of reloc to relocs[0].
+
+2019-04-15 Sudakshina Das <sudi.das@arm.com>
+
+ * config/tc-arm.c (md_pcrel_from_section): New switch case
+ for BFD_RELOC_THUMB_PCREL_BRANCH5.
+ (v8_1_branch_value_check): New function to check branch
+ offsets.
+ (md_appdy_fix): New switch case for
+ BFD_RELOC_THUMB_PCREL_BRANCH5.
+ (tc_gen_reloc): Likewise.
+
+2019-04-15 Andre Vieira <andre.simoesdiasvieira@arm.com>
+
+ * config/tc-arm.c (do_neon_movhf): Remove fp-armv8 check.
+ (armv8_1m_main_ext_table): New extension table.
+ (arm_archs): Use the new extension table.
+ * doc/c-arm.texi: Add missing arch and document new extensions.
+ * testsuite/gas/arm/armv8.1-m.main-fp.d: New.
+ * testsuite/gas/arm/armv8.1-m.main-fp-dp.d: New.
+ * testsuite/gas/arm/armv8.1-m.main-hp.d: New.
+
+2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
+
+ * config/tc-arm.c (cpu_arch_ver): Add entry for Armv8.1-M Mainline
+ Tag_CPU_arch build attribute value. Reindent.
+ (get_aeabi_cpu_arch_from_fset): Update assert.
+ (aeabi_set_public_attributes): Update assert for Tag_DIV_use logic.
+ * testsuite/gas/arm/attr-march-armv8_1-m.main.d: New test.
+
+2019-04-09 Matthew Fortune <matthew.fortune@mips.com>
+
+ * config/tc-mips.c (mips_cpu_info_table): Add i6500. Update
+ default ASEs for i6400.
+ * doc/c-mips.texi (-march): Document i6500.
+ * testsuite/gas/mips/elf_mach_i6400.d: New test.
+ * testsuite/gas/mips/elf_mach_i6500.d: New test.
+ * testsuite/gas/mips/mips.exp: Run the new tests.
+
+2019-04-09 Matthew Fortune <matthew.fortune@mips.com>
+
+ * config/tc-mips.c (mips_set_options) <init_ase>: New field.
+ (file_mips_opts, mips_opts) <init_ase>: Initialize new field.
+ (file_mips_check_options): Propagate initial ASE settings.
+ (mips_after_parse_args, parse_code_option): Track the initial
+ ASE settings for a CPU.
+ (s_mipsset): Restore the initial ASE settings when reverting
+ to the default arch.
+ * testsuite/gas/mips/elf_mach_p6600.d: New test.
+ * testsuite/gas/mips/mips.exp: Run the new test.
+
+2019-04-12 John Darrington <john@darrington.wattle.id.au>
+
+ config/tc-s12z.h: Remove definition of macro TC_M68K
+
+2019-04-01 John Darrington <john@darrington.wattle.id.au>
+
+ config/tc-s12z.c: Use bfd_boolean where appropriate.
+
+2019-04-11 Max Filippov <jcmvbkbc@gmail.com>
+
+ * testsuite/gas/xtensa/loop-relax-2.d: New test definition.
+ * testsuite/gas/xtensa/loop-relax.d: New test definition.
+ * testsuite/gas/xtensa/loop-relax.s: New test source.
+ * testsuite/gas/xtensa/text-section-literals-1a.d: New test
+ definition.
+ * testsuite/gas/xtensa/text-section-literals-2.d: New test
+ definition.
+ * testsuite/gas/xtensa/text-section-literals-2.s: New test
+ source.
+ * testsuite/gas/xtensa/text-section-literals-2a.d: New test
+ definition.
+ * testsuite/gas/xtensa/text-section-literals-3.d: New test
+ definition.
+ * testsuite/gas/xtensa/text-section-literals-3.s: New test
+ source.
+ * testsuite/gas/xtensa/text-section-literals-4.d: New test
+ definition.
+ * testsuite/gas/xtensa/text-section-literals-4.s: New test
+ source.
+ * testsuite/gas/xtensa/text-section-literals-4a.d: New test
+ definition.
+
+2019-04-11 Max Filippov <jcmvbkbc@gmail.com>
+
+ * testsuite/gas/xtensa/all.exp: Remove all expect-based
+ tests and all explicit run_dump_test / run_list_test
+ invocations. Add run_dump_tests for all .d files in the
+ test subdirectory.
+ * testsuite/gas/xtensa/entry_align.d: New test definition.
+ * testsuite/gas/xtensa/entry_align.l: New test output.
+ * testsuite/gas/xtensa/entry_misalign.d: New test definition.
+ * testsuite/gas/xtensa/entry_misalign2.d: New test definition.
+ * testsuite/gas/xtensa/j_too_far.d: New test definition.
+ * testsuite/gas/xtensa/j_too_far.l: New test output.
+ * testsuite/gas/xtensa/loop_align.d: New test definition.
+ * testsuite/gas/xtensa/loop_misalign.d: New test definition.
+ * testsuite/gas/xtensa/trampoline-2.d: New test definition.
+ * testsuite/gas/xtensa/trampoline-2.l: Remove empty output.
+ * testsuite/gas/xtensa/xtensa-err.exp: Use positive logic.
+
+2019-04-11 Max Filippov <jcmvbkbc@gmail.com>
+
+ * config/tc-xtensa.c (xtensa_literal_pseudo): Drop code that has
+ no effect.
+ (get_literal_pool_location): Only search for the literal pool
+ when auto litpools is used, otherwise take one recorded in the
+ tc_segment_info_data.
+ (xtensa_assign_litpool_addresses): New function.
+ (xtensa_move_literals): Don't duplicate 'literal pool location
+ required...' error message. Call xtensa_assign_litpool_addresses.
+
+2019-04-11 Max Filippov <jcmvbkbc@gmail.com>
+
+ * config/tc-xtensa.c (xtensa_is_init_fini): Add declaration.
+ (xtensa_mark_literal_pool_location): Don't add fill frag to literal
+ section that records literal pool location.
+ (md_begin): Call xtensa_mark_literal_pool_location when text
+ section literals or auto litpools are used.
+ (xtensa_elf_section_change_hook): Call
+ xtensa_mark_literal_pool_location when text section literals or
+ auto litpools are used, there's no literal pool location defined
+ for the current section and it's not .init or .fini.
+ * testsuite/gas/xtensa/auto-litpools-first1.d: Fix up addresses.
+ * testsuite/gas/xtensa/auto-litpools-first2.d: Likewise.
+ * testsuite/gas/xtensa/auto-litpools.d: Likewise.
+
+2019-04-11 Sudakshina Das <sudi.das@arm.com>
+
+ * config/tc-aarch64.c (process_omitted_operand): Add case for
+ AARCH64_OPND_Rt_SP.
+ (parse_operands): Likewise.
+ * testsuite/gas/aarch64/armv8_5-a-memtag.d: Update tests.
+ * testsuite/gas/aarch64/armv8_5-a-memtag.s: Likewise.
+ * testsuite/gas/aarch64/illegal-memtag.l: Likewise.
+ * testsuite/gas/aarch64/illegal-memtag.s: Likewise.
+
+2019-04-11 Sudakshina Das <sudi.das@arm.com>
+
+ * testsuite/gas/aarch64/armv8_5-a-memtag.d: New tests for ldgm and stgm.
+ * testsuite/gas/aarch64/armv8_5-a-memtag.s: Likewise.
+ * testsuite/gas/aarch64/illegal-memtag.l: Likewise.
+ * testsuite/gas/aarch64/illegal-memtag.s: Likewise.
+
+2019-04-10 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
+
+ * config/tc-i386.c (need_plt32_p) [TE_SOLARIS]: Return FALSE.
+ * testsuite/gas/i386/solaris/solaris.exp: New driver.
+ * testsuite/gas/i386/solaris/reloc64.d,
+ testsuite/gas/i386/solaris/x86-64-jump.d,
+ testsuite/gas/i386/solaris/x86-64-mpx-branch-1.d,
+ testsuite/gas/i386/solaris/x86-64-mpx-branch-2.d,
+ testsuite/gas/i386/solaris/x86-64-nop-3.d,
+ testsuite/gas/i386/solaris/x86-64-nop-4.d,
+ testsuite/gas/i386/solaris/x86-64-nop-5.d,
+ testsuite/gas/i386/solaris/x86-64-relax-2.d,
+ testsuite/gas/i386/solaris/x86-64-relax-3.d: New tests.
+ * testsuite/gas/i386/reloc64.d,
+ testsuite/gas/i386/x86-64-jump.d,
+ testsuite/gas/i386/x86-64-mpx-branch-1.d,
+ testsuite/gas/i386/x86-64-mpx-branch-2.d,
+ testsuite/gas/i386/x86-64-nop-3.d,
+ testsuite/gas/i386/x86-64-nop-4.d,
+ testsuite/gas/i386/x86-64-nop-5.d,
+ testsuite/gas/i386/x86-64-relax-2.d,
+ testsuite/gas/i386/x86-64-relax-3.d: Skip on *-*-solaris*.
+
+2019-04-10 Alan Modra <amodra@gmail.com>
+
+ * config/te-cloudabi.h: New file.
+ * config/tc-aarch64.c (aarch64_after_parse_args): Use TE_CLOUDABI
+ rather than TARGET_OS to select cloudabi.
+ * config/tc-i386.h (ELF_TARGET_FORMAT64): Define for TE_CLOUDABI.
+ * configure.tgt (*-*-cloudabi*): Set em=cloudabi.
+
+2019-04-09 Robert Suchanek <robert.suchanek@mips.com>
+
+ * testsuite/gas/mips/mips.exp: Run hwr-names test.
+ * testsuite/gas/mips/hwr-names.s: Add test cases for RDHWR with
+ the SEL field.
+ * testsuite/gas/mips/mipsr6@hwr-names.d: New file.
+
+2019-04-08 H.J. Lu <hongjiu.lu@intel.com>
+
+ * config/tc-i386.c (output_insn): Support
+ GNU_PROPERTY_X86_ISA_1_AVX512_BF16.
+ * testsuite/gas/i386/property-2.s: Add AVX512_BF16 test.
+ * testsuite/gas/i386/property-2.d: Updated.
+ * testsuite/gas/i386/x86-64-property-2.d: Likewise.
+
+2019-04-08 H.J. Lu <hongjiu.lu@intel.com>
+
+ * configure.tgt: Remove i386-*-kaos* and i386-*-chaos targets.
+ * testsuite/gas/i386/i386.exp: Remove *-*-caos* and "*-*-kaos*
+ check.
+
+2019-04-05 H.J. Lu <hongjiu.lu@intel.com>
+
+ * testsuite/gas/i386/i386.exp: Run -mx86-used-note=yes tests.
+ * testsuite/gas/i386/property-2.d: New file.
+ * testsuite/gas/i386/property-2.s: Likewise.
+ * testsuite/gas/i386/x86-64-property-2.d: Likewise.
+
+2019-04-05 Xuepeng Guo <xuepeng.guo@intel.com>
+
+ * config/tc-i386.c (cpu_arch): Add .avx512_bf16.
+ (cpu_noarch): Add noavx512_bf16.
+ * doc/c-i386.texi: Document avx512_bf16.
+ * testsuite/gas/i386/avx512_bf16.d: New file.
+ * testsuite/gas/i386/avx512_bf16.s: Likewise.
+ * testsuite/gas/i386/avx512_bf16_vl-inval.l: Likewise.
+ * testsuite/gas/i386/avx512_bf16_vl-inval.s: Likewise.
+ * testsuite/gas/i386/avx512_bf16_vl.d: Likewise.
+ * testsuite/gas/i386/avx512_bf16_vl.s: Likewise.
+ * testsuite/gas/i386/x86-64-avx512_bf16.d: Likewise.
+ * testsuite/gas/i386/x86-64-avx512_bf16.s: Likewise.
+ * testsuite/gas/i386/x86-64-avx512_bf16_vl-inval.l: Likesie.
+ * testsuite/gas/i386/x86-64-avx512_bf16_vl-inval.s: Likewise.
+ * testsuite/gas/i386/x86-64-avx512_bf16_vl.d: Likewise.
+ * testsuite/gas/i386/x86-64-avx512_bf16_vl.s: Likewise.
+ * testsuite/gas/i386/i386.exp: Add BF16 related tests.
+
+2019-04-05 Alan Modra <amodra@gmail.com>
+
+ * testsuite/gas/ppc/bc.s,
+ * testsuite/gas/ppc/bcat.d,
+ * testsuite/gas/ppc/bcaterr.d,
+ * testsuite/gas/ppc/bcaterr.l,
+ * testsuite/gas/ppc/bcy.d,
+ * testsuite/gas/ppc/bcyerr.d,
+ * testsuite/gas/ppc/bcyerr.l: New tests.
+ * testsuite/gas/ppc/ppc.exp: Run them.
+
+2019-04-05 Alan Modra <amodra@gmail.com>
+
+ * testsuite/gas/ppc/476.d: Remove trailing spaces.
+ * testsuite/gas/ppc/a2.d: Likewise.
+ * testsuite/gas/ppc/booke.d: Likewise.
+ * testsuite/gas/ppc/booke_xcoff.d: Likewise.
+ * testsuite/gas/ppc/e500.d: Likewise.
+ * testsuite/gas/ppc/e500mc.d: Likewise.
+ * testsuite/gas/ppc/e6500.d: Likewise.
+ * testsuite/gas/ppc/htm.d: Likewise.
+ * testsuite/gas/ppc/power6.d: Likewise.
+ * testsuite/gas/ppc/power8.d: Likewise.
+ * testsuite/gas/ppc/power9.d: Likewise.
+ * testsuite/gas/ppc/vle.d: Likewise.
+
+2019-04-04 Peter Bergner <bergner@linux.ibm.com>
+
+ PR gas/24349
+ * testsuite/gas/ppc/power8.s: (bdnztar, bdnztarl, bdztar, bdztarl,
+ btar, btarl, bdnztar-, bdnztarl-, bdnztar+, bdnztarl+, bdztar-,
+ bdztarl-, bdztar+, bdztarl+, bgetar, bnltar, bgetarl, bnltarl,
+ bletar, bngtar, bletarl, bngtarl, bnetar, bnetarl, bnstar, bnutar,
+ bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-, bnltarl-, bletar-,
+ bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-, bnstar-, bnutar-,
+ bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+, bnltarl+, bletar+,
+ bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+, bnstar+, bnutar+,
+ bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl, beqtar,
+ beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
+ bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
+ buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
+ bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
+ bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
+ bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
+ bttarl+): Add tests of extended mnemonics.
+ * testsuite/gas/ppc/power8.d: Likewise. Update previous bctar tests
+ to expect new extended mnemonics.
+ * testsuite/gas/ppc/a2.s: <bc, bc-, bc+, bcl, bcl-, bcl+>: Update test
+ to not use illegal BO value. Use a more convenient BI value.
+ * testsuite/gas/ppc/a2.d: Update tests for new expect output.
+
+2019-04-03 Max Filippov <jcmvbkbc@gmail.com>
+
+ * config/tc-xtensa.c (convert_frag_immed): Drop
+ convert_frag_immed_finish_loop invocation.
+ (convert_frag_immed_finish_loop): Drop declaration and
+ definition.
+ * config/xtensa-relax.c (widen_spec_list): Replace loop
+ widening that uses addi/addmi with widening that uses l32r
+ and const16.
+
+2019-04-01 Andre Vieira <andre.simoesdiasvieira@arm.com>
+
+ * config/tc-arm.c (arm_ext_table): New struct type.
+ (arm_arch_option_table): Add new 'arm_ext_table' field.
+ (ARM_EXT,ARM_ADD,ARM_REMOVE, ALL_FP): New macros.
+ (armv5te_ext_table, armv7ve_ext_table, armv7a_ext_table,
+ armv7r_ext_table, armv7em_ext_table, armv8a_ext_table,
+ armv81a_ext_table, armv82a_ext_table, armv84a_ext_table,
+ armv85a_ext_table, armv8m_main_ext_table,
+ armv8r_ext_table): New architecture extension tables.
+ (ARM_ARCH_OPT): Add new default field.
+ (ARM_ARCH_OPT2): New macro.
+ (arm_archs): Extend some architectures with the new architecture
+ extension tables mentioned above.
+ (arm_extensions): Add DEPRECATED comment with instructions to
+ use new table.
+ (arm_parse_extension): Change to use new extension tables.
+ (arm_parse_cpu): Don't change existing behavior.
+ (arm_parse_arch): Change to use new extension tables.
+ * doc/c-arm.texi: Document new architecture extensions.
+ * testsuite/gas/arm/attr-mfpu-neon-fp16.d: Change test to use new
+ extension option rather than -mfpu and change expected behaviour to
+ sane outputs.
+ * testsuite/gas/arm/armv8-2-fp16-scalar-bad-ext.d: New.
+ * testsuite/gas/arm/armv8-2-fp16-scalar-ext.d: New.
+ * testsuite/gas/arm/armv8-2-fp16-scalar-thumb-ext.d: New.
+ * testsuite/gas/arm/armv8-2-fp16-simd-ext.d: New.
+ * testsuite/gas/arm/armv8-2-fp16-simd-thumb-ext.d: New.
+ * testsuite/gas/arm/armv8-2-fp16-simd-warning-ext.d: New.
+ * testsuite/gas/arm/armv8-2-fp16-simd-warning-thumb-ext.d: New.
+ * testsuite/gas/arm/armv8_2+rdma-ext.d: New.
+ * testsuite/gas/arm/armv8_2-a-fp16-thumb2-ext.d: New.
+ * testsuite/gas/arm/armv8_2-a-fp16_ext.d: New.
+ * testsuite/gas/arm/armv8_3-a-fp-bad-ext.d: New.
+ * testsuite/gas/arm/armv8_3-a-fp-ext.d: New.
+ * testsuite/gas/arm/armv8_3-a-fp16-ext.d: New.
+ * testsuite/gas/arm/armv8_3-a-simd-bad-ext.d: New.
+ * testsuite/gas/arm/armv8_4-a-fp16-ext.d: New.
+ * testsuite/gas/arm/armv8m.main+fp.d: New.
+ * testsuite/gas/arm/armv8m.main+fp.dp.d: New.
+ * testsuite/gas/arm/attr-ext-fpv5-d16.d: New.
+ * testsuite/gas/arm/attr-ext-fpv5.d: New.
+ * testsuite/gas/arm/attr-ext-idiv.d: New.
+ * testsuite/gas/arm/attr-ext-mp.d: New.
+ * testsuite/gas/arm/attr-ext-neon-fp16.d: New.
+ * testsuite/gas/arm/attr-ext-neon-vfpv3.d: New.
+ * testsuite/gas/arm/attr-ext-neon-vfpv4.d: New.
+ * testsuite/gas/arm/attr-ext-sec.d: New.
+ * testsuite/gas/arm/attr-ext-vfpv3-d16-fp16.d: New.
+ * testsuite/gas/arm/attr-ext-vfpv3-d16.d: New.
+ * testsuite/gas/arm/attr-ext-vfpv3-fp16.d: New.
+ * testsuite/gas/arm/attr-ext-vfpv3.d: New.
+ * testsuite/gas/arm/attr-ext-vfpv3xd-fp.d: New.
+ * testsuite/gas/arm/attr-ext-vfpv3xd.d: New.
+ * testsuite/gas/arm/attr-ext-vfpv4-d16.d: New.
+ * testsuite/gas/arm/attr-ext-vfpv4-sp-d16.d: New.
+ * testsuite/gas/arm/attr-ext-vfpv4.d: New.
+ * testsuite/gas/arm/dotprod-mandatory-ext.d: New.
+ * testsuite/gas/arm/fpv5-d16.s: New.
+ * testsuite/gas/arm/fpv5-sp-d16.s: New.
+
+2019-03-28 Alan Modra <amodra@gmail.com>
+
+ PR 24390
+ * testsuite/gas/ppc/476.d: Update mtfsb*.
+ * testsuite/gas/ppc/a2.d: Likewise.
+
+2019-03-21 Alan Modra <amodra@gmail.com>
+
+ * emul.h (struct emulation): Delete strip_underscore.
+ * emul-target.h (emul_strip_underscore): Don't define.
+ (emul_struct_name): Update initialization.
+
+2019-03-21 Alan Modra <amodra@gmail.com>
+
+ * config/tc-d10v.c (md_apply_fix): Apply BFD_RELOC_8.
+ * config/tc-pdp11.c (md_apply_fix): Likewise.
+ * config/tc-d30v.c (md_apply_fix): Don't emit errors for BFD_RELOC_8,
+ BFD_RELOC_16, and BFD_RELOC_64.
+ * testsuite/gas/all/gas.exp: Move target exclusions for forward
+ test, but not cr16, to..
+ * testsuite/gas/all/forward.d: ..here, with explanation. Remove
+ d10v, d30v, and pdp11 xfails.
+
+2019-03-19 H.J. Lu <hongjiu.lu@intel.com>
+
+ * config/tc-i386.c (optimize_encoding): Don't check AVX for
+ EVEX vector load/store optimization. Check both operands for
+ ZMM register. Update EVEX vector load/store opcode check.
+ Choose EVEX Disp8 over VEX Disp32.
+ * testsuite/gas/i386/optimize-1.d: Updated.
+ * testsuite/gas/i386/optimize-1a.d: Likewise.
+ * testsuite/gas/i386/optimize-2.d: Likewise.
+ * testsuite/gas/i386/optimize-4.d: Likewise.
+ * testsuite/gas/i386/optimize-5.d: Likewise.
+ * testsuite/gas/i386/x86-64-optimize-2.d: Likewise.
+ * testsuite/gas/i386/x86-64-optimize-2a.d: Likewise.
+ * testsuite/gas/i386/x86-64-optimize-2b.d: Likewise.
+ * testsuite/gas/i386/x86-64-optimize-3.d: Likewise.
+ * testsuite/gas/i386/x86-64-optimize-5.d: Likewise.
+ * testsuite/gas/i386/x86-64-optimize-6.d: Likewise.
+ * testsuite/gas/i386/optimize-1.s: Add ZMM register load
+ test.
+ * testsuite/gas/i386/x86-64-optimize-2.s: Likewise.
+
2019-03-19 H.J. Lu <hongjiu.lu@intel.com>
PR gas/24352
2019-01-31 John Darrington <john@darrington.wattle.id.au>
- * config/tc-s12z.c (lex_imm): Add new argument exp_o.
+ * config/tc-s12z.c (lex_imm): Add new argument exp_o.
(emit_reloc): New function.
(md_apply_fix): [BFD_RELOC_S12Z_OPR] Recognise that it
can be either 2 bytes or 3 bytes long.
2019-01-09 John Darrington <john@darrington.wattle.id.au>
- * testsuite/gas/s12z/jsr.s: New case.
+ * testsuite/gas/s12z/jsr.s: New case.
* testsuite/gas/s12z/jsr.d: New case.
2019-01-09 Andrew Paprocki <andrew@ishiboo.com>
projects / binutils-gdb.git / blobdiff