+2006-07-07 James E Wilson <wilson@specifix.com>
+
+ * config/tc-mips.c (mips_cpu_info_table): Add sb1a.
+
+2006-07-06 Mohammed Adnène Trojette <adn@diwi.org>
+ Nick Clifton <nickc@redhat.com>
+
+ PR binutils/2877
+ * doc/as.texi: Fix spelling typo: branchs => branches.
+ * doc/c-m68hc11.texi: Likewise.
+ * config/tc-m68hc11.c: Likewise.
+ Support old spelling of command line switch for backwards
+ compatibility.
+
+2006-07-04 Thiemo Seufer <ths@mips.com>
+ David Ung <davidu@mips.com>
+
+ * config/tc-mips.c (s_is_linkonce): New function.
+ (mips16_mark_labels): Don't adjust mips16 symbol addresses for
+ weak, external, and linkonce symbols.
+ (pic_need_relax): Use s_is_linkonce.
+
+2006-06-24 H.J. Lu <hongjiu.lu@intel.com>
+
+ * doc/as.texinfo (Org): Remove space.
+ (P2align): Add "@var{abs-expr},".
+
+2006-06-23 H.J. Lu <hongjiu.lu@intel.com>
+
+ * config/tc-i386.c (cpu_arch_tune_set): New.
+ (cpu_arch_isa): Likewise.
+ (i386_align_code): Use xchg %ax,%ax for 2 byte nop. Optimize
+ nops with short or long nop sequences based on -march=/.arch
+ and -mtune=.
+ (set_cpu_arch): Set cpu_arch_isa. If cpu_arch_tune_set is 0,
+ set cpu_arch_tune and cpu_arch_tune_flags.
+ (md_parse_option): For -march=, set cpu_arch_isa and set
+ cpu_arch_tune and cpu_arch_tune_flags if cpu_arch_tune_set is
+ 0. Set cpu_arch_tune_set to 1 for -mtune=.
+ (i386_target_format): Don't set cpu_arch_tune.
+
+2006-06-23 Nigel Stephens <nigel@mips.com>
+
+ * config/tc-mips.c (nopic_need_relax): Handle -fdata-sections
+ generated .sbss.* and .gnu.linkonce.sb.*.
+
+2006-06-23 Thiemo Seufer <ths@mips.com>
+ David Ung <davidu@mips.com>
+
+ * config/tc-mips.h (TC_SEGMENT_INFO_TYPE): Declare per-segment
+ label_list.
+ * config/tc-mips.c (label_list): Define per-segment label_list.
+ (mips_clear_insn_labels, mips_move_labels, mips16_mark_labels,
+ append_insn, s_align, s_cons, s_float_cons, s_gpword, s_gpdword,
+ mips_from_file_after_relocs, mips_define_label): Use per-segment
+ label_list.
+
+2006-06-22 Thiemo Seufer <ths@mips.com>
+
+ * config/tc-mips.c (ISA_SUPPORTS_MIPS16E): New macro.
+ (append_insn): Use it.
+ (md_apply_fix): Whitespace formatting.
+ (md_begin, append_insn, macro, macro2, mips16_immed, mips_align,
+ mips16_extended_frag): Remove register specifier.
+ (md_convert_frag): Likewise. Use TRUE ans FALSE instead of numeric
+ constants.
+
+2006-06-21 Mark Shinwell <shinwell@codesourcery.com>
+
+ * config/tc-arm.c (s_arm_unwind_save_vfp_armv6): New. Parse
+ a directive saving VFP registers for ARMv6 or later.
+ (s_arm_unwind_save): Add parameter arch_v6 and call
+ s_arm_unwind_save_vfp or s_arm_unwind_save_vfp_armv6 as
+ appropriate.
+ (md_pseudo_table): Add entry for new "vsave" directive.
+ * doc/c-arm.texi: Correct error in example for "save"
+ directive (fstmdf -> fstmdx). Also document "vsave" directive.
+
+2006-06-18 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
+ Anatoly Sokolov <aesok@post.ru>
+
+ * config/tc-avr.c (mcu_types): Add support for atmega165p, atmega169p
+ and atmega644p devices. Rename atmega164/atmega324 devices to
+ atmega164p/atmega324p.
+ * doc/c-avr.texi: Document new mcu and arch options.
+
+2006-06-17 Nick Clifton <nickc@redhat.com>
+
+ * config/tc-arm.c (enum parse_operand_result): Move outside of
+ #ifdef OBJ_ELF so that non-ELF targeted ARM ports can build.
+
+2006-06-16 H.J. Lu <hongjiu.lu@intel.com>
+
+ * config/tc-i386.h (processor_type): New.
+ (arch_entry): Add type.
+
+ * config/tc-i386.c (cpu_arch_tune): New.
+ (cpu_arch_tune_flags): Likewise.
+ (cpu_arch_isa_flags): Likewise.
+ (cpu_arch): Updated.
+ (set_cpu_arch): Also update cpu_arch_isa_flags.
+ (md_assemble): Update cpu_arch_isa_flags.
+ (OPTION_MARCH): New.
+ (OPTION_MTUNE): Likewise.
+ (md_longopts): Add -march= and -mtune=.
+ (md_parse_option): Support -march= and -mtune=.
+ (md_show_usage): Add -march=CPU/-mtune=CPU.
+ (i386_target_format): Also update cpu_arch_isa_flags,
+ cpu_arch_tune and cpu_arch_tune_flags.
+
+ * doc/as.texinfo: Add -march=CPU/-mtune=CPU.
+
+ * doc/c-i386.texi: Document -march=CPU/-mtune=CPU.
+
+2006-06-15 Mark Shinwell <shinwell@codesourcery.com>
+
+ * config/tc-arm.c (enum parse_operand_result): New.
+ (struct group_reloc_table_entry): New.
+ (enum group_reloc_type): New.
+ (group_reloc_table): New array.
+ (find_group_reloc_table_entry): New function.
+ (parse_shifter_operand_group_reloc): New function.
+ (parse_address_main): New function, incorporating code
+ from the old parse_address function. To be used via...
+ (parse_address): wrapper for parse_address_main; and
+ (parse_address_group_reloc): new function, likewise.
+ (enum operand_parse_code): New codes OP_SHG, OP_ADDRGLDR,
+ OP_ADDRGLDRS, OP_ADDRGLDC.
+ (parse_operands): Support for these new operand codes.
+ New macro po_misc_or_fail_no_backtrack.
+ (encode_arm_cp_address): Preserve group relocations.
+ (insns): Modify to use the above operand codes where group
+ relocations are permitted.
+ (md_apply_fix): Handle the group relocations
+ ALU_PC_G0_NC through LDC_SB_G2.
+ (tc_gen_reloc): Likewise.
+ (arm_force_relocation): Leave group relocations for the linker.
+ (arm_fix_adjustable): Likewise.
+
+2006-06-15 Julian Brown <julian@codesourcery.com>
+
+ * config/tc-arm.c (do_vfp_nsyn_ldr_str): Remove, fold into...
+ (do_neon_ldr_str): Always defer to VFP encoding routines, which handle
+ relocs properly.
+
+2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
+
+ * config/tc-i386.c (process_suffix): Don't add rex64 for
+ "xchg %rax,%rax".
+
+2006-06-09 Thiemo Seufer <ths@mips.com>
+
+ * config/tc-mips.c (mips_ip): Maintain argument count.
+
+2006-06-09 Alan Modra <amodra@bigpond.net.au>
+
+ * config/tc-iq2000.c: Include sb.h.
+
+2006-06-08 Nigel Stephens <nigel@mips.com>
+
+ * config/tc-mips.c (mips_pseudo_table): Add "origin" and "repeat"
+ aliases for better compatibility with SGI tools.
+
+2006-06-08 Alan Modra <amodra@bigpond.net.au>
+
+ * configure.in (BFDLIB, BFDVER_H, ALL_OBJ_DEPS): Delete.
+ * Makefile.am (GASLIBS): Expand @BFDLIB@.
+ (BFDVER_H): Delete.
+ (OBJS): Expand @ALL_OBJ_DEPS@. Depend on all fopen-*.h variants.
+ (obj-aout.o): Depend on $(DEP_@target_get_type@_aout)
+ (obj-coff.o, obj-ecoff.o, obj-elf.o): Similarly.
+ Run "make dep-am".
+ * dep-in.sed: Don't substitute bfdver.h. Do remove symcat.h.
+ * Makefile.in: Regenerate.
+ * doc/Makefile.in: Regenerate.
+ * configure: Regenerate.
+
+2006-06-07 Joseph S. Myers <joseph@codesourcery.com>
+
+ * po/Make-in (pdf, ps): New dummy targets.
+
+2006-06-07 Julian Brown <julian@codesourcery.com>
+
+ * config/tc-arm.c (stdarg.h): include.
+ (arm_it): Add uncond_value field. Add isvec and issingle to operand
+ array.
+ (arm_reg_type): Add REG_TYPE_VFSD (single or double VFP reg) and
+ REG_TYPE_NSDQ (single, double or quad vector reg).
+ (reg_expected_msgs): Update.
+ (BAD_FPU): Add macro for unsupported FPU instruction error.
+ (parse_neon_type): Support 'd' as an alias for .f64.
+ (parse_typed_reg_or_scalar): Support REG_TYPE_VFSD, REG_TYPE_NSDQ
+ sets of registers.
+ (parse_vfp_reg_list): Don't update first arg on error.
+ (parse_neon_mov): Support extra syntax for VFP moves.
+ (operand_parse_code): Add OP_RVSD, OP_RNSDQ, OP_VRSDLST, OP_RVSD_IO,
+ OP_RNSDQ_RNSC, OP_RVC_PSR, OP_APSR_RR, OP_oRNSDQ.
+ (parse_operands): Support isvec, issingle operands fields, new parse
+ codes above.
+ (do_vfp_nsyn_mrs, do_vfp_nsyn_msr): New functions. Support VFP mrs,
+ msr variants.
+ (do_mrs, do_msr, do_t_mrs, do_t_msr): Add support for above.
+ (NEON_ENC_TAB): Add vnmul, vnmla, vnmls, vcmp, vcmpz, vcmpe, vcmpez.
+ (NEON_ENC_SINGLE, NEON_ENC_DOUBLE): Define macros.
+ (NEON_SHAPE_DEF): New macro. Define table of possible instruction
+ shapes.
+ (neon_shape): Redefine in terms of above.
+ (neon_shape_class): New enumeration, table of shape classes.
+ (neon_shape_el): New enumeration. One element of a shape.
+ (neon_shape_el_size): Register widths of above, where appropriate.
+ (neon_shape_info): New struct. Info for shape table.
+ (neon_shape_tab): New array.
+ (neon_type_mask): Add N_F64, N_VFP. Update N_MAX_NONSPECIAL.
+ (neon_check_shape): Rewrite as...
+ (neon_select_shape): New function to classify instruction shapes,
+ driven by new table neon_shape_tab array.
+ (neon_quad): New function. Return 1 if shape should set Q flag in
+ instructions (or equivalent), 0 otherwise.
+ (type_chk_of_el_type): Support F64.
+ (el_type_of_type_chk): Likewise.
+ (neon_check_type): Add support for VFP type checking (VFP data
+ elements fill their containing registers).
+ (do_vfp_cond_or_thumb): Fill in condition field in ARM mode, or 0xE
+ in thumb mode for VFP instructions.
+ (do_vfp_nsyn_opcode): New function. Look up the opcode in argument,
+ and encode the current instruction as if it were that opcode.
+ (try_vfp_nsyn): New. If this looks like a VFP instruction with ARGS
+ arguments, call function in PFN.
+ (do_vfp_nsyn_add_sub, do_vfp_nsyn_mla_mls, do_vfp_nsyn_mul)
+ (do_vfp_nsyn_abs_neg, do_vfp_nsyn_ldm_stm, do_vfp_nsyn_ldr_str)
+ (do_vfp_nsyn_sqrt, do_vfp_nsyn_div, do_vfp_nsyn_nmul)
+ (do_vfp_nsyn_cmp, nsyn_insert_sp, do_vfp_nsyn_push)
+ (do_vfp_nsyn_pop, do_vfp_nsyn_cvt, do_vfp_nsyn_cvtz): New functions.
+ Redirect Neon-syntax VFP instructions to VFP instruction handlers.
+ (do_neon_dyadic_i_su, do_neon_dyadic_i64_su, do_neon_shl_imm)
+ (do_neon_qshl_imm, do_neon_logic, do_neon_bitfield)
+ (neon_dyadic_misc, neon_compare, do_neon_tst, do_neon_qdmulh)
+ (do_neon_fcmp_absolute, do_neon_step, do_neon_sli, do_neon_sri)
+ (do_neon_qshlu_imm, neon_move_immediate, do_neon_mvn, do_neon_ext)
+ (do_neon_rev, do_neon_dup, do_neon_rshift_round_imm, do_neon_trn)
+ (do_neon_zip_uzp, do_neon_sat_abs_neg, do_neon_pair_long)
+ (do_neon_recip_est, do_neon_cls, do_neon_clz, do_neon_cnt)
+ (do_neon_swp): Use neon_select_shape not neon_check_shape. Use
+ neon_quad.
+ (vfp_or_neon_is_neon): New function. Call if a mnemonic shared
+ between VFP and Neon turns out to belong to Neon. Perform
+ architecture check and fill in condition field if appropriate.
+ (do_neon_addsub_if_i, do_neon_mac_maybe_scalar, do_neon_abs_neg)
+ (do_neon_cvt): Add support for VFP variants of instructions.
+ (neon_cvt_flavour): Extend to cover VFP conversions.
+ (do_neon_mov): Rewrite to use neon_select_shape. Add support for VFP
+ vmov variants.
+ (do_neon_ldr_str): Handle single-precision VFP load/store.
+ (do_neon_ld_st_interleave, do_neon_ld_st_lane, do_neon_ld_dup): Use
+ NS_NULL not NS_IGNORE.
+ (opcode_tag): Add OT_csuffixF for operands which either take a
+ conditional suffix, or have 0xF in the condition field.
+ (md_assemble): Add support for OT_csuffixF.
+ (NCE): Replace macro with...
+ (NCE_tag, NCE, NCEF): New macros.
+ (nCE): Replace macro with...
+ (nCE_tag, nCE, nCEF): New macros.
+ (insns): Add support for VFP insns or VFP versions of insns msr,
+ mrs, vsqrt, vdiv, vnmul, vnmla, vnmls, vcmp, vcmpe, vpush, vpop,
+ vcvtz, vmul, vmla, vmls, vadd, vsub, vabs, vneg, vldm, vldmia,
+ vldbdb, vstm, vstmia, vstmdb, vldr, vstr, vcvt, vmov. Group shared
+ VFP/Neon insns together.
+
+2006-06-07 Alan Modra <amodra@bigpond.net.au>
+ Ladislav Michl <ladis@linux-mips.org>
+
+ * app.c: Don't include headers already included by as.h.
+ * as.c: Likewise.
+ * atof-generic.c: Likewise.
+ * cgen.c: Likewise.
+ * dwarf2dbg.c: Likewise.
+ * expr.c: Likewise.
+ * input-file.c: Likewise.
+ * input-scrub.c: Likewise.
+ * macro.c: Likewise.
+ * output-file.c: Likewise.
+ * read.c: Likewise.
+ * sb.c: Likewise.
+ * config/bfin-lex.l: Likewise.
+ * config/obj-coff.h: Likewise.
+ * config/obj-elf.h: Likewise.
+ * config/obj-som.h: Likewise.
+ * config/tc-arc.c: Likewise.
+ * config/tc-arm.c: Likewise.
+ * config/tc-avr.c: Likewise.
+ * config/tc-bfin.c: Likewise.
+ * config/tc-cris.c: Likewise.
+ * config/tc-d10v.c: Likewise.
+ * config/tc-d30v.c: Likewise.
+ * config/tc-dlx.h: Likewise.
+ * config/tc-fr30.c: Likewise.
+ * config/tc-frv.c: Likewise.
+ * config/tc-h8300.c: Likewise.
+ * config/tc-hppa.c: Likewise.
+ * config/tc-i370.c: Likewise.
+ * config/tc-i860.c: Likewise.
+ * config/tc-i960.c: Likewise.
+ * config/tc-ip2k.c: Likewise.
+ * config/tc-iq2000.c: Likewise.
+ * config/tc-m32c.c: Likewise.
+ * config/tc-m32r.c: Likewise.
+ * config/tc-maxq.c: Likewise.
+ * config/tc-mcore.c: Likewise.
+ * config/tc-mips.c: Likewise.
+ * config/tc-mmix.c: Likewise.
+ * config/tc-mn10200.c: Likewise.
+ * config/tc-mn10300.c: Likewise.
+ * config/tc-msp430.c: Likewise.
+ * config/tc-mt.c: Likewise.
+ * config/tc-ns32k.c: Likewise.
+ * config/tc-openrisc.c: Likewise.
+ * config/tc-ppc.c: Likewise.
+ * config/tc-s390.c: Likewise.
+ * config/tc-sh.c: Likewise.
+ * config/tc-sh64.c: Likewise.
+ * config/tc-sparc.c: Likewise.
+ * config/tc-tic30.c: Likewise.
+ * config/tc-tic4x.c: Likewise.
+ * config/tc-tic54x.c: Likewise.
+ * config/tc-v850.c: Likewise.
+ * config/tc-vax.c: Likewise.
+ * config/tc-xc16x.c: Likewise.
+ * config/tc-xstormy16.c: Likewise.
+ * config/tc-xtensa.c: Likewise.
+ * config/tc-z80.c: Likewise.
+ * config/tc-z8k.c: Likewise.
+ * macro.h: Don't include sb.h or ansidecl.h.
+ * sb.h: Don't include stdio.h or ansidecl.h.
+ * cond.c: Include sb.h.
+ * itbl-lex.l: Include as.h instead of other system headers.
+ * itbl-parse.y: Likewise.
+ * itbl-ops.c: Similarly.
+ * itbl-ops.h: Don't include as.h or ansidecl.h.
+ * config/bfin-defs.h: Don't include bfd.h or as.h.
+ * config/bfin-parse.y: Include as.h instead of other system headers.
+
+2006-06-06 Ben Elliston <bje@au.ibm.com>
+ Anton Blanchard <anton@samba.org>
+
+ * config/tc-ppc.c (parse_cpu): Handle "-mpower6".
+ (md_show_usage): Document it.
+ (ppc_setup_opcodes): Test power6 opcode flag bits.
+ * doc/c-ppc.texi (PowerPC-Opts): Document "-mpower6".
+
+2006-06-06 Thiemo Seufer <ths@mips.com>
+ Chao-ying Fu <fu@mips.com>
+
+ * config/tc-mips.c (ISA_SUPPORTS_DSP64): New macro.
+ (CPU_HAS_MIPS3D, CPU_HAS_MDMX, CPU_HAS_DSP, CPU_HAS_MT): Delete.
+ (macro_build): Update comment.
+ (mips_ip): Allow DSP64 instructions for MIPS64R2.
+ (mips_after_parse_args): Remove uses of CPU_HAS_MIPS3D and
+ CPU_HAS_MDMX.
+ (mips_cpu_info): Fix formatting. Add MIPS_CPU_ASE_MIPS3D and
+ MIPS_CPU_ASE_MDMX flags for sb1.
+
+2006-06-05 Thiemo Seufer <ths@mips.com>
+
+ * config/tc-mips.c (macro_build): Use INSERT_OPERAND wherew
+ appropriate.
+ (mips16_macro_build): Use MIPS16_INSERT_OPERAND where appropriate.
+ (mips_ip): Make overflowed/underflowed constant arguments in DSP
+ and MT instructions a fatal error. Use INSERT_OPERAND where
+ appropriate. Improve warnings for break and wait code overflows.
+ Use symbolic constant of OP_MASK_COPZ.
+ (mips16_ip): Use MIPS16_INSERT_OPERAND where appropriate.
+
+2006-06-05 Daniel Jacobowitz <dan@codesourcery.com>
+
+ * po/Make-in (top_builddir): Define.
+
+2006-06-02 Joseph S. Myers <joseph@codesourcery.com>
+
+ * doc/Makefile.am (TEXI2DVI): Define.
+ * doc/Makefile.in: Regenerate.
+ * doc/c-arc.texi: Fix typo.
+
+2006-06-01 Alan Modra <amodra@bigpond.net.au>
+
+ * config/obj-ieee.c: Delete.
+ * config/obj-ieee.h: Delete.
+ * Makefile.am (OBJ_FORMATS): Remove ieee.
+ (OBJ_FORMAT_CFILES, OBJ_FORMAT_HFILES): Similarly.
+ (obj-ieee.o): Remove rule.
+ * Makefile.in: Regenerate.
+ * configure.in (atof): Remove tahoe.
+ (OBJ_MAYBE_IEEE): Don't define.
+ * configure: Regenerate.
+ * config.in: Regenerate.
+ * doc/Makefile.in: Regenerate.
+ * po/POTFILES.in: Regenerate.
+
+2006-05-31 Daniel Jacobowitz <dan@codesourcery.com>
+
+ * Makefile.am: Replace INTLLIBS and INTLDEPS with LIBINTL
+ and LIBINTL_DEP everywhere.
+ (INTLLIBS): Remove.
+ (INCLUDES, DEP_INCLUDES): Use @INCINTL@.
+ * acinclude.m4: Include new gettext macros.
+ * configure.in: Use ZW_GNU_GETTEXT_SISTER_DIR and AM_PO_SUBDIRS.
+ Remove local code for po/Makefile.
+ * Makefile.in, configure, doc/Makefile.in: Regenerated.
+
+2006-05-30 Nick Clifton <nickc@redhat.com>
+
+ * po/es.po: Updated Spanish translation.
+
+2006-05-06 Denis Chertykov <denisc@overta.ru>
+
+ * doc/c-avr.texi: New file.
+ * doc/Makefile.am (CPU_DOCS): Add c-avr.texi
+ * doc/all.texi: Set AVR
+ * doc/as.texinfo: Include c-avr.texi
+
+2006-05-28 Jie Zhang <jie.zhang@analog.com>
+
+ * config/bfin-parse.y (check_macfunc): Loose the condition of
+ calling check_multiply_halfregs ().
+
+2006-05-25 Jie Zhang <jie.zhang@analog.com>
+
+ * config/bfin-parse.y (asm_1): Better check and deal with
+ vector and scalar Multiply 16-Bit Operands instructions.
+
+2006-05-24 Nick Clifton <nickc@redhat.com>
+
+ * config/tc-hppa.c: Convert to ISO C90 format.
+ * config/tc-hppa.h: Likewise.
+
+2006-05-24 Carlos O'Donell <carlos@systemhalted.org>
+ Randolph Chung <randolph@tausq.org>
+
+ * config/tc-hppa.c (is_tls_gdidx, is_tls_ldidx, is_tls_dtpoff,
+ is_tls_ieoff, is_tls_leoff): Define.
+ (fix_new_hppa): Handle TLS.
+ (cons_fix_new_hppa): Likewise.
+ (pa_ip): Likewise.
+ (md_apply_fix): Handle TLS relocs.
+ * config/tc-hppa.h (hppa_fix_adjustable): Handle TLS.
+
+2006-05-24 Bjoern Haase <bjoern.m.haase@web.de>
+
+ * config/tc-avr.c: Add new cpu targets avr6, avr2560 and avr2561.
+
+2006-05-23 Thiemo Seufer <ths@mips.com>
+ David Ung <davidu@mips.com>
+ Nigel Stephens <nigel@mips.com>
+
+ [ gas/ChangeLog ]
+ * config/tc-mips.c (ISA_SUPPORTS_SMARTMIPS): Rename.
+ (ISA_SUPPORTS_DSP_ASE, ISA_SUPPORTS_MT_ASE, ISA_HAS_64BIT_FPRS,
+ ISA_HAS_MXHC1): New macros.
+ (HAVE_32BIT_FPRS): Use ISA_HAS_64BIT_FPRS instead of
+ ISA_HAS_64BIT_REGS. Formatting fixes. Improved comments.
+ (mips_cpu_info): Change to use combined ASE/IS_ISA flag.
+ (MIPS_CPU_IS_ISA, MIPS_CPU_ASE_SMARTMIPS, MIPS_CPU_ASE_DSP,
+ MIPS_CPU_ASE_MT, MIPS_CPU_ASE_MIPS3D, MIPS_CPU_ASE_MDMX): New defines.
+ (mips_after_parse_args): Change default handling of float register
+ size to account for 32bit code with 64bit FP. Better sanity checking
+ of ISA/ASE/ABI option combinations.
+ (s_mipsset): Support switching of GPR and FPR sizes via
+ .set {g,f}p={32,64,default}. Better sanity checking for .set ASE
+ options.
+ (mips_elf_final_processing): We should record the use of 64bit FP
+ registers in 32bit code but we don't, because ELF header flags are
+ a scarce ressource.
+ (mips_cpu_info_table): Add ASE flags for CPUs with mandatory ASE
+ extensions. Add 4ksc, 4kec, 4kem, 4kep, 4ksd, m4kp, 24kec, 24kef,
+ 24kex, 34kc, 34kf, 34kx, 25kf CPU definitions.
+ (mips_cpu_info_from_isa): Use MIPS_CPU_IS_ISA.
+ * doc/c-mips.texi: Document .set {g,f}p={32,64,default}. Document
+ missing -march options. Document .set arch=CPU. Move .set smartmips
+ to ASE page. Use @code for .set FOO examples.
+
+2006-05-23 Jie Zhang <jie.zhang@analog.com>
+
+ * config/tc-bfin.c (bfin_start_line_hook): Bump line counters
+ if needed.
+
+2006-05-23 Jie Zhang <jie.zhang@analog.com>
+
+ * config/bfin-defs.h (bfin_equals): Remove declaration.
+ * config/bfin-parse.y (asm_1): Remove "expr ASSIGN expr".
+ * config/tc-bfin.c (bfin_name_is_register): Remove.
+ (bfin_equals): Remove.
+ * config/tc-bfin.h (TC_EQUAL_IN_INSN): Redefine as 1.
+ (bfin_name_is_register): Remove declaration.
+
+2006-05-19 Thiemo Seufer <ths@mips.com>
+ Nigel Stephens <nigel@mips.com>
+
+ * config/tc-mipc.c (ISA_HAS_ODD_SINGLE_FPR): New define.
+ (mips_oddfpreg_ok): New function.
+ (mips_ip): Use it.
+
+2006-05-19 Thiemo Seufer <ths@mips.com>
+ David Ung <davidu@mips.com>
+
+ * config/tc-mips.h (tc_mips_regname_to_dw2regnum): Declare.
+ * config/tc-mipc.c (ABI_NEEDS_64BIT_REGS, ISA_HAS_64BIT_REGS,
+ ISA_HAS_DROR, ISA_HAS_ROR): Reformat.
+ (regname, RTYPE_MASK, RTYPE_NUM, RTYPE_FPU, RTYPE_FCC, RTYPE_VEC,
+ RTYPE_GP, RTYPE_CP0, RTYPE_PC, RTYPE_ACC, RTYPE_CCC, RNUM_MASK,
+ RWARN, GENERIC_REGISTER_NUMBERS, FPU_REGISTER_NAMES,
+ FPU_CONDITION_CODE_NAMES, COPROC_CONDITION_CODE_NAMES,
+ N32N64_SYMBOLIC_REGISTER_NAMES, O32_SYMBOLIC_REGISTER_NAMES,
+ SYMBOLIC_REGISTER_NAMES, MIPS16_SPECIAL_REGISTER_NAMES,
+ MDMX_VECTOR_REGISTER_NAMES, MIPS_DSP_ACCUMULATOR_NAMES, reg_names,
+ reg_names_o32, reg_names_n32n64): Define register classes.
+ (reg_lookup): New function, use register classes.
+ (md_begin): Reserve register names in the symbol table. Simplify
+ OBJ_ELF defines.
+ (mips_ip): Fix comment formatting. Handle symbolic COP0 registers.
+ Use reg_lookup.
+ (mips16_ip): Use reg_lookup.
+ (tc_get_register): Likewise.
+ (tc_mips_regname_to_dw2regnum): New function.
+
+2006-05-19 Thiemo Seufer <ths@mips.com>
+
+ * config/tc-arm.c, config/tc-arm.h (tc_arm_regname_to_dw2regnum):
+ Un-constify string argument.
+ * config/tc-i386.c, config/tc-i386.h (tc_x86_regname_to_dw2regnum):
+ Likewise.
+ * config/tc-m68k.c, config/tc-m68k.h (tc_m68k_regname_to_dw2regnum):
+ Likewise.
+ * config/tc-ppc.c, config/tc-ppc.h (tc_ppc_regname_to_dw2regnum):
+ Likewise.
+ * config/tc-s390.c, config/tc-s390.h (tc_s390_regname_to_dw2regnum):
+ Likewise.
+ * config/tc-sh.c, config/tc-sh.h (sh_regname_to_dw2regnum):
+ Likewise.
+ * config/tc-sparc.c, config/tc-sparc.h (sparc_regname_to_dw2regnum):
+ Likewise.
+
+2006-05-19 Nathan Sidwell <nathan@codesourcery.com>
+
+ * gas/config/tc-m68k.c (m68k_init_arch): Move checking of
+ cfloat/m68881 to correct architecture before using it.
+
+2006-05-16 Bjoern Haase <bjoern.m.haase@web.de>
+
+ * config/tc-avr.h (TC_VALIDATE_FIX): Allow fixups for immediate
+ constant values.
+
+2006-05-15 Paul Brook <paul@codesourcery.com>
+
+ * config/tc-arm.c (arm_adjust_symtab): Use
+ bfd_is_arm_special_symbol_name.
+
+2006-05-15 Bob Wilson <bob.wilson@acm.org>
+
+ * config/tc-xtensa.c (is_direct_call_opcode, is_branch_jmp_to_next,
+ xg_assemble_vliw_tokens, xtensa_mark_narrow_branches,
+ xtensa_fix_short_loop_frags, is_local_forward_loop, relax_frag_immed):
+ Handle errors from calls to xtensa_opcode_is_* functions.
+
+2006-05-14 Thiemo Seufer <ths@mips.com>
+
+ * config/tc-mips.c (macro_build): Test for currently active
+ mips16 option.
+ (mips16_ip): Reject invalid opcodes.
+
+2006-05-11 Carlos O'Donell <carlos@codesourcery.com>
+
+ * doc/as.texinfo: Rename "Index" to "AS Index",
+ and "ABORT" to "ABORT (COFF)".
+
+2006-05-11 Paul Brook <paul@codesourcery.com>
+
+ * config/tc-arm.c (parse_half): New function.
+ (operand_parse_code): Remove OP_Iffff. Add OP_HALF.
+ (parse_operands): Ditto.
+ (do_mov16): Reject invalid relocations.
+ (do_t_mov16): Ditto. Use Thumb reloc numbers.
+ (insns): Replace Iffff with HALF.
+ (md_apply_fix): Add MOVW and MOVT relocs.
+ (tc_gen_reloc): Ditto.
+ * doc/c-arm.texi: Document relocation operators
+
+2006-05-11 Paul Brook <paul@codesourcery.com>
+
+ * config/tc-arm.c (arm_fix_adjustable): Return 0 for function symbols.
+
2006-05-11 Thiemo Seufer <ths@mips.com>
* config/tc-mips.c (append_insn): Don't check the range of j or
projects / binutils-gdb.git / blobdiff