-*- text -*-
+* Remove (rudimentary) support for the x86-64 sub-architectures Intel L1OM and
+ Intel K1OM.
+
+Changes in 2.38:
+
+* Add support for AArch64 system registers that were missing in previous
+ releases.
+
+* Add support for the LoongArch instruction set.
+
+* Add a command-line option, -muse-unaligned-vector-move, for x86 target
+ to encode aligned vector move as unaligned vector move.
+
+* Add support for Cortex-R52+ for Arm.
+
+* Add support for Cortex-A510, Cortex-A710, Cortex-X2 for AArch64.
+
+* Add support for Cortex-A710 for Arm.
+
+* Add support for Scalable Matrix Extension (SME) for AArch64.
+
+* The --multibyte-handling=[allow|warn|warn-sym-only] option tells the
+ assembler what to when it encoutners multibyte characters in the input. The
+ default is to allow them. Setting the option to "warn" will generate a
+ warning message whenever any multibyte character is encountered. Using the
+ option to "warn-sym-only" will make the assembler generate a warning whenever a
+ symbol is defined containing multibyte characters. (References to undefined
+ symbols will not generate warnings).
+
+* Outputs of .ds.x directive and .tfloat directive with hex input from
+ x86 assembler have been reduced from 12 bytes to 10 bytes to match the
+ output of .tfloat directive.
+
+* Add support for 'armv8.8-a', 'armv9-a', 'armv9.1-a', 'armv9.2-a' and
+ 'armv9.3-a' for -march in AArch64 GAS.
+
+* Add support for 'armv8.7-a', 'armv8.8-a', 'armv9-a', 'armv9.1-a',
+ 'armv9.2-a' and 'armv9.3-a' for -march in Arm GAS.
+
+* Add support for Intel AVX512_FP16 instructions.
+
+Changes in 2.37:
+
+* arm-symbianelf support removed.
+
+* Add support for Realm Management Extension (RME) for AArch64.
+
+Changes in 2.36:
+
+* Add support for Intel AVX VNNI instructions.
+
+* Add support for Intel HRESET instruction.
+
+* Add support for Intel UINTR instructions.
+
+* Support non-absolute segment values for i386 lcall and ljmp.
+
+* When setting the link order attribute of ELF sections, it is now possible to
+ use a numeric section index instead of symbol name.
+
+* Add support for Cortex-A78, Cortex-A78AE, Cortex-A78C and Cortex-X1 for
+ AArch64 and ARM.
+ Add support for Cortex-R82, Neoverse V1, and Neoverse N2 for ARM.
+
+* Add support for ETMv4 (Embedded Trace Macrocell), ETE (Embedded Trace
+ Extension), TRBE (Trace Buffer Extension)and BRBE (Branch Record Buffer
+ Extension) system registers for AArch64.
+
+* Add support for Armv8-R and Armv8.7-A AArch64.
+
+* Add support for DSB memory nXS barrier, WFET and WFIT instruction for Armv8.7
+ AArch64.
+
+* Add support for +flagm feature for -march in Armv8.4 AArch64.
+
+* Add support for +ls64 feature for -march in Armv8.7 AArch64. Add atomic
+ 64-byte load/store instructions for this feature.
+
+* Add support for +pauth (Pointer Authentication) feature for -march in
+ AArch64.
+
+* Add support for Intel TDX instructions.
+
+* Add support for Intel Key Locker instructions.
+
+* Added a .nop directive to generate a single no-op instruction in a target
+ neutral manner. This instruction does have an effect on DWARF line number
+ generation, if that is active.
+
+* Removed --reduce-memory-overheads and --hash-size as gas now
+ uses hash tables that can be expand and shrink automatically.
+
+* Add {disp16} pseudo prefix to x86 assembler.
+
+* Add support for Intel AMX instructions.
+
+* Configure with --enable-x86-used-note by default for Linux/x86.
+
+* Add support for the SHF_GNU_RETAIN flag, which can be applied to
+ sections using the 'R' flag in the .section directive.
+ SHF_GNU_RETAIN specifies that the section should not be garbage
+ collected by the linker. It requires the GNU or FreeBSD ELF OSABIs.
+
+Changes in 2.35:
+
+* X86 NaCl target support is removed.
+
+* Extend .symver directive to update visibility of the original symbol
+ and assign one original symbol to different versioned symbols.
+
+* Add support for Intel SERIALIZE and TSXLDTRK instructions.
+
+* Add -mlfence-after-load=, -mlfence-before-indirect-branch= and
+ -mlfence-before-ret= options to x86 assembler to help mitigate
+ CVE-2020-0551.
+
+* Add --gdwarf-5 option to the assembler to generate DWARF 5 debug output
+ (if such output is being generated). Added the ability to generate
+ version 5 .debug_line sections.
+
+* Add -mbig-obj support to i386 MingW targets.
+
+Changes in 2.34:
+
+* Add -malign-branch-boundary=NUM, -malign-branch=TYPE[+TYPE...],
+ -malign-branch-prefix-size=NUM and -mbranches-within-32B-boundaries
+ options to x86 assembler to align branches within a fixed boundary
+ with segment prefixes or NOPs.
+
+* Add support for Zilog eZ80 and Zilog Z180 CPUs.
+
+* Add support for z80-elf target.
+
+* Add support for relocation of each byte or word of multibyte value to Z80
+ targets (just use right shift to 0, 8, 16, or 24 bits or AND operation
+ with 0xff/0xffff mask): ld a, label >> 16 \ ld hl, label & 0xffff
+
+* Add SDCC support for Z80 targets.
+
+Changes in 2.33:
+
+* Add support for the Arm Scalable Vector Extension version 2 (SVE2)
+ instructions.
+
+* Add support for the Arm Transactional Memory Extension (TME)
+ instructions.
+
+* Add support for the Armv8.1-M Mainline and M-profile Vector Extension (MVE)
+ instructions.
+
+* For MIPS, Add -m[no-]fix-loongson3-llsc option to fix (or not) Loongson3
+ LLSC Errata. Add a --enable-mips-fix-loongson3-llsc=[yes|no] configure
+ time option to set the default behavior. Set the default if the configure
+ option is not used to "no".
+
+* Add support for the Arm Cortex-A76AE, Cortex-A77 and Cortex-M35P
+ processors.
+
+* Add support for the AArch64 Cortex-A34, Cortex-A65, Cortex-A65AE,
+ Cortex-A76AE, and Cortex-A77 processors.
+
+* Add .float16 directive for both Arm and AArch64 to allow encoding of 16-bit
+ floating point literals. Add .float16_format directive and
+ -mfp16-format=[ieee|alternative] option for Arm to control the format of the
+ encoding.
+
+* Add --gdwarf-cie-version command line flag. This allows control over which
+ version of DWARF CIE the assembler creates.
+
+Changes in 2.32:
+
+* Add -mvexwig=[0|1] option to x86 assembler to control encoding of
+ VEX.W-ignored (WIG) VEX instructions.
+
+* Add -mx86-used-note=[yes|no] option to generate (or not) x86 GNU property
+ notes. Add a --enable-x86-used-note configure time option to set the
+ default behavior. Set the default if the configure option is not used
+ to "no".
+
+* Add support for the MIPS Loongson EXTensions R2 (EXT2) instructions.
+
+* Add support for the MIPS Loongson EXTensions (EXT) instructions.
+
+* Add support for the MIPS Loongson Content Address Memory (CAM) ASE.
+
+* Add support for the C-SKY processor series.
+
+* Add support for the MIPS Loongson MultiMedia extensions Instructions (MMI)
+ ASE.
+
+Changes in 2.31:
+
+* The ADR and ADRL pseudo-instructions supported by the ARM assembler
+ now only set the bottom bit of the address of thumb function symbols
+ if the -mthumb-interwork command line option is active.
+
+* Add support for the MIPS Global INValidate (GINV) ASE.
+
+* Add support for the MIPS Cyclic Redudancy Check (CRC) ASE.
+
+* Add support for the Freescale S12Z architecture.
+
+* Add --generate-missing-build-notes=[yes|no] option to create (or not) GNU
+ Build Attribute notes if none are present in the input sources. Add a
+ --enable-generate-build-notes=[yes|no] configure time option to set the
+ default behaviour. Set the default if the configure option is not used
+ to "no".
+
+* Remove -mold-gcc command-line option for x86 targets.
+
* Add -O[2|s] command-line options to x86 assembler to enable alternate
shorter instruction encoding.
assembler should generate common symbols with the STT_COMMON type by
default. Default to no.
-* New command line option --elf-stt-common= for ELF targets to control
+* New command-line option --elf-stt-common= for ELF targets to control
whether to generate common symbols with the STT_COMMON type.
* Add ability to set section flags and types via numeric values for ELF
x86 assembler should generate relax relocations by default. Default to
yes, except for x86 Solaris targets older than Solaris 12.
-* New command line option -mrelax-relocations= for x86 target to control
+* New command-line option -mrelax-relocations= for x86 target to control
whether to generate relax relocations.
-* New command line option -mfence-as-lock-add=yes for x86 target to encode
+* New command-line option -mfence-as-lock-add=yes for x86 target to encode
lfence, mfence and sfence as "lock addl $0x0, (%[re]sp)".
* Add assembly-time relaxation option for ARC cpus.
* Replace support for openrisc and or32 with support for or1k.
* Enhanced the ARM port to accept the assembler output from the CodeComposer
- Studio tool. Support is enabled via the new command line option -mccs.
+ Studio tool. Support is enabled via the new command-line option -mccs.
* Add support for the Andes NDS32.
* Add support for the Texas Instruments MSP430X processor.
-* Add -gdwarf-sections command line option to enable per-code-section
+* Add -gdwarf-sections command-line option to enable per-code-section
generation of DWARF .debug_line sections.
* Add support for Altera Nios II.
* Add support for the Renesas RX processor.
-* New command line option, --compress-debug-sections, which requests
+* New command-line option, --compress-debug-sections, which requests
compression of DWARF debug information sections in the relocatable output
file. Compressed debug sections are supported by readelf, objdump, and
gold, but not currently by Gnu ld.
* New pseudo op .cfi_val_encoded_addr, to record constant addresses in unwind
tables without runtime relocation.
-* New command line option, -h-tick-hex, for sh, m32c, and h8/300 targets, which
+* New command-line option, -h-tick-hex, for sh, m32c, and h8/300 targets, which
adds compatibility with H'00 style hex constants.
-* New command line option, -msse-check=[none|error|warning], for x86
+* New command-line option, -msse-check=[none|error|warning], for x86
targets.
-* New sub-option added to the assembler's -a command line switch to
+* New sub-option added to the assembler's -a command-line switch to
generate a listing output. The 'g' sub-option will insert into the listing
various information about the assembly, such as assembler version, the
- command line options used, and a time stamp.
+ command-line options used, and a time stamp.
-* New command line option -msse2avx for x86 target to encode SSE
+* New command-line option -msse2avx for x86 target to encode SSE
instructions with VEX prefix.
* Add Intel XSAVE, EPT, MOVBE, AES, PCLMUL, AVX/FMA support for x86 target.
-* New command line options, -march=CPU[,+EXTENSION...], -mtune=CPU,
+* New command-line options, -march=CPU[,+EXTENSION...], -mtune=CPU,
-mmnemonic=[att|intel], -msyntax=[att|intel], -mindex-reg,
-mnaked-reg and -mold-gcc, for x86 targets.
* Add support for the "@<file>" syntax to the command line, so that extra
switches can be read from <file>.
-* The SH target supports a new command line switch --enable-reg-prefix which,
+* The SH target supports a new command-line switch --enable-reg-prefix which,
if enabled, will allow register names to be optionally prefixed with a $
character. This allows register names to be distinguished from label names.
for the VAX target in order to be more compatible with the VAX MACRO
assembler.
-* New command line option -mtune=[itanium1|itanium2] for IA64 targets.
+* New command-line option -mtune=[itanium1|itanium2] for IA64 targets.
Changes in 2.16:
* Redefinition of macros now results in an error.
-* New command line option -mhint.b=[ok|warning|error] for IA64 targets.
+* New command-line option -mhint.b=[ok|warning|error] for IA64 targets.
-* New command line option -munwind-check=[warning|error] for IA64
+* New command-line option -munwind-check=[warning|error] for IA64
targets.
* The IA64 port now uses automatic dependency violation removal as its default
* Added support for generating unwind tables for ARM ELF targets.
-* Add a -g command line option to generate debug information in the target's
+* Add a -g command-line option to generate debug information in the target's
preferred debug format.
* Support for the crx-elf target added.
* Support for ColdFire EMAC instructions added and Motorola syntax for MAC/EMAC
instrucitons.
-* New command line option -mno-shared for MIPS ELF targets.
+* New command-line option -mno-shared for MIPS ELF targets.
-* New command line option --alternate and pseudo-ops .altmacro and .noaltmacro
+* New command-line option --alternate and pseudo-ops .altmacro and .noaltmacro
added to enter (and leave) alternate macro syntax mode.
Changes in 2.15:
but still works for compatability.
* The MIPS assembler no longer issues a warning by default when it
- generates a nop instruction from a macro. The new command line option
+ generates a nop instruction from a macro. The new command-line option
-n will turn on the warning.
Changes in 2.11:
* x86 gas has a new .arch pseudo op to specify the target CPU architecture.
-* x86 gas -q command line option quietens warnings about register size changes
+* x86 gas -q command-line option quietens warnings about register size changes
due to suffix, indirect jmp/call without `*', stand-alone prefixes, and
translating various deprecated floating point instructions.
of new CPUs and formats, lots of bugs fixed.
\f
-Copyright (C) 2012-2018 Free Software Foundation, Inc.
+Copyright (C) 2012-2022 Free Software Foundation, Inc.
Copying and distribution of this file, with or without modification,
are permitted in any medium without royalty provided the copyright
projects / binutils-gdb.git / blobdiff