/* tc-arm.c -- Assemble for the ARM
- Copyright (C) 1994, 95, 96, 97, 98, 1999, 2000
+ Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001
Free Software Foundation, Inc.
Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
Modified by David Taylor (dtaylor@armltd.co.uk)
+ Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
This file is part of GAS, the GNU Assembler.
Software Foundation, 59 Temple Place - Suite 330, Boston, MA
02111-1307, USA. */
-#include <ctype.h>
#include <string.h>
#define NO_RELOC 0
#include "as.h"
+#include "safe-ctype.h"
/* Need TARGET_CPU. */
#include "config.h"
#define ARM_CPU_MASK 0x0000000f
/* The following bitmasks control CPU extensions (ARM7 onwards): */
-#define ARM_LONGMUL 0x00000010 /* Allow long multiplies. */
-#define ARM_HALFWORD 0x00000020 /* Allow half word loads. */
-#define ARM_THUMB 0x00000040 /* Allow BX instruction. */
+#define ARM_EXT_LONGMUL 0x00000010 /* Allow long multiplies. */
+#define ARM_EXT_HALFWORD 0x00000020 /* Allow half word loads. */
+#define ARM_EXT_THUMB 0x00000040 /* Allow BX instruction. */
#define ARM_EXT_V5 0x00000080 /* Allow CLZ, etc. */
+#define ARM_EXT_V5E 0x00000100 /* "El Segundo". */
+#define ARM_EXT_XSCALE 0x00000200 /* Allow MIA etc. */
+#define ARM_EXT_MAVERICK 0x00000400 /* Use Cirrus/DSP coprocessor. */
/* Architectures are the sum of the base and extensions. */
-#define ARM_ARCH_V4 (ARM_7 | ARM_LONGMUL | ARM_HALFWORD)
-#define ARM_ARCH_V4T (ARM_ARCH_V4 | ARM_THUMB)
+#define ARM_ARCH_V3M ARM_EXT_LONGMUL
+#define ARM_ARCH_V4 (ARM_ARCH_V3M | ARM_EXT_HALFWORD)
+#define ARM_ARCH_V4T (ARM_ARCH_V4 | ARM_EXT_THUMB)
#define ARM_ARCH_V5 (ARM_ARCH_V4 | ARM_EXT_V5)
-#define ARM_ARCH_V5T (ARM_ARCH_V5 | ARM_THUMB)
+#define ARM_ARCH_V5T (ARM_ARCH_V5 | ARM_EXT_THUMB)
+#define ARM_ARCH_V5TE (ARM_ARCH_V5T | ARM_EXT_V5E)
+#define ARM_ARCH_XSCALE (ARM_ARCH_V5TE | ARM_EXT_XSCALE)
/* Some useful combinations: */
#define ARM_ANY 0x00ffffff
#define FPU_MEMMULTI 0x7f000000 /* Not fpu_core. */
#ifndef CPU_DEFAULT
+#if defined __XSCALE__
+#define CPU_DEFAULT (ARM_9 | ARM_ARCH_XSCALE)
+#else
#if defined __thumb__
-#define CPU_DEFAULT (ARM_ARCH_V4 | ARM_THUMB)
+#define CPU_DEFAULT (ARM_7 | ARM_ARCH_V4T)
#else
-#define CPU_DEFAULT ARM_ALL
+#define CPU_DEFAULT ARM_ALL
+#endif
#endif
#endif
#if defined OBJ_COFF || defined OBJ_ELF
/* Flags stored in private area of BFD structure. */
static boolean uses_apcs_26 = false;
+static boolean atpcs = false;
static boolean support_interwork = false;
static boolean uses_apcs_float = false;
static boolean pic_code = false;
/* This array holds the chars that always start a comment. If the
pre-processor is disabled, these aren't very useful. */
-CONST char comment_chars[] = "@";
+const char comment_chars[] = "@";
/* This array holds the chars that only start a comment at the beginning of
a line. If the line seems to have the form '# 123 filename'
first line of the input file. This is because the compiler outputs
#NO_APP at the beginning of its output. */
/* Also note that comments like this one will always work. */
-CONST char line_comment_chars[] = "#";
+const char line_comment_chars[] = "#";
-CONST char line_separator_chars[] = ";";
+const char line_separator_chars[] = "|";
/* Chars that can be used to separate mant
from exp in floating point numbers. */
-CONST char EXP_CHARS[] = "eE";
+const char EXP_CHARS[] = "eE";
/* Chars that mean this number is a floating point constant. */
/* As in 0f12.456 */
/* or 0d1.2345e12 */
-CONST char FLT_CHARS[] = "rRsSfFdDxXeEpP";
+const char FLT_CHARS[] = "rRsSfFdDxXeEpP";
/* Prefix characters that indicate the start of an immediate
value. */
#endif
/* Size of relocation record. */
-CONST int md_reloc_size = 8;
+const int md_reloc_size = 8;
/* 0: assemble for ARM,
1: assemble for Thumb,
struct arm_it
{
- CONST char * error;
+ const char * error;
unsigned long instruction;
int suffix;
int size;
#define NUM_FLOAT_VALS 8
-CONST char * fp_const[] =
+const char * fp_const[] =
{
"0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
};
#define CP_T_UD 0x00800000
#define CP_T_WB 0x00200000
-#define CONDS_BIT (0x00100000)
-#define LOAD_BIT (0x00100000)
-#define TRANS_BIT (0x00200000)
+#define CONDS_BIT 0x00100000
+#define LOAD_BIT 0x00100000
+#define TRANS_BIT 0x00200000
+
+#define DOUBLE_LOAD_FLAG 0x00000001
struct asm_cond
{
- CONST char * template;
+ const char * template;
unsigned long value;
};
/* This is to save a hash look-up in the common case. */
#define COND_ALWAYS 0xe0000000
-static CONST struct asm_cond conds[] =
+static const struct asm_cond conds[] =
{
{"eq", 0x00000000},
{"ne", 0x10000000},
the set_bits: */
struct asm_flg
{
- CONST char * template; /* Basic flag string. */
+ const char * template; /* Basic flag string. */
unsigned long set_bits; /* Bits to set. */
};
-static CONST struct asm_flg s_flag[] =
+static const struct asm_flg s_flag[] =
{
{"s", CONDS_BIT},
{NULL, 0}
};
-static CONST struct asm_flg ldr_flags[] =
+static const struct asm_flg ldr_flags[] =
{
+ {"d", DOUBLE_LOAD_FLAG},
{"b", 0x00400000},
{"t", TRANS_BIT},
{"bt", 0x00400000 | TRANS_BIT},
{NULL, 0}
};
-static CONST struct asm_flg str_flags[] =
+static const struct asm_flg str_flags[] =
{
+ {"d", DOUBLE_LOAD_FLAG},
{"b", 0x00400000},
{"t", TRANS_BIT},
{"bt", 0x00400000 | TRANS_BIT},
{NULL, 0}
};
-static CONST struct asm_flg byte_flag[] =
+static const struct asm_flg byte_flag[] =
{
{"b", 0x00400000},
{NULL, 0}
};
-static CONST struct asm_flg cmp_flags[] =
+static const struct asm_flg cmp_flags[] =
{
{"s", CONDS_BIT},
{"p", 0x0010f000},
{NULL, 0}
};
-static CONST struct asm_flg ldm_flags[] =
+static const struct asm_flg ldm_flags[] =
{
{"ed", 0x01800000},
{"fd", 0x00800000},
{"ea", 0x01000000},
- {"fa", 0x08000000},
+ {"fa", 0x00000000},
{"ib", 0x01800000},
{"ia", 0x00800000},
{"db", 0x01000000},
- {"da", 0x08000000},
+ {"da", 0x00000000},
{NULL, 0}
};
-static CONST struct asm_flg stm_flags[] =
+static const struct asm_flg stm_flags[] =
{
- {"ed", 0x08000000},
+ {"ed", 0x00000000},
{"fd", 0x01000000},
{"ea", 0x00800000},
{"fa", 0x01800000},
{"ib", 0x01800000},
{"ia", 0x00800000},
{"db", 0x01000000},
- {"da", 0x08000000},
+ {"da", 0x00000000},
{NULL, 0}
};
-static CONST struct asm_flg lfm_flags[] =
+static const struct asm_flg lfm_flags[] =
{
{"fd", 0x00800000},
{"ea", 0x01000000},
{NULL, 0}
};
-static CONST struct asm_flg sfm_flags[] =
+static const struct asm_flg sfm_flags[] =
{
{"fd", 0x01000000},
{"ea", 0x00800000},
{NULL, 0}
};
-static CONST struct asm_flg round_flags[] =
+static const struct asm_flg round_flags[] =
{
{"p", 0x00000020},
{"m", 0x00000040},
in that it accepts a precision specifier as well as a rounding specifier,
despite the fact that this is meaningless. To be more compatible, we
accept it as well, though of course it does not set any bits. */
-static CONST struct asm_flg fix_flags[] =
+static const struct asm_flg fix_flags[] =
{
{"p", 0x00000020},
{"m", 0x00000040},
{NULL, 0}
};
-static CONST struct asm_flg except_flag[] =
+static const struct asm_flg except_flag[] =
{
{"e", 0x00400000},
{NULL, 0}
};
-static CONST struct asm_flg cplong_flag[] =
+static const struct asm_flg long_flag[] =
{
{"l", 0x00400000},
{NULL, 0}
struct asm_psr
{
- CONST char * template;
+ const char * template;
boolean cpsr;
unsigned long field;
};
#define PSR_s (1 << 2)
#define PSR_f (1 << 3)
-static CONST struct asm_psr psrs[] =
+static const struct asm_psr psrs[] =
{
{"CPSR", true, PSR_c | PSR_f},
{"CPSR_all", true, PSR_c | PSR_f},
{"SPSR_cxsf", false, PSR_c | PSR_x | PSR_s | PSR_f},
};
+enum cirrus_regtype
+ {
+ CIRRUS_REGTYPE_MVF = 1,
+ CIRRUS_REGTYPE_MVFX = 2,
+ CIRRUS_REGTYPE_MVD = 3,
+ CIRRUS_REGTYPE_MVDX = 4,
+ CIRRUS_REGTYPE_MVAX = 5,
+ CIRRUS_REGTYPE_DSPSC = 6,
+ CIRRUS_REGTYPE_ANY = 7
+ };
+
/* Functions called by parser. */
/* ARM instructions. */
static void do_arit PARAMS ((char *, unsigned long));
static void do_swi PARAMS ((char *, unsigned long));
/* Pseudo Op codes. */
static void do_adr PARAMS ((char *, unsigned long));
-static void do_adrl PARAMS ((char *, unsigned long));
static void do_nop PARAMS ((char *, unsigned long));
/* ARM 2. */
static void do_mul PARAMS ((char *, unsigned long));
/* ARM THUMB. */
static void do_bx PARAMS ((char *, unsigned long));
+/* ARM_EXT_XScale. */
+static void do_mia PARAMS ((char *, unsigned long));
+static void do_mar PARAMS ((char *, unsigned long));
+static void do_mra PARAMS ((char *, unsigned long));
+static void do_pld PARAMS ((char *, unsigned long));
+static void do_ldrd PARAMS ((char *, unsigned long));
+
+/* ARM_EXT_V5. */
+static void do_blx PARAMS ((char *, unsigned long));
+static void do_bkpt PARAMS ((char *, unsigned long));
+static void do_clz PARAMS ((char *, unsigned long));
+static void do_lstc2 PARAMS ((char *, unsigned long));
+static void do_cdp2 PARAMS ((char *, unsigned long));
+static void do_co_reg2 PARAMS ((char *, unsigned long));
+
+static void do_t_blx PARAMS ((char *));
+static void do_t_bkpt PARAMS ((char *));
+
+/* ARM_EXT_V5E. */
+static void do_smla PARAMS ((char *, unsigned long));
+static void do_smlal PARAMS ((char *, unsigned long));
+static void do_smul PARAMS ((char *, unsigned long));
+static void do_qadd PARAMS ((char *, unsigned long));
+static void do_co_reg2c PARAMS ((char *, unsigned long));
+
/* Coprocessor Instructions. */
static void do_cdp PARAMS ((char *, unsigned long));
static void do_lstc PARAMS ((char *, unsigned long));
static void do_fp_from_reg PARAMS ((char *, unsigned long));
static void do_fp_to_reg PARAMS ((char *, unsigned long));
+/* ARM_EXT_MAVERICK. */
+static void do_c_binops PARAMS ((char *, unsigned long, int));
+static void do_c_binops_1 PARAMS ((char *, unsigned long));
+static void do_c_binops_2 PARAMS ((char *, unsigned long));
+static void do_c_binops_3 PARAMS ((char *, unsigned long));
+static void do_c_triple PARAMS ((char *, unsigned long, int));
+static void do_c_triple_4 PARAMS ((char *, unsigned long));
+static void do_c_triple_5 PARAMS ((char *, unsigned long));
+static void do_c_quad PARAMS ((char *, unsigned long, int));
+static void do_c_quad_6 PARAMS ((char *, unsigned long));
+static void do_c_dspsc PARAMS ((char *, unsigned long, int));
+static void do_c_dspsc_1 PARAMS ((char *, unsigned long));
+static void do_c_dspsc_2 PARAMS ((char *, unsigned long));
+static void do_c_shift PARAMS ((char *, unsigned long, int));
+static void do_c_shift_1 PARAMS ((char *, unsigned long));
+static void do_c_shift_2 PARAMS ((char *, unsigned long));
+static void do_c_ldst PARAMS ((char *, unsigned long, int));
+static void do_c_ldst_1 PARAMS ((char *, unsigned long));
+static void do_c_ldst_2 PARAMS ((char *, unsigned long));
+static void do_c_ldst_3 PARAMS ((char *, unsigned long));
+static void do_c_ldst_4 PARAMS ((char *, unsigned long));
+static int cirrus_reg_required_here PARAMS ((char **, int, enum cirrus_regtype));
+static int cirrus_valid_reg PARAMS ((int, enum cirrus_regtype));
+static int cirrus_parse_offset PARAMS ((char **, int *));
+
static void fix_new_arm PARAMS ((fragS *, int, short, expressionS *, int, int));
static int arm_reg_parse PARAMS ((char **));
-static CONST struct asm_psr * arm_psr_parse PARAMS ((char **));
-static void symbol_locate PARAMS ((symbolS *, CONST char *, segT, valueT, fragS *));
+static const struct asm_psr * arm_psr_parse PARAMS ((char **));
+static void symbol_locate PARAMS ((symbolS *, const char *, segT, valueT, fragS *));
static int add_to_lit_pool PARAMS ((void));
static unsigned validate_immediate PARAMS ((unsigned));
static unsigned validate_immediate_twopart PARAMS ((unsigned int, unsigned int *));
static valueT md_chars_to_number PARAMS ((char *, int));
static void insert_reg_alias PARAMS ((char *, int));
static void output_inst PARAMS ((void));
+static int accum0_required_here PARAMS ((char **));
+static int ld_mode_required_here PARAMS ((char **));
+static void do_branch25 PARAMS ((char *, unsigned long));
+static symbolS * find_real_start PARAMS ((symbolS *));
#ifdef OBJ_ELF
static bfd_reloc_code_real_type arm_parse_reloc PARAMS ((void));
#endif
take 2: */
#define INSN_SIZE 4
-/* LONGEST_INST is the longest basic instruction name without conditions or
- flags. ARM7M has 4 of length 5. */
+/* LONGEST_INST is the longest basic instruction name without
+ conditions or flags. ARM7M has 4 of length 5. El Segundo
+ has one basic instruction name of length 7 (SMLALxy). */
+#define LONGEST_INST 10
-#define LONGEST_INST 5
+/* "INSN<cond> X,Y" where X:bit12, Y:bit16. */
+#define CIRRUS_MODE1 0x100c
+
+/* "INSN<cond> X,Y" where X:bit16, Y:bit12. */
+#define CIRRUS_MODE2 0x0c10
+
+/* "INSN<cond> X,Y" where X:0, Y:bit16. */
+#define CIRRUS_MODE3 0x1000
+
+/* "INSN<cond> X,Y,Z" where X:16, Y:0, Z:12. */
+#define CIRRUS_MODE4 0x0c0010
+
+/* "INSN<cond> X,Y,Z" where X:12, Y:16, Z:0. */
+#define CIRRUS_MODE5 0x00100c
+
+/* "INSN<cond> W,X,Y,Z" where W:5, X:12, Y:16, Z:0. */
+#define CIRRUS_MODE6 0x00100c05
struct asm_opcode
{
/* Basic string to match. */
- CONST char * template;
+ const char * template;
/* Basic instruction code. */
unsigned long value;
/* Compulsory suffix that must follow conds. If "", then the
instruction is not conditional and must have no suffix. */
- CONST char * comp_suffix;
+ const char * comp_suffix;
/* Bits to toggle if flag 'n' set. */
- CONST struct asm_flg * flags;
+ const struct asm_flg * flags;
/* Which CPU variants this exists for. */
unsigned long variants;
void (* parms) PARAMS ((char *, unsigned long));
};
-static CONST struct asm_opcode insns[] =
-{
+static const struct asm_opcode insns[] =
+{
+/* Intel XScale extensions to ARM V5 ISA. */
+ {"mia", 0x0e200010, NULL, NULL, ARM_EXT_XSCALE, do_mia},
+ {"miaph", 0x0e280010, NULL, NULL, ARM_EXT_XSCALE, do_mia},
+ {"miabb", 0x0e2c0010, NULL, NULL, ARM_EXT_XSCALE, do_mia},
+ {"miabt", 0x0e2d0010, NULL, NULL, ARM_EXT_XSCALE, do_mia},
+ {"miatb", 0x0e2e0010, NULL, NULL, ARM_EXT_XSCALE, do_mia},
+ {"miatt", 0x0e2f0010, NULL, NULL, ARM_EXT_XSCALE, do_mia},
+ {"mar", 0x0c400000, NULL, NULL, ARM_EXT_XSCALE, do_mar},
+ {"mra", 0x0c500000, NULL, NULL, ARM_EXT_XSCALE, do_mra},
+ {"pld", 0xf450f000, "", NULL, ARM_EXT_XSCALE, do_pld},
+ {"ldr", 0x000000d0, NULL, ldr_flags, ARM_ANY, do_ldrd},
+ {"str", 0x000000f0, NULL, str_flags, ARM_ANY, do_ldrd},
+
/* ARM Instructions. */
{"and", 0x00000000, NULL, s_flag, ARM_ANY, do_arit},
{"eor", 0x00200000, NULL, s_flag, ARM_ANY, do_arit},
#endif
/* Pseudo ops. */
- {"adr", 0x028f0000, NULL, NULL, ARM_ANY, do_adr},
- {"adrl", 0x028f0000, NULL, NULL, ARM_ANY, do_adrl},
+ {"adr", 0x028f0000, NULL, long_flag, ARM_ANY, do_adr},
{"nop", 0x01a00000, NULL, NULL, ARM_ANY, do_nop},
/* ARM 2 multiplies. */
handled by the PSR_xxx defines above. */
/* ARM 7M long multiplies - need signed/unsigned flags! */
- {"smull", 0x00c00090, NULL, s_flag, ARM_LONGMUL, do_mull},
- {"umull", 0x00800090, NULL, s_flag, ARM_LONGMUL, do_mull},
- {"smlal", 0x00e00090, NULL, s_flag, ARM_LONGMUL, do_mull},
- {"umlal", 0x00a00090, NULL, s_flag, ARM_LONGMUL, do_mull},
+ {"smull", 0x00c00090, NULL, s_flag, ARM_EXT_LONGMUL, do_mull},
+ {"umull", 0x00800090, NULL, s_flag, ARM_EXT_LONGMUL, do_mull},
+ {"smlal", 0x00e00090, NULL, s_flag, ARM_EXT_LONGMUL, do_mull},
+ {"umlal", 0x00a00090, NULL, s_flag, ARM_EXT_LONGMUL, do_mull},
/* ARM THUMB interworking. */
- {"bx", 0x012fff10, NULL, NULL, ARM_THUMB, do_bx},
+ {"bx", 0x012fff10, NULL, NULL, ARM_EXT_THUMB, do_bx},
/* Floating point instructions. */
{"wfs", 0x0e200110, NULL, NULL, FPU_ALL, do_fp_ctrl},
/* Generic copressor instructions. */
{"cdp", 0x0e000000, NULL, NULL, ARM_2UP, do_cdp},
- {"ldc", 0x0c100000, NULL, cplong_flag, ARM_2UP, do_lstc},
- {"stc", 0x0c000000, NULL, cplong_flag, ARM_2UP, do_lstc},
+ {"ldc", 0x0c100000, NULL, long_flag, ARM_2UP, do_lstc},
+ {"stc", 0x0c000000, NULL, long_flag, ARM_2UP, do_lstc},
{"mcr", 0x0e000010, NULL, NULL, ARM_2UP, do_co_reg},
{"mrc", 0x0e100010, NULL, NULL, ARM_2UP, do_co_reg},
+
+/* ARM ISA extension 5. */
+/* Note: blx is actually 2 opcodes, so the .value is set dynamically.
+ And it's sometimes conditional and sometimes not. */
+ {"blx", 0, NULL, NULL, ARM_EXT_V5, do_blx},
+ {"clz", 0x016f0f10, NULL, NULL, ARM_EXT_V5, do_clz},
+ {"bkpt", 0xe1200070, "", NULL, ARM_EXT_V5, do_bkpt},
+ {"ldc2", 0xfc100000, "", long_flag, ARM_EXT_V5, do_lstc2},
+ {"stc2", 0xfc000000, "", long_flag, ARM_EXT_V5, do_lstc2},
+ {"cdp2", 0xfe000000, "", NULL, ARM_EXT_V5, do_cdp2},
+ {"mcr2", 0xfe000010, "", NULL, ARM_EXT_V5, do_co_reg2},
+ {"mrc2", 0xfe100010, "", NULL, ARM_EXT_V5, do_co_reg2},
+
+/* ARM ISA extension 5E, El Segundo. */
+ {"smlabb", 0x01000080, NULL, NULL, ARM_EXT_V5E, do_smla},
+ {"smlatb", 0x010000a0, NULL, NULL, ARM_EXT_V5E, do_smla},
+ {"smlabt", 0x010000c0, NULL, NULL, ARM_EXT_V5E, do_smla},
+ {"smlatt", 0x010000e0, NULL, NULL, ARM_EXT_V5E, do_smla},
+
+ {"smlawb", 0x01200080, NULL, NULL, ARM_EXT_V5E, do_smla},
+ {"smlawt", 0x012000c0, NULL, NULL, ARM_EXT_V5E, do_smla},
+
+ {"smlalbb",0x01400080, NULL, NULL, ARM_EXT_V5E, do_smlal},
+ {"smlaltb",0x014000a0, NULL, NULL, ARM_EXT_V5E, do_smlal},
+ {"smlalbt",0x014000c0, NULL, NULL, ARM_EXT_V5E, do_smlal},
+ {"smlaltt",0x014000e0, NULL, NULL, ARM_EXT_V5E, do_smlal},
+
+ {"smulbb", 0x01600080, NULL, NULL, ARM_EXT_V5E, do_smul},
+ {"smultb", 0x016000a0, NULL, NULL, ARM_EXT_V5E, do_smul},
+ {"smulbt", 0x016000c0, NULL, NULL, ARM_EXT_V5E, do_smul},
+ {"smultt", 0x016000e0, NULL, NULL, ARM_EXT_V5E, do_smul},
+
+ {"smulwb", 0x012000a0, NULL, NULL, ARM_EXT_V5E, do_smul},
+ {"smulwt", 0x012000e0, NULL, NULL, ARM_EXT_V5E, do_smul},
+
+ {"qadd", 0x01000050, NULL, NULL, ARM_EXT_V5E, do_qadd},
+ {"qdadd", 0x01400050, NULL, NULL, ARM_EXT_V5E, do_qadd},
+ {"qsub", 0x01200050, NULL, NULL, ARM_EXT_V5E, do_qadd},
+ {"qdsub", 0x01600050, NULL, NULL, ARM_EXT_V5E, do_qadd},
+
+ {"mcrr", 0x0c400000, NULL, NULL, ARM_EXT_V5E, do_co_reg2c},
+ {"mrrc", 0x0c500000, NULL, NULL, ARM_EXT_V5E, do_co_reg2c},
+
+ /* Cirrus DSP instructions. */
+ {"cfldrs", 0x0c100400, NULL, NULL, ARM_EXT_MAVERICK, do_c_ldst_1},
+ {"cfldrd", 0x0c500400, NULL, NULL, ARM_EXT_MAVERICK, do_c_ldst_2},
+ {"cfldr32", 0x0c100500, NULL, NULL, ARM_EXT_MAVERICK, do_c_ldst_3},
+ {"cfldr64", 0x0c500500, NULL, NULL, ARM_EXT_MAVERICK, do_c_ldst_4},
+ {"cfstrs", 0x0c000400, NULL, NULL, ARM_EXT_MAVERICK, do_c_ldst_1},
+ {"cfstrd", 0x0c400400, NULL, NULL, ARM_EXT_MAVERICK, do_c_ldst_2},
+ {"cfstr32", 0x0c000500, NULL, NULL, ARM_EXT_MAVERICK, do_c_ldst_3},
+ {"cfstr64", 0x0c400500, NULL, NULL, ARM_EXT_MAVERICK, do_c_ldst_4},
+ {"cfmvsr", 0x0e000450, NULL, NULL, ARM_EXT_MAVERICK, do_c_binops_2},
+ {"cfmvrs", 0x0e100450, NULL, NULL, ARM_EXT_MAVERICK, do_c_binops_1},
+ {"cfmvdlr", 0x0e000410, NULL, NULL, ARM_EXT_MAVERICK, do_c_binops_2},
+ {"cfmvrdl", 0x0e100410, NULL, NULL, ARM_EXT_MAVERICK, do_c_binops_1},
+ {"cfmvdhr", 0x0e000430, NULL, NULL, ARM_EXT_MAVERICK, do_c_binops_2},
+ {"cfmvrdh", 0x0e100430, NULL, NULL, ARM_EXT_MAVERICK, do_c_binops_1},
+ {"cfmv64lr", 0x0e000510, NULL, NULL, ARM_EXT_MAVERICK, do_c_binops_2},
+ {"cfmvr64l", 0x0e100510, NULL, NULL, ARM_EXT_MAVERICK, do_c_binops_1},
+ {"cfmv64hr", 0x0e000530, NULL, NULL, ARM_EXT_MAVERICK, do_c_binops_2},
+ {"cfmvr64h", 0x0e100530, NULL, NULL, ARM_EXT_MAVERICK, do_c_binops_1},
+ {"cfmval32", 0x0e100610, NULL, NULL, ARM_EXT_MAVERICK, do_c_binops_3},
+ {"cfmv32al", 0x0e000610, NULL, NULL, ARM_EXT_MAVERICK, do_c_binops_3},
+ {"cfmvam32", 0x0e100630, NULL, NULL, ARM_EXT_MAVERICK, do_c_binops_3},
+ {"cfmv32am", 0x0e000630, NULL, NULL, ARM_EXT_MAVERICK, do_c_binops_3},
+ {"cfmvah32", 0x0e100650, NULL, NULL, ARM_EXT_MAVERICK, do_c_binops_3},
+ {"cfmv32ah", 0x0e000650, NULL, NULL, ARM_EXT_MAVERICK, do_c_binops_3},
+ {"cfmv32a", 0x0e000670, NULL, NULL, ARM_EXT_MAVERICK, do_c_binops_3},
+ {"cfmva32", 0x0e100670, NULL, NULL, ARM_EXT_MAVERICK, do_c_binops_3},
+ {"cfmv64a", 0x0e000690, NULL, NULL, ARM_EXT_MAVERICK, do_c_binops_3},
+ {"cfmva64", 0x0e100690, NULL, NULL, ARM_EXT_MAVERICK, do_c_binops_3},
+ {"cfmvsc32", 0x0e1006b0, NULL, NULL, ARM_EXT_MAVERICK, do_c_dspsc_1},
+ {"cfmv32sc", 0x0e0006b0, NULL, NULL, ARM_EXT_MAVERICK, do_c_dspsc_2},
+ {"cfcpys", 0x0e000400, NULL, NULL, ARM_EXT_MAVERICK, do_c_binops_1},
+ {"cfcpyd", 0x0e000420, NULL, NULL, ARM_EXT_MAVERICK, do_c_binops_1},
+ {"cfcvtsd", 0x0e000460, NULL, NULL, ARM_EXT_MAVERICK, do_c_binops_1},
+ {"cfcvtds", 0x0e000440, NULL, NULL, ARM_EXT_MAVERICK, do_c_binops_1},
+ {"cfcvt32s", 0x0e000480, NULL, NULL, ARM_EXT_MAVERICK, do_c_binops_1},
+ {"cfcvt32d", 0x0e0004a0, NULL, NULL, ARM_EXT_MAVERICK, do_c_binops_1},
+ {"cfcvt64s", 0x0e0004c0, NULL, NULL, ARM_EXT_MAVERICK, do_c_binops_1},
+ {"cfcvt64d", 0x0e0004e0, NULL, NULL, ARM_EXT_MAVERICK, do_c_binops_1},
+ {"cfcvts32", 0x0e100580, NULL, NULL, ARM_EXT_MAVERICK, do_c_binops_1},
+ {"cfcvtd32", 0x0e1005a0, NULL, NULL, ARM_EXT_MAVERICK, do_c_binops_1},
+ {"cftruncs32",0x0e1005c0, NULL, NULL, ARM_EXT_MAVERICK, do_c_binops_1},
+ {"cftruncd32",0x0e1005e0, NULL, NULL, ARM_EXT_MAVERICK, do_c_binops_1},
+ {"cfrshl32", 0x0e000550, NULL, NULL, ARM_EXT_MAVERICK, do_c_triple_4},
+ {"cfrshl64", 0x0e000570, NULL, NULL, ARM_EXT_MAVERICK, do_c_triple_4},
+ {"cfsh32", 0x0e000500, NULL, NULL, ARM_EXT_MAVERICK, do_c_shift_1},
+ {"cfsh64", 0x0e200500, NULL, NULL, ARM_EXT_MAVERICK, do_c_shift_2},
+ {"cfcmps", 0x0e100490, NULL, NULL, ARM_EXT_MAVERICK, do_c_triple_5},
+ {"cfcmpd", 0x0e1004b0, NULL, NULL, ARM_EXT_MAVERICK, do_c_triple_5},
+ {"cfcmp32", 0x0e100590, NULL, NULL, ARM_EXT_MAVERICK, do_c_triple_5},
+ {"cfcmp64", 0x0e1005b0, NULL, NULL, ARM_EXT_MAVERICK, do_c_triple_5},
+ {"cfabss", 0x0e300400, NULL, NULL, ARM_EXT_MAVERICK, do_c_binops_1},
+ {"cfabsd", 0x0e300420, NULL, NULL, ARM_EXT_MAVERICK, do_c_binops_1},
+ {"cfnegs", 0x0e300440, NULL, NULL, ARM_EXT_MAVERICK, do_c_binops_1},
+ {"cfnegd", 0x0e300460, NULL, NULL, ARM_EXT_MAVERICK, do_c_binops_1},
+ {"cfadds", 0x0e300480, NULL, NULL, ARM_EXT_MAVERICK, do_c_triple_5},
+ {"cfaddd", 0x0e3004a0, NULL, NULL, ARM_EXT_MAVERICK, do_c_triple_5},
+ {"cfsubs", 0x0e3004c0, NULL, NULL, ARM_EXT_MAVERICK, do_c_triple_5},
+ {"cfsubd", 0x0e3004e0, NULL, NULL, ARM_EXT_MAVERICK, do_c_triple_5},
+ {"cfmuls", 0x0e100400, NULL, NULL, ARM_EXT_MAVERICK, do_c_triple_5},
+ {"cfmuld", 0x0e100420, NULL, NULL, ARM_EXT_MAVERICK, do_c_triple_5},
+ {"cfabs32", 0x0e300500, NULL, NULL, ARM_EXT_MAVERICK, do_c_binops_1},
+ {"cfabs64", 0x0e300520, NULL, NULL, ARM_EXT_MAVERICK, do_c_binops_1},
+ {"cfneg32", 0x0e300540, NULL, NULL, ARM_EXT_MAVERICK, do_c_binops_1},
+ {"cfneg64", 0x0e300560, NULL, NULL, ARM_EXT_MAVERICK, do_c_binops_1},
+ {"cfadd32", 0x0e300580, NULL, NULL, ARM_EXT_MAVERICK, do_c_triple_5},
+ {"cfadd64", 0x0e3005a0, NULL, NULL, ARM_EXT_MAVERICK, do_c_triple_5},
+ {"cfsub32", 0x0e3005c0, NULL, NULL, ARM_EXT_MAVERICK, do_c_triple_5},
+ {"cfsub64", 0x0e3005e0, NULL, NULL, ARM_EXT_MAVERICK, do_c_triple_5},
+ {"cfmul32", 0x0e100500, NULL, NULL, ARM_EXT_MAVERICK, do_c_triple_5},
+ {"cfmul64", 0x0e100520, NULL, NULL, ARM_EXT_MAVERICK, do_c_triple_5},
+ {"cfmac32", 0x0e100540, NULL, NULL, ARM_EXT_MAVERICK, do_c_triple_5},
+ {"cfmsc32", 0x0e100560, NULL, NULL, ARM_EXT_MAVERICK, do_c_triple_5},
+ {"cfmadd32", 0x0e000600, NULL, NULL, ARM_EXT_MAVERICK, do_c_quad_6},
+ {"cfmsub32", 0x0e100600, NULL, NULL, ARM_EXT_MAVERICK, do_c_quad_6},
+ {"cfmadda32", 0x0e200600, NULL, NULL, ARM_EXT_MAVERICK, do_c_quad_6},
+ {"cfmsuba32", 0x0e300600, NULL, NULL, ARM_EXT_MAVERICK, do_c_quad_6},
};
/* Defines for various bits that we will want to toggle. */
struct thumb_opcode
{
/* Basic string to match. */
- CONST char * template;
+ const char * template;
/* Basic instruction code. */
unsigned long value;
void (* parms) PARAMS ((char *));
};
-static CONST struct thumb_opcode tinsns[] =
-{
- {"adc", 0x4140, 2, ARM_THUMB, do_t_arit},
- {"add", 0x0000, 2, ARM_THUMB, do_t_add},
- {"and", 0x4000, 2, ARM_THUMB, do_t_arit},
- {"asr", 0x0000, 2, ARM_THUMB, do_t_asr},
- {"b", T_OPCODE_BRANCH, 2, ARM_THUMB, do_t_branch12},
- {"beq", 0xd0fe, 2, ARM_THUMB, do_t_branch9},
- {"bne", 0xd1fe, 2, ARM_THUMB, do_t_branch9},
- {"bcs", 0xd2fe, 2, ARM_THUMB, do_t_branch9},
- {"bhs", 0xd2fe, 2, ARM_THUMB, do_t_branch9},
- {"bcc", 0xd3fe, 2, ARM_THUMB, do_t_branch9},
- {"bul", 0xd3fe, 2, ARM_THUMB, do_t_branch9},
- {"blo", 0xd3fe, 2, ARM_THUMB, do_t_branch9},
- {"bmi", 0xd4fe, 2, ARM_THUMB, do_t_branch9},
- {"bpl", 0xd5fe, 2, ARM_THUMB, do_t_branch9},
- {"bvs", 0xd6fe, 2, ARM_THUMB, do_t_branch9},
- {"bvc", 0xd7fe, 2, ARM_THUMB, do_t_branch9},
- {"bhi", 0xd8fe, 2, ARM_THUMB, do_t_branch9},
- {"bls", 0xd9fe, 2, ARM_THUMB, do_t_branch9},
- {"bge", 0xdafe, 2, ARM_THUMB, do_t_branch9},
- {"blt", 0xdbfe, 2, ARM_THUMB, do_t_branch9},
- {"bgt", 0xdcfe, 2, ARM_THUMB, do_t_branch9},
- {"ble", 0xddfe, 2, ARM_THUMB, do_t_branch9},
- {"bal", 0xdefe, 2, ARM_THUMB, do_t_branch9},
- {"bic", 0x4380, 2, ARM_THUMB, do_t_arit},
- {"bl", 0xf7fffffe, 4, ARM_THUMB, do_t_branch23},
- {"bx", 0x4700, 2, ARM_THUMB, do_t_bx},
- {"cmn", T_OPCODE_CMN, 2, ARM_THUMB, do_t_arit},
- {"cmp", 0x0000, 2, ARM_THUMB, do_t_compare},
- {"eor", 0x4040, 2, ARM_THUMB, do_t_arit},
- {"ldmia", 0xc800, 2, ARM_THUMB, do_t_ldmstm},
- {"ldr", 0x0000, 2, ARM_THUMB, do_t_ldr},
- {"ldrb", 0x0000, 2, ARM_THUMB, do_t_ldrb},
- {"ldrh", 0x0000, 2, ARM_THUMB, do_t_ldrh},
- {"ldrsb", 0x5600, 2, ARM_THUMB, do_t_lds},
- {"ldrsh", 0x5e00, 2, ARM_THUMB, do_t_lds},
- {"ldsb", 0x5600, 2, ARM_THUMB, do_t_lds},
- {"ldsh", 0x5e00, 2, ARM_THUMB, do_t_lds},
- {"lsl", 0x0000, 2, ARM_THUMB, do_t_lsl},
- {"lsr", 0x0000, 2, ARM_THUMB, do_t_lsr},
- {"mov", 0x0000, 2, ARM_THUMB, do_t_mov},
- {"mul", T_OPCODE_MUL, 2, ARM_THUMB, do_t_arit},
- {"mvn", T_OPCODE_MVN, 2, ARM_THUMB, do_t_arit},
- {"neg", T_OPCODE_NEG, 2, ARM_THUMB, do_t_arit},
- {"orr", 0x4300, 2, ARM_THUMB, do_t_arit},
- {"pop", 0xbc00, 2, ARM_THUMB, do_t_push_pop},
- {"push", 0xb400, 2, ARM_THUMB, do_t_push_pop},
- {"ror", 0x41c0, 2, ARM_THUMB, do_t_arit},
- {"sbc", 0x4180, 2, ARM_THUMB, do_t_arit},
- {"stmia", 0xc000, 2, ARM_THUMB, do_t_ldmstm},
- {"str", 0x0000, 2, ARM_THUMB, do_t_str},
- {"strb", 0x0000, 2, ARM_THUMB, do_t_strb},
- {"strh", 0x0000, 2, ARM_THUMB, do_t_strh},
- {"swi", 0xdf00, 2, ARM_THUMB, do_t_swi},
- {"sub", 0x0000, 2, ARM_THUMB, do_t_sub},
- {"tst", T_OPCODE_TST, 2, ARM_THUMB, do_t_arit},
+static const struct thumb_opcode tinsns[] =
+{
+ {"adc", 0x4140, 2, ARM_EXT_THUMB, do_t_arit},
+ {"add", 0x0000, 2, ARM_EXT_THUMB, do_t_add},
+ {"and", 0x4000, 2, ARM_EXT_THUMB, do_t_arit},
+ {"asr", 0x0000, 2, ARM_EXT_THUMB, do_t_asr},
+ {"b", T_OPCODE_BRANCH, 2, ARM_EXT_THUMB, do_t_branch12},
+ {"beq", 0xd0fe, 2, ARM_EXT_THUMB, do_t_branch9},
+ {"bne", 0xd1fe, 2, ARM_EXT_THUMB, do_t_branch9},
+ {"bcs", 0xd2fe, 2, ARM_EXT_THUMB, do_t_branch9},
+ {"bhs", 0xd2fe, 2, ARM_EXT_THUMB, do_t_branch9},
+ {"bcc", 0xd3fe, 2, ARM_EXT_THUMB, do_t_branch9},
+ {"bul", 0xd3fe, 2, ARM_EXT_THUMB, do_t_branch9},
+ {"blo", 0xd3fe, 2, ARM_EXT_THUMB, do_t_branch9},
+ {"bmi", 0xd4fe, 2, ARM_EXT_THUMB, do_t_branch9},
+ {"bpl", 0xd5fe, 2, ARM_EXT_THUMB, do_t_branch9},
+ {"bvs", 0xd6fe, 2, ARM_EXT_THUMB, do_t_branch9},
+ {"bvc", 0xd7fe, 2, ARM_EXT_THUMB, do_t_branch9},
+ {"bhi", 0xd8fe, 2, ARM_EXT_THUMB, do_t_branch9},
+ {"bls", 0xd9fe, 2, ARM_EXT_THUMB, do_t_branch9},
+ {"bge", 0xdafe, 2, ARM_EXT_THUMB, do_t_branch9},
+ {"blt", 0xdbfe, 2, ARM_EXT_THUMB, do_t_branch9},
+ {"bgt", 0xdcfe, 2, ARM_EXT_THUMB, do_t_branch9},
+ {"ble", 0xddfe, 2, ARM_EXT_THUMB, do_t_branch9},
+ {"bal", 0xdefe, 2, ARM_EXT_THUMB, do_t_branch9},
+ {"bic", 0x4380, 2, ARM_EXT_THUMB, do_t_arit},
+ {"bl", 0xf7fffffe, 4, ARM_EXT_THUMB, do_t_branch23},
+ {"blx", 0, 0, ARM_EXT_V5, do_t_blx},
+ {"bkpt", 0xbe00, 2, ARM_EXT_V5, do_t_bkpt},
+ {"bx", 0x4700, 2, ARM_EXT_THUMB, do_t_bx},
+ {"cmn", T_OPCODE_CMN, 2, ARM_EXT_THUMB, do_t_arit},
+ {"cmp", 0x0000, 2, ARM_EXT_THUMB, do_t_compare},
+ {"eor", 0x4040, 2, ARM_EXT_THUMB, do_t_arit},
+ {"ldmia", 0xc800, 2, ARM_EXT_THUMB, do_t_ldmstm},
+ {"ldr", 0x0000, 2, ARM_EXT_THUMB, do_t_ldr},
+ {"ldrb", 0x0000, 2, ARM_EXT_THUMB, do_t_ldrb},
+ {"ldrh", 0x0000, 2, ARM_EXT_THUMB, do_t_ldrh},
+ {"ldrsb", 0x5600, 2, ARM_EXT_THUMB, do_t_lds},
+ {"ldrsh", 0x5e00, 2, ARM_EXT_THUMB, do_t_lds},
+ {"ldsb", 0x5600, 2, ARM_EXT_THUMB, do_t_lds},
+ {"ldsh", 0x5e00, 2, ARM_EXT_THUMB, do_t_lds},
+ {"lsl", 0x0000, 2, ARM_EXT_THUMB, do_t_lsl},
+ {"lsr", 0x0000, 2, ARM_EXT_THUMB, do_t_lsr},
+ {"mov", 0x0000, 2, ARM_EXT_THUMB, do_t_mov},
+ {"mul", T_OPCODE_MUL, 2, ARM_EXT_THUMB, do_t_arit},
+ {"mvn", T_OPCODE_MVN, 2, ARM_EXT_THUMB, do_t_arit},
+ {"neg", T_OPCODE_NEG, 2, ARM_EXT_THUMB, do_t_arit},
+ {"orr", 0x4300, 2, ARM_EXT_THUMB, do_t_arit},
+ {"pop", 0xbc00, 2, ARM_EXT_THUMB, do_t_push_pop},
+ {"push", 0xb400, 2, ARM_EXT_THUMB, do_t_push_pop},
+ {"ror", 0x41c0, 2, ARM_EXT_THUMB, do_t_arit},
+ {"sbc", 0x4180, 2, ARM_EXT_THUMB, do_t_arit},
+ {"stmia", 0xc000, 2, ARM_EXT_THUMB, do_t_ldmstm},
+ {"str", 0x0000, 2, ARM_EXT_THUMB, do_t_str},
+ {"strb", 0x0000, 2, ARM_EXT_THUMB, do_t_strb},
+ {"strh", 0x0000, 2, ARM_EXT_THUMB, do_t_strh},
+ {"swi", 0xdf00, 2, ARM_EXT_THUMB, do_t_swi},
+ {"sub", 0x0000, 2, ARM_EXT_THUMB, do_t_sub},
+ {"tst", T_OPCODE_TST, 2, ARM_EXT_THUMB, do_t_arit},
/* Pseudo ops: */
- {"adr", 0x0000, 2, ARM_THUMB, do_t_adr},
- {"nop", 0x46C0, 2, ARM_THUMB, do_t_nop}, /* mov r8,r8 */
+ {"adr", 0x0000, 2, ARM_EXT_THUMB, do_t_adr},
+ {"nop", 0x46C0, 2, ARM_EXT_THUMB, do_t_nop}, /* mov r8,r8 */
};
struct reg_entry
{
- CONST char * name;
+ const char * name;
int number;
};
#define cp_register(reg) ((reg) >= 32 && (reg) <= 47)
#define fp_register(reg) ((reg) >= 16 && (reg) <= 23)
+#define ARM_EXT_MAVERICKSC_REG 134
+
+#define cirrus_register(reg) ((reg) >= 50 && (reg) <= 134)
+#define cirrus_mvf_register(reg) ((reg) >= 50 && (reg) <= 65)
+#define cirrus_mvd_register(reg) ((reg) >= 70 && (reg) <= 85)
+#define cirrus_mvfx_register(reg) ((reg) >= 90 && (reg) <= 105)
+#define cirrus_mvdx_register(reg) ((reg) >= 110 && (reg) <= 125)
+#define cirrus_mvax_register(reg) ((reg) >= 130 && (reg) <= 133)
+#define ARM_EXT_MAVERICKsc_register(reg) ((reg) == ARM_EXT_MAVERICKSC_REG)
+
#define REG_PC 15
#define REG_LR 14
#define REG_SP 13
/* These are the standard names. Users can add aliases with .req. */
-static CONST struct reg_entry reg_table[] =
+static const struct reg_entry reg_table[] =
{
/* Processor Register Numbers. */
{"r0", 0}, {"r1", 1}, {"r2", 2}, {"r3", 3},
{"s4",20}, {"s5",21}, {"s6",22}, {"s7",23},
{"d0",16}, {"d1",17}, {"d2",18}, {"d3",19},
{"d4",20}, {"d5",21}, {"d6",22}, {"d7",23},
+ /* Cirrus DSP coprocessor registers. */
+ {"mvf0", 50}, {"mvf1", 51}, {"mvf2", 52}, {"mvf3", 53},
+ {"mvf4", 54}, {"mvf5", 55}, {"mvf6", 56}, {"mvf7", 57},
+ {"mvf8", 58}, {"mvf9", 59}, {"mvf10", 60}, {"mvf11", 61},
+ {"mvf12", 62},{"mvf13", 63}, {"mvf14", 64}, {"mvf15", 65},
+ {"mvd0", 70}, {"mvd1", 71}, {"mvd2", 72}, {"mvd3", 73},
+ {"mvd4", 74}, {"mvd5", 75}, {"mvd6", 76}, {"mvd7", 77},
+ {"mvd8", 78}, {"mvd9", 79}, {"mvd10", 80}, {"mvd11", 81},
+ {"mvd12", 82},{"mvd13", 83}, {"mvd14", 84}, {"mvd15", 85},
+ {"mvfx0", 90},{"mvfx1", 91}, {"mvfx2", 92}, {"mvfx3", 93},
+ {"mvfx4", 94},{"mvfx5", 95}, {"mvfx6", 96}, {"mvfx7", 97},
+ {"mvfx8", 98},{"mvfx9", 99}, {"mvfx10", 100},{"mvfx11", 101},
+ {"mvfx12", 102},{"mvfx13", 103},{"mvfx14", 104},{"mvfx15", 105},
+ {"mvdx0", 110}, {"mvdx1", 111}, {"mvdx2", 112}, {"mvdx3", 113},
+ {"mvdx4", 114}, {"mvdx5", 115}, {"mvdx6", 116}, {"mvdx7", 117},
+ {"mvdx8", 118}, {"mvdx9", 119}, {"mvdx10", 120},{"mvdx11", 121},
+ {"mvdx12", 122},{"mvdx13", 123},{"mvdx14", 124},{"mvdx15", 125},
+ {"mvax0", 130}, {"mvax1", 131}, {"mvax2", 132}, {"mvax3", 133},
+ {"dspsc", ARM_EXT_MAVERICKSC_REG},
/* FIXME: At some point we need to add VFP register names. */
/* Array terminator. */
{NULL, 0}
#define BAD_PC _("r15 not allowed here")
#define BAD_FLAGS _("Instruction should not have flags")
#define BAD_COND _("Instruction is not conditional")
+#define ERR_NO_ACCUM _("acc0 expected")
static struct hash_control * arm_ops_hsh = NULL;
static struct hash_control * arm_tops_hsh = NULL;
static int my_get_expression PARAMS ((expressionS *, char **));
-CONST pseudo_typeS md_pseudo_table[] =
+const pseudo_typeS md_pseudo_table[] =
{
/* Never called becasue '.req' does not start line. */
{ "req", s_req, 0 },
== inst.reloc.exp.X_add_number)
&& literals[lit_count].exp.X_unsigned == inst.reloc.exp.X_unsigned)
break;
+
+ if (literals[lit_count].exp.X_op == inst.reloc.exp.X_op
+ && inst.reloc.exp.X_op == O_symbol
+ && (literals[lit_count].exp.X_add_number
+ == inst.reloc.exp.X_add_number)
+ && (literals[lit_count].exp.X_add_symbol
+ == inst.reloc.exp.X_add_symbol)
+ && (literals[lit_count].exp.X_op_symbol
+ == inst.reloc.exp.X_op_symbol))
+ break;
+
lit_count++;
}
if (lit_count == next_literal_pool_place) /* New entry. */
{
- if (next_literal_pool_place > MAX_LITERAL_POOL_SIZE)
+ if (next_literal_pool_place >= MAX_LITERAL_POOL_SIZE)
{
inst.error = _("Literal Pool Overflow");
return FAIL;
static void
symbol_locate (symbolP, name, segment, valu, frag)
symbolS * symbolP;
- CONST char * name; /* It is copied, the caller can modify. */
+ const char * name; /* It is copied, the caller can modify. */
segT segment; /* Segment identifier (SEG_<something>). */
valueT valu; /* Symbol value. */
fragS * frag; /* Associated fragment. */
case 16:
if (! thumb_mode)
{
- if (! (cpu_variant & ARM_THUMB))
+ if (! (cpu_variant & ARM_EXT_THUMB))
as_bad (_("selected processor does not support THUMB opcodes"));
thumb_mode = 1;
case 32:
if (thumb_mode)
{
- if ((cpu_variant & ARM_ANY) == ARM_THUMB)
+ if ((cpu_variant & ARM_ANY) == ARM_EXT_THUMB)
as_bad (_("selected processor does not support ARM opcodes"));
thumb_mode = 0;
return FAIL;
}
-static CONST struct asm_psr *
+static const struct asm_psr *
arm_psr_parse (ccp)
register char ** ccp;
{
char * start = * ccp;
char c;
char * p;
- CONST struct asm_psr * psr;
+ const struct asm_psr * psr;
p = start;
{
c = *p++;
}
- while (isalpha (c) || c == '_');
+ while (ISALPHA (c) || c == '_');
/* Terminate the word. */
*--p = 0;
strncpy (start, "SPSR", 4);
/* Now locate the word in the psr hash table. */
- psr = (CONST struct asm_psr *) hash_find (arm_psr_hsh, start);
+ psr = (const struct asm_psr *) hash_find (arm_psr_hsh, start);
/* Restore the input stream. */
*p = c;
char ** str;
{
char * start = * str;
- CONST struct asm_psr * psr;
+ const struct asm_psr * psr;
psr = arm_psr_parse (str);
return;
}
- if (inst.instruction & ((PSR_c | PSR_x | PSR_s) << PSR_SHIFT))
+#if 0 /* The first edition of the ARM architecture manual stated that
+ writing anything other than the flags with an immediate operation
+ had UNPREDICTABLE effects. This constraint was removed in the
+ second edition of the specification. */
+ if ((cpu_variant & ARM_EXT_V5) != ARM_EXT_V5
+ && inst.instruction & ((PSR_c | PSR_x | PSR_s) << PSR_SHIFT))
{
- inst.error = _("only flag field of psr can be set with immediate value");
+ inst.error = _("immediate value cannot be used to set this field");
return;
}
+#endif
flags |= INST_IMMEDIATE;
return;
}
-/* Returns the index into fp_values of a floating point number,
- or -1 if not in the table. */
+/* Expects *str -> the characters "acc0", possibly with leading blanks.
+ Advances *str to the next non-alphanumeric.
+ Returns 0, or else FAIL (in which case sets inst.error).
+
+ (In a future XScale, there may be accumulators other than zero.
+ At that time this routine and its callers can be upgraded to suit.) */
static int
-my_get_float_expression (str)
+accum0_required_here (str)
char ** str;
{
- LITTLENUM_TYPE words[MAX_LITTLENUMS];
- char * save_in;
- expressionS exp;
- int i;
- int j;
+ static char buff [128]; /* Note the address is taken. Hence, static. */
+ char * p = * str;
+ char c;
+ int result = 0; /* The accum number. */
- memset (words, 0, MAX_LITTLENUMS * sizeof (LITTLENUM_TYPE));
+ skip_whitespace (p);
- /* Look for a raw floating point number. */
- if ((save_in = atof_ieee (*str, 'x', words)) != NULL
- && is_end_of_line[(unsigned char) *save_in])
+ *str = p; /* Advance caller's string pointer too. */
+ c = *p++;
+ while (ISALNUM (c))
+ c = *p++;
+
+ *--p = 0; /* Aap nul into input buffer at non-alnum. */
+
+ if (! ( streq (*str, "acc0") || streq (*str, "ACC0")))
{
- for (i = 0; i < NUM_FLOAT_VALS; i++)
+ sprintf (buff, _("acc0 expected, not '%.100s'"), *str);
+ inst.error = buff;
+ result = FAIL;
+ }
+
+ *p = c; /* Unzap. */
+ *str = p; /* Caller's string pointer to after match. */
+ return result;
+}
+
+/* Expects **str -> after a comma. May be leading blanks.
+ Advances *str, recognizing a load mode, and setting inst.instruction.
+ Returns rn, or else FAIL (in which case may set inst.error
+ and not advance str)
+
+ Note: doesn't know Rd, so no err checks that require such knowledge. */
+
+static int
+ld_mode_required_here (string)
+ char ** string;
+{
+ char * str = * string;
+ int rn;
+ int pre_inc = 0;
+
+ skip_whitespace (str);
+
+ if (* str == '[')
+ {
+ str++;
+
+ skip_whitespace (str);
+
+ if ((rn = reg_required_here (& str, 16)) == FAIL)
+ return FAIL;
+
+ skip_whitespace (str);
+
+ if (* str == ']')
{
- for (j = 0; j < MAX_LITTLENUMS; j++)
+ str ++;
+
+ if (skip_past_comma (& str) == SUCCESS)
{
- if (words[j] != fp_values[i][j])
- break;
+ /* [Rn],... (post inc) */
+ if (ldst_extend (& str, 1) == FAIL)
+ return FAIL;
}
-
- if (j == MAX_LITTLENUMS)
+ else /* [Rn] */
{
- *str = save_in;
- return i;
+ skip_whitespace (str);
+
+ if (* str == '!')
+ {
+ str ++;
+ inst.instruction |= WRITE_BACK;
+ }
+
+ inst.instruction |= INDEX_UP | HWOFFSET_IMM;
+ pre_inc = 1;
}
}
- }
-
- /* Try and parse a more complex expression, this will probably fail
- unless the code uses a floating point prefix (eg "0f"). */
- save_in = input_line_pointer;
- input_line_pointer = *str;
- if (expression (&exp) == absolute_section
- && exp.X_op == O_big
- && exp.X_add_number < 0)
- {
- /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
- Ditto for 15. */
- if (gen_to_words (words, 5, (long) 15) == 0)
+ else /* [Rn,...] */
{
- for (i = 0; i < NUM_FLOAT_VALS; i++)
+ if (skip_past_comma (& str) == FAIL)
{
- for (j = 0; j < MAX_LITTLENUMS; j++)
- {
- if (words[j] != fp_values[i][j])
- break;
- }
+ inst.error = _("pre-indexed expression expected");
+ return FAIL;
+ }
- if (j == MAX_LITTLENUMS)
- {
- *str = input_line_pointer;
- input_line_pointer = save_in;
- return i;
- }
+ pre_inc = 1;
+
+ if (ldst_extend (& str, 1) == FAIL)
+ return FAIL;
+
+ skip_whitespace (str);
+
+ if (* str ++ != ']')
+ {
+ inst.error = _("missing ]");
+ return FAIL;
+ }
+
+ skip_whitespace (str);
+
+ if (* str == '!')
+ {
+ str ++;
+ inst.instruction |= WRITE_BACK;
}
}
}
+ else if (* str == '=') /* ldr's "r,=label" syntax */
+ /* We should never reach here, because <text> = <expression> is
+ caught gas/read.c read_a_source_file() as a .set operation. */
+ return FAIL;
+ else /* PC +- 8 bit immediate offset. */
+ {
+ if (my_get_expression (& inst.reloc.exp, & str))
+ return FAIL;
- *str = input_line_pointer;
- input_line_pointer = save_in;
- return -1;
+ inst.instruction |= HWOFFSET_IMM; /* The I bit. */
+ inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM8;
+ inst.reloc.exp.X_add_number -= 8; /* PC rel adjust. */
+ inst.reloc.pc_rel = 1;
+ inst.instruction |= (REG_PC << 16);
+
+ rn = REG_PC;
+ pre_inc = 1;
+ }
+
+ inst.instruction |= (pre_inc ? PRE_INDEX : 0);
+ * string = str;
+
+ return rn;
}
-/* Return true if anything in the expression is a bignum. */
+/* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
+ SMLAxy{cond} Rd,Rm,Rs,Rn
+ SMLAWy{cond} Rd,Rm,Rs,Rn
+ Error if any register is R15. */
-static int
-walk_no_bignums (sp)
- symbolS * sp;
+static void
+do_smla (str, flags)
+ char * str;
+ unsigned long flags;
{
- if (symbol_get_value_expression (sp)->X_op == O_big)
- return 1;
+ int rd, rm, rs, rn;
- if (symbol_get_value_expression (sp)->X_add_symbol)
- {
- return (walk_no_bignums (symbol_get_value_expression (sp)->X_add_symbol)
- || (symbol_get_value_expression (sp)->X_op_symbol
- && walk_no_bignums (symbol_get_value_expression (sp)->X_op_symbol)));
- }
+ skip_whitespace (str);
- return 0;
+ if ((rd = reg_required_here (& str, 16)) == FAIL
+ || skip_past_comma (& str) == FAIL
+ || (rm = reg_required_here (& str, 0)) == FAIL
+ || skip_past_comma (& str) == FAIL
+ || (rs = reg_required_here (& str, 8)) == FAIL
+ || skip_past_comma (& str) == FAIL
+ || (rn = reg_required_here (& str, 12)) == FAIL)
+ inst.error = BAD_ARGS;
+
+ else if (rd == REG_PC || rm == REG_PC || rs == REG_PC || rn == REG_PC)
+ inst.error = BAD_PC;
+
+ else if (flags)
+ inst.error = BAD_FLAGS;
+
+ else
+ end_of_line (str);
}
-static int
-my_get_expression (ep, str)
- expressionS * ep;
- char ** str;
+/* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
+ SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
+ Error if any register is R15.
+ Warning if Rdlo == Rdhi. */
+
+static void
+do_smlal (str, flags)
+ char * str;
+ unsigned long flags;
{
- char * save_in;
- segT seg;
+ int rdlo, rdhi, rm, rs;
- save_in = input_line_pointer;
- input_line_pointer = *str;
- seg = expression (ep);
+ skip_whitespace (str);
-#ifdef OBJ_AOUT
- if (seg != absolute_section
- && seg != text_section
- && seg != data_section
- && seg != bss_section
- && seg != undefined_section)
+ if ((rdlo = reg_required_here (& str, 12)) == FAIL
+ || skip_past_comma (& str) == FAIL
+ || (rdhi = reg_required_here (& str, 16)) == FAIL
+ || skip_past_comma (& str) == FAIL
+ || (rm = reg_required_here (& str, 0)) == FAIL
+ || skip_past_comma (& str) == FAIL
+ || (rs = reg_required_here (& str, 8)) == FAIL)
{
- inst.error = _("bad_segment");
- *str = input_line_pointer;
- input_line_pointer = save_in;
- return 1;
+ inst.error = BAD_ARGS;
+ return;
}
-#endif
- /* Get rid of any bignums now, so that we don't generate an error for which
- we can't establish a line number later on. Big numbers are never valid
- in instructions, which is where this routine is always called. */
- if (ep->X_op == O_big
- || (ep->X_add_symbol
- && (walk_no_bignums (ep->X_add_symbol)
- || (ep->X_op_symbol
- && walk_no_bignums (ep->X_op_symbol)))))
+ if (rdlo == REG_PC || rdhi == REG_PC || rm == REG_PC || rs == REG_PC)
{
- inst.error = _("Invalid constant");
- *str = input_line_pointer;
- input_line_pointer = save_in;
- return 1;
+ inst.error = BAD_PC;
+ return;
}
- *str = input_line_pointer;
- input_line_pointer = save_in;
- return 0;
+ if (rdlo == rdhi)
+ as_tsktsk (_("rdhi and rdlo must be different"));
+
+ if (flags)
+ inst.error = BAD_FLAGS;
+ else
+ end_of_line (str);
}
-/* UNRESTRICT should be one if <shift> <register> is permitted for this
- instruction. */
+/* ARM V5E (El Segundo) signed-multiply (argument parse)
+ SMULxy{cond} Rd,Rm,Rs
+ Error if any register is R15. */
-static int
-decode_shift (str, unrestrict)
- char ** str;
- int unrestrict;
+static void
+do_smul (str, flags)
+ char * str;
+ unsigned long flags;
{
- const struct asm_shift_name * shift;
- char * p;
- char c;
+ int rd, rm, rs;
- skip_whitespace (* str);
+ skip_whitespace (str);
- for (p = * str; isalpha (* p); p ++)
- ;
+ if ((rd = reg_required_here (& str, 16)) == FAIL
+ || skip_past_comma (& str) == FAIL
+ || (rm = reg_required_here (& str, 0)) == FAIL
+ || skip_past_comma (& str) == FAIL
+ || (rs = reg_required_here (& str, 8)) == FAIL)
+ inst.error = BAD_ARGS;
- if (p == * str)
- {
- inst.error = _("Shift expression expected");
- return FAIL;
- }
+ else if (rd == REG_PC || rm == REG_PC || rs == REG_PC)
+ inst.error = BAD_PC;
- c = * p;
- * p = '\0';
- shift = (const struct asm_shift_name *) hash_find (arm_shift_hsh, * str);
- * p = c;
+ else if (flags)
+ inst.error = BAD_FLAGS;
- if (shift == NULL)
- {
- inst.error = _("Shift expression expected");
- return FAIL;
- }
+ else
+ end_of_line (str);
+}
- assert (shift->properties->index == shift_properties[shift->properties->index].index);
+/* ARM V5E (El Segundo) saturating-add/subtract (argument parse)
+ Q[D]{ADD,SUB}{cond} Rd,Rm,Rn
+ Error if any register is R15. */
- if (shift->properties->index == SHIFT_RRX)
- {
- * str = p;
- inst.instruction |= shift->properties->bit_field;
- return SUCCESS;
- }
+static void
+do_qadd (str, flags)
+ char * str;
+ unsigned long flags;
+{
+ int rd, rm, rn;
- skip_whitespace (p);
+ skip_whitespace (str);
- if (unrestrict && reg_required_here (& p, 8) != FAIL)
- {
- inst.instruction |= shift->properties->bit_field | SHIFT_BY_REG;
- * str = p;
- return SUCCESS;
- }
- else if (! is_immediate_prefix (* p))
- {
- inst.error = (unrestrict
- ? _("shift requires register or #expression")
- : _("shift requires #expression"));
- * str = p;
- return FAIL;
- }
+ if ((rd = reg_required_here (& str, 12)) == FAIL
+ || skip_past_comma (& str) == FAIL
+ || (rm = reg_required_here (& str, 0)) == FAIL
+ || skip_past_comma (& str) == FAIL
+ || (rn = reg_required_here (& str, 16)) == FAIL)
+ inst.error = BAD_ARGS;
- inst.error = NULL;
- p ++;
+ else if (rd == REG_PC || rm == REG_PC || rn == REG_PC)
+ inst.error = BAD_PC;
- if (my_get_expression (& inst.reloc.exp, & p))
- return FAIL;
+ else if (flags)
+ inst.error = BAD_FLAGS;
- /* Validate some simple #expressions. */
- if (inst.reloc.exp.X_op == O_constant)
- {
- unsigned num = inst.reloc.exp.X_add_number;
+ else
+ end_of_line (str);
+}
- /* Reject operations greater than 32. */
- if (num > 32
- /* Reject a shift of 0 unless the mode allows it. */
- || (num == 0 && shift->properties->allows_0 == 0)
- /* Reject a shift of 32 unless the mode allows it. */
- || (num == 32 && shift->properties->allows_32 == 0)
- )
- {
- /* As a special case we allow a shift of zero for
- modes that do not support it to be recoded as an
- logical shift left of zero (ie nothing). We warn
- about this though. */
- if (num == 0)
- {
- as_warn (_("Shift of 0 ignored."));
- shift = & shift_names[0];
- assert (shift->properties->index == SHIFT_LSL);
- }
- else
- {
- inst.error = _("Invalid immediate shift");
- return FAIL;
- }
- }
+/* ARM V5E (el Segundo)
+ MCRRcc <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
+ MRRCcc <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
- /* Shifts of 32 are encoded as 0, for those shifts that
- support it. */
- if (num == 32)
- num = 0;
+ These are equivalent to the XScale instructions MAR and MRA,
+ respectively, when coproc == 0, opcode == 0, and CRm == 0.
- inst.instruction |= (num << 7) | shift->properties->bit_field;
- }
- else
+ Result unpredicatable if Rd or Rn is R15. */
+
+static void
+do_co_reg2c (str, flags)
+ char * str;
+ unsigned long flags;
+{
+ int rd, rn;
+
+ skip_whitespace (str);
+
+ if (co_proc_number (& str) == FAIL)
{
- inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
- inst.reloc.pc_rel = 0;
- inst.instruction |= shift->properties->bit_field;
+ if (!inst.error)
+ inst.error = BAD_ARGS;
+ return;
}
- * str = p;
- return SUCCESS;
-}
+ if (skip_past_comma (& str) == FAIL
+ || cp_opc_expr (& str, 4, 4) == FAIL)
+ {
+ if (!inst.error)
+ inst.error = BAD_ARGS;
+ return;
+ }
-/* Do those data_ops which can take a negative immediate constant
- by altering the instuction. A bit of a hack really.
- MOV <-> MVN
- AND <-> BIC
- ADC <-> SBC
- by inverting the second operand, and
- ADD <-> SUB
- CMP <-> CMN
- by negating the second operand. */
+ if (skip_past_comma (& str) == FAIL
+ || (rd = reg_required_here (& str, 12)) == FAIL)
+ {
+ if (!inst.error)
+ inst.error = BAD_ARGS;
+ return;
+ }
-static int
-negate_data_op (instruction, value)
- unsigned long * instruction;
- unsigned long value;
-{
- int op, new_inst;
- unsigned long negated, inverted;
+ if (skip_past_comma (& str) == FAIL
+ || (rn = reg_required_here (& str, 16)) == FAIL)
+ {
+ if (!inst.error)
+ inst.error = BAD_ARGS;
+ return;
+ }
- negated = validate_immediate (-value);
- inverted = validate_immediate (~value);
+ /* Unpredictable result if rd or rn is R15. */
+ if (rd == REG_PC || rn == REG_PC)
+ as_tsktsk
+ (_("Warning: Instruction unpredictable when using r15"));
- op = (*instruction >> DATA_OP_SHIFT) & 0xf;
- switch (op)
+ if (skip_past_comma (& str) == FAIL
+ || cp_reg_required_here (& str, 0) == FAIL)
{
- /* First negates. */
- case OPCODE_SUB: /* ADD <-> SUB */
- new_inst = OPCODE_ADD;
- value = negated;
- break;
+ if (!inst.error)
+ inst.error = BAD_ARGS;
+ return;
+ }
- case OPCODE_ADD:
- new_inst = OPCODE_SUB;
- value = negated;
- break;
+ if (flags)
+ inst.error = BAD_COND;
- case OPCODE_CMP: /* CMP <-> CMN */
- new_inst = OPCODE_CMN;
- value = negated;
- break;
+ end_of_line (str);
+}
- case OPCODE_CMN:
- new_inst = OPCODE_CMP;
- value = negated;
- break;
+/* ARM V5 count-leading-zeroes instruction (argument parse)
+ CLZ{<cond>} <Rd>, <Rm>
+ Condition defaults to COND_ALWAYS.
+ Error if Rd or Rm are R15. */
- /* Now Inverted ops. */
- case OPCODE_MOV: /* MOV <-> MVN */
- new_inst = OPCODE_MVN;
- value = inverted;
- break;
+static void
+do_clz (str, flags)
+ char * str;
+ unsigned long flags;
+{
+ int rd, rm;
- case OPCODE_MVN:
- new_inst = OPCODE_MOV;
- value = inverted;
- break;
+ if (flags)
+ {
+ as_bad (BAD_FLAGS);
+ return;
+ }
- case OPCODE_AND: /* AND <-> BIC */
- new_inst = OPCODE_BIC;
- value = inverted;
- break;
+ skip_whitespace (str);
- case OPCODE_BIC:
- new_inst = OPCODE_AND;
- value = inverted;
- break;
+ if (((rd = reg_required_here (& str, 12)) == FAIL)
+ || (skip_past_comma (& str) == FAIL)
+ || ((rm = reg_required_here (& str, 0)) == FAIL))
+ inst.error = BAD_ARGS;
- case OPCODE_ADC: /* ADC <-> SBC */
- new_inst = OPCODE_SBC;
- value = inverted;
- break;
+ else if (rd == REG_PC || rm == REG_PC )
+ inst.error = BAD_PC;
- case OPCODE_SBC:
- new_inst = OPCODE_ADC;
- value = inverted;
- break;
+ else
+ end_of_line (str);
+}
- /* We cannot do anything. */
- default:
- return FAIL;
- }
+/* ARM V5 (argument parse)
+ LDC2{L} <coproc>, <CRd>, <addressing mode>
+ STC2{L} <coproc>, <CRd>, <addressing mode>
+ Instruction is not conditional, and has 0xf in the codition field.
+ Otherwise, it's the same as LDC/STC. */
- if (value == (unsigned) FAIL)
- return FAIL;
+static void
+do_lstc2 (str, flags)
+ char * str;
+ unsigned long flags;
+{
+ if (flags)
+ inst.error = BAD_COND;
- *instruction &= OPCODE_MASK;
- *instruction |= new_inst << DATA_OP_SHIFT;
- return value;
+ skip_whitespace (str);
+
+ if (co_proc_number (& str) == FAIL)
+ {
+ if (!inst.error)
+ inst.error = BAD_ARGS;
+ }
+ else if (skip_past_comma (& str) == FAIL
+ || cp_reg_required_here (& str, 12) == FAIL)
+ {
+ if (!inst.error)
+ inst.error = BAD_ARGS;
+ }
+ else if (skip_past_comma (& str) == FAIL
+ || cp_address_required_here (& str) == FAIL)
+ {
+ if (! inst.error)
+ inst.error = BAD_ARGS;
+ }
+ else
+ end_of_line (str);
}
-static int
-data_op2 (str)
- char ** str;
+/* ARM V5 (argument parse)
+ CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>, <opcode_2>
+ Instruction is not conditional, and has 0xf in the condition field.
+ Otherwise, it's the same as CDP. */
+
+static void
+do_cdp2 (str, flags)
+ char * str;
+ unsigned long flags;
{
- int value;
- expressionS expr;
+ skip_whitespace (str);
- skip_whitespace (* str);
+ if (co_proc_number (& str) == FAIL)
+ {
+ if (!inst.error)
+ inst.error = BAD_ARGS;
+ return;
+ }
- if (reg_required_here (str, 0) != FAIL)
+ if (skip_past_comma (& str) == FAIL
+ || cp_opc_expr (& str, 20,4) == FAIL)
{
- if (skip_past_comma (str) == SUCCESS)
- /* Shift operation on register. */
- return decode_shift (str, NO_SHIFT_RESTRICT);
+ if (!inst.error)
+ inst.error = BAD_ARGS;
+ return;
+ }
- return SUCCESS;
+ if (skip_past_comma (& str) == FAIL
+ || cp_reg_required_here (& str, 12) == FAIL)
+ {
+ if (!inst.error)
+ inst.error = BAD_ARGS;
+ return;
}
- else
+
+ if (skip_past_comma (& str) == FAIL
+ || cp_reg_required_here (& str, 16) == FAIL)
{
- /* Immediate expression. */
- if (is_immediate_prefix (**str))
+ if (!inst.error)
+ inst.error = BAD_ARGS;
+ return;
+ }
+
+ if (skip_past_comma (& str) == FAIL
+ || cp_reg_required_here (& str, 0) == FAIL)
+ {
+ if (!inst.error)
+ inst.error = BAD_ARGS;
+ return;
+ }
+
+ if (skip_past_comma (& str) == SUCCESS)
+ {
+ if (cp_opc_expr (& str, 5, 3) == FAIL)
{
- (*str)++;
- inst.error = NULL;
+ if (!inst.error)
+ inst.error = BAD_ARGS;
+ return;
+ }
+ }
- if (my_get_expression (&inst.reloc.exp, str))
- return FAIL;
+ if (flags)
+ inst.error = BAD_FLAGS;
- if (inst.reloc.exp.X_add_symbol)
- {
- inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
- inst.reloc.pc_rel = 0;
- }
- else
- {
- if (skip_past_comma (str) == SUCCESS)
- {
- /* #x, y -- ie explicit rotation by Y. */
- if (my_get_expression (&expr, str))
- return FAIL;
-
- if (expr.X_op != O_constant)
- {
- inst.error = _("Constant expression expected");
- return FAIL;
- }
-
- /* Rotate must be a multiple of 2. */
- if (((unsigned) expr.X_add_number) > 30
- || (expr.X_add_number & 1) != 0
- || ((unsigned) inst.reloc.exp.X_add_number) > 255)
- {
- inst.error = _("Invalid constant");
- return FAIL;
- }
- inst.instruction |= INST_IMMEDIATE;
- inst.instruction |= inst.reloc.exp.X_add_number;
- inst.instruction |= expr.X_add_number << 7;
- return SUCCESS;
- }
-
- /* Implicit rotation, select a suitable one. */
- value = validate_immediate (inst.reloc.exp.X_add_number);
-
- if (value == FAIL)
- {
- /* Can't be done. Perhaps the code reads something like
- "add Rd, Rn, #-n", where "sub Rd, Rn, #n" would be OK. */
- if ((value = negate_data_op (&inst.instruction,
- inst.reloc.exp.X_add_number))
- == FAIL)
- {
- inst.error = _("Invalid constant");
- return FAIL;
- }
- }
-
- inst.instruction |= value;
- }
-
- inst.instruction |= INST_IMMEDIATE;
- return SUCCESS;
- }
-
- (*str)++;
- inst.error = _("Register or shift expression expected");
- return FAIL;
- }
+ end_of_line (str);
}
-static int
-fp_op2 (str)
- char ** str;
-{
- skip_whitespace (* str);
-
- if (fp_reg_required_here (str, 0) != FAIL)
- return SUCCESS;
- else
- {
- /* Immediate expression. */
- if (*((*str)++) == '#')
- {
- int i;
-
- inst.error = NULL;
-
- skip_whitespace (* str);
-
- /* First try and match exact strings, this is to guarantee
- that some formats will work even for cross assembly. */
-
- for (i = 0; fp_const[i]; i++)
- {
- if (strncmp (*str, fp_const[i], strlen (fp_const[i])) == 0)
- {
- char *start = *str;
-
- *str += strlen (fp_const[i]);
- if (is_end_of_line[(unsigned char) **str])
- {
- inst.instruction |= i + 8;
- return SUCCESS;
- }
- *str = start;
- }
- }
-
- /* Just because we didn't get a match doesn't mean that the
- constant isn't valid, just that it is in a format that we
- don't automatically recognize. Try parsing it with
- the standard expression routines. */
- if ((i = my_get_float_expression (str)) >= 0)
- {
- inst.instruction |= i + 8;
- return SUCCESS;
- }
-
- inst.error = _("Invalid floating point immediate expression");
- return FAIL;
- }
- inst.error =
- _("Floating point register or immediate expression expected");
- return FAIL;
- }
-}
+/* ARM V5 (argument parse)
+ MCR2 <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>, <opcode_2>
+ MRC2 <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>, <opcode_2>
+ Instruction is not conditional, and has 0xf in the condition field.
+ Otherwise, it's the same as MCR/MRC. */
static void
-do_arit (str, flags)
- char * str;
+do_co_reg2 (str, flags)
+ char * str;
unsigned long flags;
{
skip_whitespace (str);
- if (reg_required_here (&str, 12) == FAIL
- || skip_past_comma (&str) == FAIL
- || reg_required_here (&str, 16) == FAIL
- || skip_past_comma (&str) == FAIL
- || data_op2 (&str) == FAIL)
+ if (co_proc_number (& str) == FAIL)
{
if (!inst.error)
inst.error = BAD_ARGS;
return;
}
- inst.instruction |= flags;
- end_of_line (str);
- return;
-}
-
-static void
-do_adr (str, flags)
- char * str;
- unsigned long flags;
-{
- /* This is a pseudo-op of the form "adr rd, label" to be converted
- into a relative address of the form "add rd, pc, #label-.-8". */
- skip_whitespace (str);
-
- if (reg_required_here (&str, 12) == FAIL
- || skip_past_comma (&str) == FAIL
- || my_get_expression (&inst.reloc.exp, &str))
+ if (skip_past_comma (& str) == FAIL
+ || cp_opc_expr (& str, 21, 3) == FAIL)
{
if (!inst.error)
inst.error = BAD_ARGS;
return;
}
- /* Frag hacking will turn this into a sub instruction if the offset turns
- out to be negative. */
- inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
- inst.reloc.exp.X_add_number -= 8; /* PC relative adjust. */
- inst.reloc.pc_rel = 1;
- inst.instruction |= flags;
-
- end_of_line (str);
-}
-
-static void
-do_adrl (str, flags)
- char * str;
- unsigned long flags;
-{
- /* This is a pseudo-op of the form "adrl rd, label" to be converted
- into a relative address of the form:
- add rd, pc, #low(label-.-8)"
- add rd, rd, #high(label-.-8)" */
-
- skip_whitespace (str);
-
- if (reg_required_here (& str, 12) == FAIL
- || skip_past_comma (& str) == FAIL
- || my_get_expression (& inst.reloc.exp, & str))
+ if (skip_past_comma (& str) == FAIL
+ || reg_required_here (& str, 12) == FAIL)
{
if (!inst.error)
inst.error = BAD_ARGS;
return;
}
- end_of_line (str);
-
- /* Frag hacking will turn this into a sub instruction if the offset turns
- out to be negative. */
- inst.reloc.type = BFD_RELOC_ARM_ADRL_IMMEDIATE;
- inst.reloc.exp.X_add_number -= 8; /* PC relative adjust */
- inst.reloc.pc_rel = 1;
- inst.instruction |= flags;
- inst.size = INSN_SIZE * 2;
-
- return;
-}
-
-static void
-do_cmp (str, flags)
- char * str;
- unsigned long flags;
-{
- skip_whitespace (str);
-
- if (reg_required_here (&str, 16) == FAIL)
+ if (skip_past_comma (& str) == FAIL
+ || cp_reg_required_here (& str, 16) == FAIL)
{
if (!inst.error)
inst.error = BAD_ARGS;
return;
}
- if (skip_past_comma (&str) == FAIL
- || data_op2 (&str) == FAIL)
+ if (skip_past_comma (& str) == FAIL
+ || cp_reg_required_here (& str, 0) == FAIL)
{
if (!inst.error)
inst.error = BAD_ARGS;
return;
}
- inst.instruction |= flags;
- if ((flags & 0x0000f000) == 0)
- inst.instruction |= CONDS_BIT;
+ if (skip_past_comma (& str) == SUCCESS)
+ {
+ if (cp_opc_expr (& str, 5, 3) == FAIL)
+ {
+ if (!inst.error)
+ inst.error = BAD_ARGS;
+ return;
+ }
+ }
+
+ if (flags)
+ inst.error = BAD_COND;
end_of_line (str);
- return;
}
+/* THUMB V5 breakpoint instruction (argument parse)
+ BKPT <immed_8>. */
+
static void
-do_mov (str, flags)
+do_t_bkpt (str)
char * str;
- unsigned long flags;
{
+ expressionS expr;
+ unsigned long number;
+
skip_whitespace (str);
- if (reg_required_here (&str, 12) == FAIL)
+ /* Allow optional leading '#'. */
+ if (is_immediate_prefix (*str))
+ str ++;
+
+ memset (& expr, '\0', sizeof (expr));
+ if (my_get_expression (& expr, & str) || (expr.X_op != O_constant))
{
- if (!inst.error)
- inst.error = BAD_ARGS;
+ inst.error = _("bad or missing expression");
return;
}
- if (skip_past_comma (&str) == FAIL
- || data_op2 (&str) == FAIL)
+ number = expr.X_add_number;
+
+ /* Check it fits an 8 bit unsigned. */
+ if (number != (number & 0xff))
{
- if (!inst.error)
- inst.error = BAD_ARGS;
+ inst.error = _("immediate value out of range");
return;
}
- inst.instruction |= flags;
+ inst.instruction |= number;
+
end_of_line (str);
- return;
}
-static int
-ldst_extend (str, hwse)
- char ** str;
- int hwse;
+/* ARM V5 branch-link-exchange (argument parse) for BLX(1) only.
+ Expects inst.instruction is set for BLX(1).
+ Note: this is cloned from do_branch, and the reloc changed to be a
+ new one that can cope with setting one extra bit (the H bit). */
+
+static void
+do_branch25 (str, flags)
+ char * str;
+ unsigned long flags ATTRIBUTE_UNUSED;
{
- int add = INDEX_UP;
+ if (my_get_expression (& inst.reloc.exp, & str))
+ return;
- switch (**str)
- {
- case '#':
- case '$':
- (*str)++;
- if (my_get_expression (& inst.reloc.exp, str))
- return FAIL;
+#ifdef OBJ_ELF
+ {
+ char * save_in;
- if (inst.reloc.exp.X_op == O_constant)
- {
- int value = inst.reloc.exp.X_add_number;
+ /* ScottB: February 5, 1998 */
+ /* Check to see of PLT32 reloc required for the instruction. */
- if ((hwse && (value < -255 || value > 255))
- || (value < -4095 || value > 4095))
- {
- inst.error = _("address offset too large");
- return FAIL;
- }
+ /* arm_parse_reloc() works on input_line_pointer.
+ We actually want to parse the operands to the branch instruction
+ passed in 'str'. Save the input pointer and restore it later. */
+ save_in = input_line_pointer;
+ input_line_pointer = str;
- if (value < 0)
- {
- value = -value;
- add = 0;
- }
+ if (inst.reloc.exp.X_op == O_symbol
+ && *str == '('
+ && arm_parse_reloc () == BFD_RELOC_ARM_PLT32)
+ {
+ inst.reloc.type = BFD_RELOC_ARM_PLT32;
+ inst.reloc.pc_rel = 0;
+ /* Modify str to point to after parsed operands, otherwise
+ end_of_line() will complain about the (PLT) left in str. */
+ str = input_line_pointer;
+ }
+ else
+ {
+ inst.reloc.type = BFD_RELOC_ARM_PCREL_BLX;
+ inst.reloc.pc_rel = 1;
+ }
- /* Halfword and signextension instructions have the
- immediate value split across bits 11..8 and bits 3..0. */
- if (hwse)
- inst.instruction |= (add | HWOFFSET_IMM
- | ((value >> 4) << 8) | (value & 0xF));
- else
- inst.instruction |= add | value;
- }
- else
- {
- if (hwse)
- {
- inst.instruction |= HWOFFSET_IMM;
- inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM8;
- }
- else
- inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM;
- inst.reloc.pc_rel = 0;
- }
- return SUCCESS;
+ input_line_pointer = save_in;
+ }
+#else
+ inst.reloc.type = BFD_RELOC_ARM_PCREL_BLX;
+ inst.reloc.pc_rel = 1;
+#endif /* OBJ_ELF */
- case '-':
- add = 0;
- /* Fall through. */
+ end_of_line (str);
+}
- case '+':
- (*str)++;
- /* Fall through. */
+/* ARM V5 branch-link-exchange instruction (argument parse)
+ BLX <target_addr> ie BLX(1)
+ BLX{<condition>} <Rm> ie BLX(2)
+ Unfortunately, there are two different opcodes for this mnemonic.
+ So, the insns[].value is not used, and the code here zaps values
+ into inst.instruction.
+ Also, the <target_addr> can be 25 bits, hence has its own reloc. */
- default:
- if (reg_required_here (str, 0) == FAIL)
- return FAIL;
+static void
+do_blx (str, flags)
+ char * str;
+ unsigned long flags;
+{
+ char * mystr = str;
+ int rm;
- if (hwse)
- inst.instruction |= add;
- else
- {
- inst.instruction |= add | OFFSET_REG;
- if (skip_past_comma (str) == SUCCESS)
- return decode_shift (str, SHIFT_RESTRICT);
- }
+ if (flags)
+ {
+ as_bad (BAD_FLAGS);
+ return;
+ }
- return SUCCESS;
+ skip_whitespace (mystr);
+ rm = reg_required_here (& mystr, 0);
+
+ /* The above may set inst.error. Ignore his opinion. */
+ inst.error = 0;
+
+ if (rm != FAIL)
+ {
+ /* Arg is a register.
+ Use the condition code our caller put in inst.instruction.
+ Pass ourselves off as a BX with a funny opcode. */
+ inst.instruction |= 0x012fff30;
+ do_bx (str, flags);
+ }
+ else
+ {
+ /* This must be is BLX <target address>, no condition allowed. */
+ if (inst.instruction != COND_ALWAYS)
+ {
+ inst.error = BAD_COND;
+ return;
+ }
+
+ inst.instruction = 0xfafffffe;
+
+ /* Process like a B/BL, but with a different reloc.
+ Note that B/BL expecte fffffe, not 0, offset in the opcode table. */
+ do_branch25 (str, flags);
}
}
+/* ARM V5 Thumb BLX (argument parse)
+ BLX <target_addr> which is BLX(1)
+ BLX <Rm> which is BLX(2)
+ Unfortunately, there are two different opcodes for this mnemonic.
+ So, the tinsns[].value is not used, and the code here zaps values
+ into inst.instruction. */
+
static void
-do_ldst (str, flags)
- char * str;
- unsigned long flags;
+do_t_blx (str)
+ char * str;
{
- int halfword = 0;
- int pre_inc = 0;
- int conflict_reg;
- int value;
+ char * mystr = str;
+ int rm;
- /* This is not ideal, but it is the simplest way of dealing with the
- ARM7T halfword instructions (since they use a different
- encoding, but the same mnemonic): */
- halfword = (flags & 0x80000000) != 0;
- if (halfword)
+ skip_whitespace (mystr);
+ inst.instruction = 0x4780;
+
+ /* Note that this call is to the ARM register recognizer. BLX(2)
+ uses the ARM register space, not the Thumb one, so a call to
+ thumb_reg() would be wrong. */
+ rm = reg_required_here (& mystr, 3);
+ inst.error = 0;
+
+ if (rm != FAIL)
{
- /* This is actually a load/store of a halfword, or a
- signed-extension load. */
- if ((cpu_variant & ARM_HALFWORD) == 0)
- {
- inst.error
- = _("Processor does not support halfwords or signed bytes");
- return;
- }
+ /* It's BLX(2). The .instruction was zapped with rm & is final. */
+ inst.size = 2;
+ }
+ else
+ {
+ /* No ARM register. This must be BLX(1). Change the .instruction. */
+ inst.instruction = 0xf7ffeffe;
+ inst.size = 4;
- inst.instruction = ((inst.instruction & COND_MASK)
- | (flags & ~COND_MASK));
+ if (my_get_expression (& inst.reloc.exp, & mystr))
+ return;
- flags = 0;
+ inst.reloc.type = BFD_RELOC_THUMB_PCREL_BLX;
+ inst.reloc.pc_rel = 1;
}
+ end_of_line (mystr);
+}
+
+/* ARM V5 breakpoint instruction (argument parse)
+ BKPT <16 bit unsigned immediate>
+ Instruction is not conditional.
+ The bit pattern given in insns[] has the COND_ALWAYS condition,
+ and it is an error if the caller tried to override that.
+ Note "flags" is nonzero if a flag was supplied (which is an error). */
+
+static void
+do_bkpt (str, flags)
+ char * str;
+ unsigned long flags;
+{
+ expressionS expr;
+ unsigned long number;
+
skip_whitespace (str);
- if ((conflict_reg = reg_required_here (& str, 12)) == FAIL)
+ /* Allow optional leading '#'. */
+ if (is_immediate_prefix (* str))
+ str++;
+
+ memset (& expr, '\0', sizeof (expr));
+
+ if (my_get_expression (& expr, & str) || (expr.X_op != O_constant))
{
- if (!inst.error)
- inst.error = BAD_ARGS;
+ inst.error = _("bad or missing expression");
return;
}
- if (skip_past_comma (& str) == FAIL)
+ number = expr.X_add_number;
+
+ /* Check it fits a 16 bit unsigned. */
+ if (number != (number & 0xffff))
{
- inst.error = _("Address expected");
+ inst.error = _("immediate value out of range");
return;
}
- if (*str == '[')
- {
- int reg;
+ /* Top 12 of 16 bits to bits 19:8. */
+ inst.instruction |= (number & 0xfff0) << 4;
- str++;
+ /* Bottom 4 of 16 bits to bits 3:0. */
+ inst.instruction |= number & 0xf;
- skip_whitespace (str);
+ end_of_line (str);
- if ((reg = reg_required_here (&str, 16)) == FAIL)
- return;
+ if (flags)
+ inst.error = BAD_FLAGS;
+}
- /* Conflicts can occur on stores as well as loads. */
- conflict_reg = (conflict_reg == reg);
+/* Xscale multiply-accumulate (argument parse)
+ MIAcc acc0,Rm,Rs
+ MIAPHcc acc0,Rm,Rs
+ MIAxycc acc0,Rm,Rs. */
- skip_whitespace (str);
+static void
+do_mia (str, flags)
+ char * str;
+ unsigned long flags;
+{
+ int rs;
+ int rm;
- if (*str == ']')
- {
- str ++;
+ if (flags)
+ as_bad (BAD_FLAGS);
- if (skip_past_comma (&str) == SUCCESS)
- {
- /* [Rn],... (post inc) */
- if (ldst_extend (&str, halfword) == FAIL)
- return;
- if (conflict_reg)
- as_warn (_("%s register same as write-back base"),
- ((inst.instruction & LOAD_BIT)
- ? _("destination") : _("source")));
- }
- else
- {
- /* [Rn] */
- if (halfword)
- inst.instruction |= HWOFFSET_IMM;
+ else if (accum0_required_here (& str) == FAIL)
+ inst.error = ERR_NO_ACCUM;
- skip_whitespace (str);
+ else if (skip_past_comma (& str) == FAIL
+ || (rm = reg_required_here (& str, 0)) == FAIL)
+ inst.error = BAD_ARGS;
- if (*str == '!')
- {
- if (conflict_reg)
- as_warn (_("%s register same as write-back base"),
- ((inst.instruction & LOAD_BIT)
- ? _("destination") : _("source")));
- str++;
- inst.instruction |= WRITE_BACK;
- }
+ else if (skip_past_comma (& str) == FAIL
+ || (rs = reg_required_here (& str, 12)) == FAIL)
+ inst.error = BAD_ARGS;
- flags |= INDEX_UP;
- if (! (flags & TRANS_BIT))
- pre_inc = 1;
- }
- }
- else
- {
- /* [Rn,...] */
- if (skip_past_comma (&str) == FAIL)
- {
- inst.error = _("pre-indexed expression expected");
- return;
- }
+ /* inst.instruction has now been zapped with both rm and rs. */
+ else if (rm == REG_PC || rs == REG_PC)
+ inst.error = BAD_PC; /* Undefined result if rm or rs is R15. */
- pre_inc = 1;
- if (ldst_extend (&str, halfword) == FAIL)
- return;
+ else
+ end_of_line (str);
+}
- skip_whitespace (str);
+/* Xscale move-accumulator-register (argument parse)
- if (*str++ != ']')
- {
- inst.error = _("missing ]");
- return;
- }
+ MARcc acc0,RdLo,RdHi. */
- skip_whitespace (str);
+static void
+do_mar (str, flags)
+ char * str;
+ unsigned long flags;
+{
+ int rdlo, rdhi;
- if (*str == '!')
- {
- if (conflict_reg)
- as_warn (_("%s register same as write-back base"),
- ((inst.instruction & LOAD_BIT)
- ? _("destination") : _("source")));
- str++;
- inst.instruction |= WRITE_BACK;
- }
- }
- }
- else if (*str == '=')
- {
- /* Parse an "ldr Rd, =expr" instruction; this is another pseudo op. */
- str++;
+ if (flags)
+ as_bad (BAD_FLAGS);
- skip_whitespace (str);
+ else if (accum0_required_here (& str) == FAIL)
+ inst.error = ERR_NO_ACCUM;
- if (my_get_expression (&inst.reloc.exp, &str))
- return;
+ else if (skip_past_comma (& str) == FAIL
+ || (rdlo = reg_required_here (& str, 12)) == FAIL)
+ inst.error = BAD_ARGS;
- if (inst.reloc.exp.X_op != O_constant
- && inst.reloc.exp.X_op != O_symbol)
- {
- inst.error = _("Constant expression expected");
- return;
- }
+ else if (skip_past_comma (& str) == FAIL
+ || (rdhi = reg_required_here (& str, 16)) == FAIL)
+ inst.error = BAD_ARGS;
- if (inst.reloc.exp.X_op == O_constant
- && (value = validate_immediate (inst.reloc.exp.X_add_number)) != FAIL)
- {
- /* This can be done with a mov instruction. */
- inst.instruction &= LITERAL_MASK;
- inst.instruction |= INST_IMMEDIATE | (OPCODE_MOV << DATA_OP_SHIFT);
- inst.instruction |= (flags & COND_MASK) | (value & 0xfff);
- end_of_line (str);
- return;
- }
- else
- {
- /* Insert into literal pool. */
- if (add_to_lit_pool () == FAIL)
- {
- if (!inst.error)
- inst.error = _("literal pool insertion failed");
- return;
- }
+ /* inst.instruction has now been zapped with both rdlo and rdhi. */
+ else if (rdlo == REG_PC || rdhi == REG_PC)
+ inst.error = BAD_PC; /* Undefined result if rdlo or rdhi is R15. */
- /* Change the instruction exp to point to the pool. */
- if (halfword)
- {
- inst.instruction |= HWOFFSET_IMM;
- inst.reloc.type = BFD_RELOC_ARM_HWLITERAL;
- }
- else
- inst.reloc.type = BFD_RELOC_ARM_LITERAL;
- inst.reloc.pc_rel = 1;
- inst.instruction |= (REG_PC << 16);
- pre_inc = 1;
- }
- }
else
- {
- if (my_get_expression (&inst.reloc.exp, &str))
- return;
+ end_of_line (str);
+}
- if (halfword)
- {
- inst.instruction |= HWOFFSET_IMM;
- inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM8;
- }
- else
- inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM;
-#ifndef TE_WINCE
- /* PC rel adjust. */
- inst.reloc.exp.X_add_number -= 8;
-#endif
- inst.reloc.pc_rel = 1;
- inst.instruction |= (REG_PC << 16);
- pre_inc = 1;
- }
+/* Xscale move-register-accumulator (argument parse)
- if (pre_inc && (flags & TRANS_BIT))
- inst.error = _("Pre-increment instruction with translate");
+ MRAcc RdLo,RdHi,acc0. */
- inst.instruction |= flags | (pre_inc ? PRE_INDEX : 0);
- end_of_line (str);
- return;
-}
+static void
+do_mra (str, flags)
+ char * str;
+ unsigned long flags;
+{
+ int rdlo;
+ int rdhi;
-static long
-reg_list (strp)
- char ** strp;
-{
- char * str = * strp;
- long range = 0;
- int another_range;
-
- /* We come back here if we get ranges concatenated by '+' or '|'. */
- do
+ if (flags)
{
- another_range = 0;
-
- if (*str == '{')
- {
- int in_range = 0;
- int cur_reg = -1;
-
- str++;
- do
- {
- int reg;
-
- skip_whitespace (str);
-
- if ((reg = reg_required_here (& str, -1)) == FAIL)
- return FAIL;
-
- if (in_range)
- {
- int i;
-
- if (reg <= cur_reg)
- {
- inst.error = _("Bad range in register list");
- return FAIL;
- }
-
- for (i = cur_reg + 1; i < reg; i++)
- {
- if (range & (1 << i))
- as_tsktsk
- (_("Warning: Duplicated register (r%d) in register list"),
- i);
- else
- range |= 1 << i;
- }
- in_range = 0;
- }
-
- if (range & (1 << reg))
- as_tsktsk (_("Warning: Duplicated register (r%d) in register list"),
- reg);
- else if (reg <= cur_reg)
- as_tsktsk (_("Warning: Register range not in ascending order"));
-
- range |= 1 << reg;
- cur_reg = reg;
- }
- while (skip_past_comma (&str) != FAIL
- || (in_range = 1, *str++ == '-'));
- str--;
- skip_whitespace (str);
-
- if (*str++ != '}')
- {
- inst.error = _("Missing `}'");
- return FAIL;
- }
- }
- else
- {
- expressionS expr;
+ as_bad (BAD_FLAGS);
+ return;
+ }
- if (my_get_expression (&expr, &str))
- return FAIL;
+ skip_whitespace (str);
- if (expr.X_op == O_constant)
- {
- if (expr.X_add_number
- != (expr.X_add_number & 0x0000ffff))
- {
- inst.error = _("invalid register mask");
- return FAIL;
- }
+ if ((rdlo = reg_required_here (& str, 12)) == FAIL)
+ inst.error = BAD_ARGS;
- if ((range & expr.X_add_number) != 0)
- {
- int regno = range & expr.X_add_number;
+ else if (skip_past_comma (& str) == FAIL
+ || (rdhi = reg_required_here (& str, 16)) == FAIL)
+ inst.error = BAD_ARGS;
- regno &= -regno;
- regno = (1 << regno) - 1;
- as_tsktsk
- (_("Warning: Duplicated register (r%d) in register list"),
- regno);
- }
+ else if (skip_past_comma (& str) == FAIL
+ || accum0_required_here (& str) == FAIL)
+ inst.error = ERR_NO_ACCUM;
- range |= expr.X_add_number;
- }
- else
- {
- if (inst.reloc.type != 0)
- {
- inst.error = _("expression too complex");
- return FAIL;
- }
+ /* inst.instruction has now been zapped with both rdlo and rdhi. */
+ else if (rdlo == rdhi)
+ inst.error = BAD_ARGS; /* Undefined result if 2 writes to same reg. */
- memcpy (&inst.reloc.exp, &expr, sizeof (expressionS));
- inst.reloc.type = BFD_RELOC_ARM_MULTI;
- inst.reloc.pc_rel = 0;
- }
- }
+ else if (rdlo == REG_PC || rdhi == REG_PC)
+ inst.error = BAD_PC; /* Undefined result if rdlo or rdhi is R15. */
+ else
+ end_of_line (str);
+}
- skip_whitespace (str);
+/* Xscale: Preload-Cache
- if (*str == '|' || *str == '+')
- {
- str++;
- another_range = 1;
- }
- }
- while (another_range);
+ PLD <addr_mode>
- *strp = str;
- return range;
-}
+ Syntactically, like LDR with B=1, W=0, L=1. */
static void
-do_ldmstm (str, flags)
+do_pld (str, flags)
char * str;
unsigned long flags;
{
- int base_reg;
- long range;
-
- skip_whitespace (str);
-
- if ((base_reg = reg_required_here (&str, 16)) == FAIL)
- return;
+ int rd;
- if (base_reg == REG_PC)
+ if (flags)
{
- inst.error = _("r15 not allowed as base register");
+ as_bad (BAD_FLAGS);
return;
}
skip_whitespace (str);
- if (*str == '!')
- {
- flags |= WRITE_BACK;
- str++;
- }
-
- if (skip_past_comma (&str) == FAIL
- || (range = reg_list (&str)) == FAIL)
+ if (* str != '[')
{
- if (! inst.error)
- inst.error = BAD_ARGS;
+ inst.error = _("'[' expected after PLD mnemonic");
return;
}
- if (*str == '^')
+ ++ str;
+ skip_whitespace (str);
+
+ if ((rd = reg_required_here (& str, 16)) == FAIL)
+ return;
+
+ skip_whitespace (str);
+
+ if (* str == ']')
{
- str++;
- flags |= LDM_TYPE_2_OR_3;
+ /* [Rn], ... ? */
+ ++ str;
+ skip_whitespace (str);
+
+ if (skip_past_comma (& str) == SUCCESS)
+ {
+ if (ldst_extend (& str, 0) == FAIL)
+ return;
+ }
+ else if (* str == '!') /* [Rn]! */
+ {
+ inst.error = _("writeback used in preload instruction");
+ ++ str;
+ }
+ else /* [Rn] */
+ inst.instruction |= INDEX_UP | PRE_INDEX;
}
+ else /* [Rn, ...] */
+ {
+ if (skip_past_comma (& str) == FAIL)
+ {
+ inst.error = _("pre-indexed expression expected");
+ return;
+ }
- inst.instruction |= flags | range;
- end_of_line (str);
- return;
-}
+ if (ldst_extend (& str, 0) == FAIL)
+ return;
-static void
-do_swi (str, flags)
- char * str;
- unsigned long flags;
-{
- skip_whitespace (str);
+ skip_whitespace (str);
- /* Allow optional leading '#'. */
- if (is_immediate_prefix (*str))
- str++;
+ if (* str != ']')
+ {
+ inst.error = _("missing ]");
+ return;
+ }
- if (my_get_expression (& inst.reloc.exp, & str))
- return;
+ ++ str;
+ skip_whitespace (str);
- inst.reloc.type = BFD_RELOC_ARM_SWI;
- inst.reloc.pc_rel = 0;
- inst.instruction |= flags;
+ if (* str == '!') /* [Rn]! */
+ {
+ inst.error = _("writeback used in preload instruction");
+ ++ str;
+ }
- end_of_line (str);
+ inst.instruction |= PRE_INDEX;
+ }
- return;
+ end_of_line (str);
}
+/* Xscale load-consecutive (argument parse)
+ Mode is like LDRH.
+
+ LDRccD R, mode
+ STRccD R, mode. */
+
static void
-do_swap (str, flags)
+do_ldrd (str, flags)
char * str;
unsigned long flags;
{
- int reg;
+ int rd;
+ int rn;
- skip_whitespace (str);
+ if (flags != DOUBLE_LOAD_FLAG)
+ {
+ /* Change instruction pattern to normal ldr/str. */
+ if (inst.instruction & 0x20)
+ inst.instruction = (inst.instruction & COND_MASK) | 0x04000000; /* str */
+ else
+ inst.instruction = (inst.instruction & COND_MASK) | 0x04100000; /* ldr */
- if ((reg = reg_required_here (&str, 12)) == FAIL)
- return;
+ /* Perform a normal load/store instruction parse. */
+ do_ldst (str, flags);
- if (reg == REG_PC)
- {
- inst.error = _("r15 not allowed in swap");
return;
}
- if (skip_past_comma (&str) == FAIL
- || (reg = reg_required_here (&str, 0)) == FAIL)
+ if ((cpu_variant & ARM_EXT_XSCALE) != ARM_EXT_XSCALE)
{
- if (!inst.error)
- inst.error = BAD_ARGS;
+ static char buff[128];
+
+ --str;
+ while (ISSPACE (*str))
+ --str;
+ str -= 4;
+
+ /* Deny all knowledge. */
+ sprintf (buff, _("bad instruction '%.100s'"), str);
+ inst.error = buff;
return;
}
- if (reg == REG_PC)
+ skip_whitespace (str);
+
+ if ((rd = reg_required_here (& str, 12)) == FAIL)
{
- inst.error = _("r15 not allowed in swap");
+ inst.error = BAD_ARGS;
return;
}
- if (skip_past_comma (&str) == FAIL
- || *str++ != '[')
+ if (skip_past_comma (& str) == FAIL
+ || (rn = ld_mode_required_here (& str)) == FAIL)
{
- inst.error = BAD_ARGS;
+ if (!inst.error)
+ inst.error = BAD_ARGS;
return;
}
- skip_whitespace (str);
-
- if ((reg = reg_required_here (&str, 16)) == FAIL)
- return;
-
- if (reg == REG_PC)
+ /* inst.instruction has now been zapped with Rd and the addressing mode. */
+ if (rd & 1) /* Unpredictable result if Rd is odd. */
{
- inst.error = BAD_PC;
+ inst.error = _("Destination register must be even");
return;
}
- skip_whitespace (str);
-
- if (*str++ != ']')
+ if (rd == REG_LR || rd == 12)
{
- inst.error = _("missing ]");
+ inst.error = _("r12 or r14 not allowed here");
return;
}
- inst.instruction |= flags;
+ if (((rd == rn) || (rd + 1 == rn))
+ &&
+ ((inst.instruction & WRITE_BACK)
+ || (!(inst.instruction & PRE_INDEX))))
+ as_warn (_("pre/post-indexing used when modified address register is destination"));
+
end_of_line (str);
- return;
}
-static void
-do_branch (str, flags)
- char * str;
- unsigned long flags ATTRIBUTE_UNUSED;
-{
- if (my_get_expression (&inst.reloc.exp, &str))
- return;
+/* Returns the index into fp_values of a floating point number,
+ or -1 if not in the table. */
-#ifdef OBJ_ELF
- {
- char * save_in;
+static int
+my_get_float_expression (str)
+ char ** str;
+{
+ LITTLENUM_TYPE words[MAX_LITTLENUMS];
+ char * save_in;
+ expressionS exp;
+ int i;
+ int j;
- /* ScottB: February 5, 1998 - Check to see of PLT32 reloc
- required for the instruction. */
+ memset (words, 0, MAX_LITTLENUMS * sizeof (LITTLENUM_TYPE));
+
+ /* Look for a raw floating point number. */
+ if ((save_in = atof_ieee (*str, 'x', words)) != NULL
+ && is_end_of_line[(unsigned char) *save_in])
+ {
+ for (i = 0; i < NUM_FLOAT_VALS; i++)
+ {
+ for (j = 0; j < MAX_LITTLENUMS; j++)
+ {
+ if (words[j] != fp_values[i][j])
+ break;
+ }
+
+ if (j == MAX_LITTLENUMS)
+ {
+ *str = save_in;
+ return i;
+ }
+ }
+ }
+
+ /* Try and parse a more complex expression, this will probably fail
+ unless the code uses a floating point prefix (eg "0f"). */
+ save_in = input_line_pointer;
+ input_line_pointer = *str;
+ if (expression (&exp) == absolute_section
+ && exp.X_op == O_big
+ && exp.X_add_number < 0)
+ {
+ /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
+ Ditto for 15. */
+ if (gen_to_words (words, 5, (long) 15) == 0)
+ {
+ for (i = 0; i < NUM_FLOAT_VALS; i++)
+ {
+ for (j = 0; j < MAX_LITTLENUMS; j++)
+ {
+ if (words[j] != fp_values[i][j])
+ break;
+ }
+
+ if (j == MAX_LITTLENUMS)
+ {
+ *str = input_line_pointer;
+ input_line_pointer = save_in;
+ return i;
+ }
+ }
+ }
+ }
+
+ *str = input_line_pointer;
+ input_line_pointer = save_in;
+ return -1;
+}
+
+/* Return true if anything in the expression is a bignum. */
+
+static int
+walk_no_bignums (sp)
+ symbolS * sp;
+{
+ if (symbol_get_value_expression (sp)->X_op == O_big)
+ return 1;
+
+ if (symbol_get_value_expression (sp)->X_add_symbol)
+ {
+ return (walk_no_bignums (symbol_get_value_expression (sp)->X_add_symbol)
+ || (symbol_get_value_expression (sp)->X_op_symbol
+ && walk_no_bignums (symbol_get_value_expression (sp)->X_op_symbol)));
+ }
+
+ return 0;
+}
+
+static int
+my_get_expression (ep, str)
+ expressionS * ep;
+ char ** str;
+{
+ char * save_in;
+ segT seg;
+
+ save_in = input_line_pointer;
+ input_line_pointer = *str;
+ seg = expression (ep);
+
+#ifdef OBJ_AOUT
+ if (seg != absolute_section
+ && seg != text_section
+ && seg != data_section
+ && seg != bss_section
+ && seg != undefined_section)
+ {
+ inst.error = _("bad_segment");
+ *str = input_line_pointer;
+ input_line_pointer = save_in;
+ return 1;
+ }
+#endif
+
+ /* Get rid of any bignums now, so that we don't generate an error for which
+ we can't establish a line number later on. Big numbers are never valid
+ in instructions, which is where this routine is always called. */
+ if (ep->X_op == O_big
+ || (ep->X_add_symbol
+ && (walk_no_bignums (ep->X_add_symbol)
+ || (ep->X_op_symbol
+ && walk_no_bignums (ep->X_op_symbol)))))
+ {
+ inst.error = _("Invalid constant");
+ *str = input_line_pointer;
+ input_line_pointer = save_in;
+ return 1;
+ }
+
+ *str = input_line_pointer;
+ input_line_pointer = save_in;
+ return 0;
+}
+
+/* UNRESTRICT should be one if <shift> <register> is permitted for this
+ instruction. */
+
+static int
+decode_shift (str, unrestrict)
+ char ** str;
+ int unrestrict;
+{
+ const struct asm_shift_name * shift;
+ char * p;
+ char c;
+
+ skip_whitespace (* str);
+
+ for (p = * str; ISALPHA (* p); p ++)
+ ;
+
+ if (p == * str)
+ {
+ inst.error = _("Shift expression expected");
+ return FAIL;
+ }
+
+ c = * p;
+ * p = '\0';
+ shift = (const struct asm_shift_name *) hash_find (arm_shift_hsh, * str);
+ * p = c;
+
+ if (shift == NULL)
+ {
+ inst.error = _("Shift expression expected");
+ return FAIL;
+ }
+
+ assert (shift->properties->index == shift_properties[shift->properties->index].index);
+
+ if (shift->properties->index == SHIFT_RRX)
+ {
+ * str = p;
+ inst.instruction |= shift->properties->bit_field;
+ return SUCCESS;
+ }
+
+ skip_whitespace (p);
+
+ if (unrestrict && reg_required_here (& p, 8) != FAIL)
+ {
+ inst.instruction |= shift->properties->bit_field | SHIFT_BY_REG;
+ * str = p;
+ return SUCCESS;
+ }
+ else if (! is_immediate_prefix (* p))
+ {
+ inst.error = (unrestrict
+ ? _("shift requires register or #expression")
+ : _("shift requires #expression"));
+ * str = p;
+ return FAIL;
+ }
+
+ inst.error = NULL;
+ p ++;
+
+ if (my_get_expression (& inst.reloc.exp, & p))
+ return FAIL;
+
+ /* Validate some simple #expressions. */
+ if (inst.reloc.exp.X_op == O_constant)
+ {
+ unsigned num = inst.reloc.exp.X_add_number;
+
+ /* Reject operations greater than 32. */
+ if (num > 32
+ /* Reject a shift of 0 unless the mode allows it. */
+ || (num == 0 && shift->properties->allows_0 == 0)
+ /* Reject a shift of 32 unless the mode allows it. */
+ || (num == 32 && shift->properties->allows_32 == 0)
+ )
+ {
+ /* As a special case we allow a shift of zero for
+ modes that do not support it to be recoded as an
+ logical shift left of zero (ie nothing). We warn
+ about this though. */
+ if (num == 0)
+ {
+ as_warn (_("Shift of 0 ignored."));
+ shift = & shift_names[0];
+ assert (shift->properties->index == SHIFT_LSL);
+ }
+ else
+ {
+ inst.error = _("Invalid immediate shift");
+ return FAIL;
+ }
+ }
+
+ /* Shifts of 32 are encoded as 0, for those shifts that
+ support it. */
+ if (num == 32)
+ num = 0;
+
+ inst.instruction |= (num << 7) | shift->properties->bit_field;
+ }
+ else
+ {
+ inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
+ inst.reloc.pc_rel = 0;
+ inst.instruction |= shift->properties->bit_field;
+ }
+
+ * str = p;
+ return SUCCESS;
+}
+
+/* Do those data_ops which can take a negative immediate constant
+ by altering the instuction. A bit of a hack really.
+ MOV <-> MVN
+ AND <-> BIC
+ ADC <-> SBC
+ by inverting the second operand, and
+ ADD <-> SUB
+ CMP <-> CMN
+ by negating the second operand. */
+
+static int
+negate_data_op (instruction, value)
+ unsigned long * instruction;
+ unsigned long value;
+{
+ int op, new_inst;
+ unsigned long negated, inverted;
+
+ negated = validate_immediate (-value);
+ inverted = validate_immediate (~value);
+
+ op = (*instruction >> DATA_OP_SHIFT) & 0xf;
+ switch (op)
+ {
+ /* First negates. */
+ case OPCODE_SUB: /* ADD <-> SUB */
+ new_inst = OPCODE_ADD;
+ value = negated;
+ break;
+
+ case OPCODE_ADD:
+ new_inst = OPCODE_SUB;
+ value = negated;
+ break;
+
+ case OPCODE_CMP: /* CMP <-> CMN */
+ new_inst = OPCODE_CMN;
+ value = negated;
+ break;
+
+ case OPCODE_CMN:
+ new_inst = OPCODE_CMP;
+ value = negated;
+ break;
+
+ /* Now Inverted ops. */
+ case OPCODE_MOV: /* MOV <-> MVN */
+ new_inst = OPCODE_MVN;
+ value = inverted;
+ break;
+
+ case OPCODE_MVN:
+ new_inst = OPCODE_MOV;
+ value = inverted;
+ break;
+
+ case OPCODE_AND: /* AND <-> BIC */
+ new_inst = OPCODE_BIC;
+ value = inverted;
+ break;
+
+ case OPCODE_BIC:
+ new_inst = OPCODE_AND;
+ value = inverted;
+ break;
+
+ case OPCODE_ADC: /* ADC <-> SBC */
+ new_inst = OPCODE_SBC;
+ value = inverted;
+ break;
+
+ case OPCODE_SBC:
+ new_inst = OPCODE_ADC;
+ value = inverted;
+ break;
+
+ /* We cannot do anything. */
+ default:
+ return FAIL;
+ }
+
+ if (value == (unsigned) FAIL)
+ return FAIL;
+
+ *instruction &= OPCODE_MASK;
+ *instruction |= new_inst << DATA_OP_SHIFT;
+ return value;
+}
+
+static int
+data_op2 (str)
+ char ** str;
+{
+ int value;
+ expressionS expr;
+
+ skip_whitespace (* str);
+
+ if (reg_required_here (str, 0) != FAIL)
+ {
+ if (skip_past_comma (str) == SUCCESS)
+ /* Shift operation on register. */
+ return decode_shift (str, NO_SHIFT_RESTRICT);
+
+ return SUCCESS;
+ }
+ else
+ {
+ /* Immediate expression. */
+ if (is_immediate_prefix (**str))
+ {
+ (*str)++;
+ inst.error = NULL;
+
+ if (my_get_expression (&inst.reloc.exp, str))
+ return FAIL;
+
+ if (inst.reloc.exp.X_add_symbol)
+ {
+ inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
+ inst.reloc.pc_rel = 0;
+ }
+ else
+ {
+ if (skip_past_comma (str) == SUCCESS)
+ {
+ /* #x, y -- ie explicit rotation by Y. */
+ if (my_get_expression (&expr, str))
+ return FAIL;
+
+ if (expr.X_op != O_constant)
+ {
+ inst.error = _("Constant expression expected");
+ return FAIL;
+ }
+
+ /* Rotate must be a multiple of 2. */
+ if (((unsigned) expr.X_add_number) > 30
+ || (expr.X_add_number & 1) != 0
+ || ((unsigned) inst.reloc.exp.X_add_number) > 255)
+ {
+ inst.error = _("Invalid constant");
+ return FAIL;
+ }
+ inst.instruction |= INST_IMMEDIATE;
+ inst.instruction |= inst.reloc.exp.X_add_number;
+ inst.instruction |= expr.X_add_number << 7;
+ return SUCCESS;
+ }
+
+ /* Implicit rotation, select a suitable one. */
+ value = validate_immediate (inst.reloc.exp.X_add_number);
+
+ if (value == FAIL)
+ {
+ /* Can't be done. Perhaps the code reads something like
+ "add Rd, Rn, #-n", where "sub Rd, Rn, #n" would be OK. */
+ if ((value = negate_data_op (&inst.instruction,
+ inst.reloc.exp.X_add_number))
+ == FAIL)
+ {
+ inst.error = _("Invalid constant");
+ return FAIL;
+ }
+ }
+
+ inst.instruction |= value;
+ }
+
+ inst.instruction |= INST_IMMEDIATE;
+ return SUCCESS;
+ }
+
+ (*str)++;
+ inst.error = _("Register or shift expression expected");
+ return FAIL;
+ }
+}
+
+static int
+fp_op2 (str)
+ char ** str;
+{
+ skip_whitespace (* str);
+
+ if (fp_reg_required_here (str, 0) != FAIL)
+ return SUCCESS;
+ else
+ {
+ /* Immediate expression. */
+ if (*((*str)++) == '#')
+ {
+ int i;
+
+ inst.error = NULL;
+
+ skip_whitespace (* str);
+
+ /* First try and match exact strings, this is to guarantee
+ that some formats will work even for cross assembly. */
+
+ for (i = 0; fp_const[i]; i++)
+ {
+ if (strncmp (*str, fp_const[i], strlen (fp_const[i])) == 0)
+ {
+ char *start = *str;
+
+ *str += strlen (fp_const[i]);
+ if (is_end_of_line[(unsigned char) **str])
+ {
+ inst.instruction |= i + 8;
+ return SUCCESS;
+ }
+ *str = start;
+ }
+ }
+
+ /* Just because we didn't get a match doesn't mean that the
+ constant isn't valid, just that it is in a format that we
+ don't automatically recognize. Try parsing it with
+ the standard expression routines. */
+ if ((i = my_get_float_expression (str)) >= 0)
+ {
+ inst.instruction |= i + 8;
+ return SUCCESS;
+ }
+
+ inst.error = _("Invalid floating point immediate expression");
+ return FAIL;
+ }
+ inst.error =
+ _("Floating point register or immediate expression expected");
+ return FAIL;
+ }
+}
+
+static void
+do_arit (str, flags)
+ char * str;
+ unsigned long flags;
+{
+ skip_whitespace (str);
+
+ if (reg_required_here (&str, 12) == FAIL
+ || skip_past_comma (&str) == FAIL
+ || reg_required_here (&str, 16) == FAIL
+ || skip_past_comma (&str) == FAIL
+ || data_op2 (&str) == FAIL)
+ {
+ if (!inst.error)
+ inst.error = BAD_ARGS;
+ return;
+ }
+
+ inst.instruction |= flags;
+ end_of_line (str);
+ return;
+}
+
+static void
+do_adr (str, flags)
+ char * str;
+ unsigned long flags;
+{
+ skip_whitespace (str);
+
+ if (reg_required_here (&str, 12) == FAIL
+ || skip_past_comma (&str) == FAIL
+ || my_get_expression (&inst.reloc.exp, &str))
+ {
+ if (!inst.error)
+ inst.error = BAD_ARGS;
+ return;
+ }
+
+ if (flags & 0x00400000)
+ {
+ /* This is a pseudo-op of the form "adrl rd, label" to be converted
+ into a relative address of the form:
+ add rd, pc, #low(label-.-8)"
+ add rd, rd, #high(label-.-8)" */
+ /* Frag hacking will turn this into a sub instruction if the offset turns
+ out to be negative. */
+ inst.reloc.type = BFD_RELOC_ARM_ADRL_IMMEDIATE;
+ inst.reloc.exp.X_add_number -= 8; /* PC relative adjust */
+ inst.reloc.pc_rel = 1;
+ inst.instruction |= flags & ~0x00400000;
+ inst.size = INSN_SIZE * 2;
+ }
+ else
+ {
+ /* This is a pseudo-op of the form "adr rd, label" to be converted
+ into a relative address of the form "add rd, pc, #label-.-8". */
+ /* Frag hacking will turn this into a sub instruction if the offset turns
+ out to be negative. */
+ inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
+ inst.reloc.exp.X_add_number -= 8; /* PC relative adjust. */
+ inst.reloc.pc_rel = 1;
+ inst.instruction |= flags;
+ }
+
+ end_of_line (str);
+}
+
+static void
+do_cmp (str, flags)
+ char * str;
+ unsigned long flags;
+{
+ skip_whitespace (str);
+
+ if (reg_required_here (&str, 16) == FAIL)
+ {
+ if (!inst.error)
+ inst.error = BAD_ARGS;
+ return;
+ }
+
+ if (skip_past_comma (&str) == FAIL
+ || data_op2 (&str) == FAIL)
+ {
+ if (!inst.error)
+ inst.error = BAD_ARGS;
+ return;
+ }
+
+ inst.instruction |= flags;
+ if ((flags & 0x0000f000) == 0)
+ inst.instruction |= CONDS_BIT;
+
+ end_of_line (str);
+ return;
+}
+
+static void
+do_mov (str, flags)
+ char * str;
+ unsigned long flags;
+{
+ skip_whitespace (str);
+
+ if (reg_required_here (&str, 12) == FAIL)
+ {
+ if (!inst.error)
+ inst.error = BAD_ARGS;
+ return;
+ }
+
+ if (skip_past_comma (&str) == FAIL
+ || data_op2 (&str) == FAIL)
+ {
+ if (!inst.error)
+ inst.error = BAD_ARGS;
+ return;
+ }
+
+ inst.instruction |= flags;
+ end_of_line (str);
+ return;
+}
+
+static int
+ldst_extend (str, hwse)
+ char ** str;
+ int hwse;
+{
+ int add = INDEX_UP;
+
+ switch (**str)
+ {
+ case '#':
+ case '$':
+ (*str)++;
+ if (my_get_expression (& inst.reloc.exp, str))
+ return FAIL;
+
+ if (inst.reloc.exp.X_op == O_constant)
+ {
+ int value = inst.reloc.exp.X_add_number;
+
+ if ((hwse && (value < -255 || value > 255))
+ || (value < -4095 || value > 4095))
+ {
+ inst.error = _("address offset too large");
+ return FAIL;
+ }
+
+ if (value < 0)
+ {
+ value = -value;
+ add = 0;
+ }
+
+ /* Halfword and signextension instructions have the
+ immediate value split across bits 11..8 and bits 3..0. */
+ if (hwse)
+ inst.instruction |= (add | HWOFFSET_IMM
+ | ((value >> 4) << 8) | (value & 0xF));
+ else
+ inst.instruction |= add | value;
+ }
+ else
+ {
+ if (hwse)
+ {
+ inst.instruction |= HWOFFSET_IMM;
+ inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM8;
+ }
+ else
+ inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM;
+ inst.reloc.pc_rel = 0;
+ }
+ return SUCCESS;
+
+ case '-':
+ add = 0;
+ /* Fall through. */
+
+ case '+':
+ (*str)++;
+ /* Fall through. */
+
+ default:
+ if (reg_required_here (str, 0) == FAIL)
+ return FAIL;
+
+ if (hwse)
+ inst.instruction |= add;
+ else
+ {
+ inst.instruction |= add | OFFSET_REG;
+ if (skip_past_comma (str) == SUCCESS)
+ return decode_shift (str, SHIFT_RESTRICT);
+ }
+
+ return SUCCESS;
+ }
+}
+
+static void
+do_ldst (str, flags)
+ char * str;
+ unsigned long flags;
+{
+ int halfword = 0;
+ int pre_inc = 0;
+ int conflict_reg;
+ int value;
+
+ /* This is not ideal, but it is the simplest way of dealing with the
+ ARM7T halfword instructions (since they use a different
+ encoding, but the same mnemonic): */
+ halfword = (flags & 0x80000000) != 0;
+ if (halfword)
+ {
+ /* This is actually a load/store of a halfword, or a
+ signed-extension load. */
+ if ((cpu_variant & ARM_EXT_HALFWORD) == 0)
+ {
+ inst.error
+ = _("Processor does not support halfwords or signed bytes");
+ return;
+ }
+
+ inst.instruction = ((inst.instruction & COND_MASK)
+ | (flags & ~COND_MASK));
+
+ flags = 0;
+ }
+
+ skip_whitespace (str);
+
+ if ((conflict_reg = reg_required_here (& str, 12)) == FAIL)
+ {
+ if (!inst.error)
+ inst.error = BAD_ARGS;
+ return;
+ }
+
+ if (skip_past_comma (& str) == FAIL)
+ {
+ inst.error = _("Address expected");
+ return;
+ }
+
+ if (*str == '[')
+ {
+ int reg;
+
+ str++;
+
+ skip_whitespace (str);
+
+ if ((reg = reg_required_here (&str, 16)) == FAIL)
+ return;
+
+ /* Conflicts can occur on stores as well as loads. */
+ conflict_reg = (conflict_reg == reg);
+
+ skip_whitespace (str);
+
+ if (*str == ']')
+ {
+ str ++;
+
+ if (skip_past_comma (&str) == SUCCESS)
+ {
+ /* [Rn],... (post inc) */
+ if (ldst_extend (&str, halfword) == FAIL)
+ return;
+ if (conflict_reg)
+ {
+ if (flags & TRANS_BIT)
+ as_warn (_("Rn and Rd must be different in %s"),
+ ((inst.instruction & LOAD_BIT)
+ ? "LDRT" : "STRT"));
+ else
+ as_warn (_("%s register same as write-back base"),
+ ((inst.instruction & LOAD_BIT)
+ ? _("destination") : _("source")));
+ }
+ }
+ else
+ {
+ /* [Rn] */
+ if (halfword)
+ inst.instruction |= HWOFFSET_IMM;
+
+ skip_whitespace (str);
+
+ if (*str == '!')
+ {
+ if (conflict_reg)
+ as_warn (_("%s register same as write-back base"),
+ ((inst.instruction & LOAD_BIT)
+ ? _("destination") : _("source")));
+ str++;
+ inst.instruction |= WRITE_BACK;
+ }
+
+ flags |= INDEX_UP;
+ if (flags & TRANS_BIT)
+ {
+ if (conflict_reg)
+ as_warn (_("Rn and Rd must be different in %s"),
+ ((inst.instruction & LOAD_BIT)
+ ? "LDRT" : "STRT"));
+ }
+ else
+ pre_inc = 1;
+ }
+ }
+ else
+ {
+ /* [Rn,...] */
+ if (skip_past_comma (&str) == FAIL)
+ {
+ inst.error = _("pre-indexed expression expected");
+ return;
+ }
+
+ pre_inc = 1;
+ if (ldst_extend (&str, halfword) == FAIL)
+ return;
+
+ skip_whitespace (str);
+
+ if (*str++ != ']')
+ {
+ inst.error = _("missing ]");
+ return;
+ }
+
+ skip_whitespace (str);
+
+ if (*str == '!')
+ {
+ if (conflict_reg)
+ as_warn (_("%s register same as write-back base"),
+ ((inst.instruction & LOAD_BIT)
+ ? _("destination") : _("source")));
+ str++;
+ inst.instruction |= WRITE_BACK;
+ }
+ }
+ }
+ else if (*str == '=')
+ {
+ /* Parse an "ldr Rd, =expr" instruction; this is another pseudo op. */
+ str++;
+
+ skip_whitespace (str);
+
+ if (my_get_expression (&inst.reloc.exp, &str))
+ return;
+
+ if (inst.reloc.exp.X_op != O_constant
+ && inst.reloc.exp.X_op != O_symbol)
+ {
+ inst.error = _("Constant expression expected");
+ return;
+ }
+
+ if (inst.reloc.exp.X_op == O_constant)
+ {
+ value = validate_immediate (inst.reloc.exp.X_add_number);
+
+ if (value != FAIL)
+ {
+ /* This can be done with a mov instruction. */
+ inst.instruction &= LITERAL_MASK;
+ inst.instruction |= INST_IMMEDIATE | (OPCODE_MOV << DATA_OP_SHIFT);
+ inst.instruction |= (flags & COND_MASK) | (value & 0xfff);
+ end_of_line (str);
+ return;
+ }
+
+ value = validate_immediate (~ inst.reloc.exp.X_add_number);
+
+ if (value != FAIL)
+ {
+ /* This can be done with a mvn instruction. */
+ inst.instruction &= LITERAL_MASK;
+ inst.instruction |= INST_IMMEDIATE | (OPCODE_MVN << DATA_OP_SHIFT);
+ inst.instruction |= (flags & COND_MASK) | (value & 0xfff);
+ end_of_line (str);
+ return;
+ }
+ }
+
+ /* Insert into literal pool. */
+ if (add_to_lit_pool () == FAIL)
+ {
+ if (!inst.error)
+ inst.error = _("literal pool insertion failed");
+ return;
+ }
+
+ /* Change the instruction exp to point to the pool. */
+ if (halfword)
+ {
+ inst.instruction |= HWOFFSET_IMM;
+ inst.reloc.type = BFD_RELOC_ARM_HWLITERAL;
+ }
+ else
+ inst.reloc.type = BFD_RELOC_ARM_LITERAL;
+
+ inst.reloc.pc_rel = 1;
+ inst.instruction |= (REG_PC << 16);
+ pre_inc = 1;
+ }
+ else
+ {
+ if (my_get_expression (&inst.reloc.exp, &str))
+ return;
+
+ if (halfword)
+ {
+ inst.instruction |= HWOFFSET_IMM;
+ inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM8;
+ }
+ else
+ inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM;
+#ifndef TE_WINCE
+ /* PC rel adjust. */
+ inst.reloc.exp.X_add_number -= 8;
+#endif
+ inst.reloc.pc_rel = 1;
+ inst.instruction |= (REG_PC << 16);
+ pre_inc = 1;
+ }
+
+ if (pre_inc && (flags & TRANS_BIT))
+ inst.error = _("Pre-increment instruction with translate");
+
+ inst.instruction |= flags | (pre_inc ? PRE_INDEX : 0);
+ end_of_line (str);
+ return;
+}
+
+static long
+reg_list (strp)
+ char ** strp;
+{
+ char * str = * strp;
+ long range = 0;
+ int another_range;
+
+ /* We come back here if we get ranges concatenated by '+' or '|'. */
+ do
+ {
+ another_range = 0;
+
+ if (*str == '{')
+ {
+ int in_range = 0;
+ int cur_reg = -1;
+
+ str++;
+ do
+ {
+ int reg;
+
+ skip_whitespace (str);
+
+ if ((reg = reg_required_here (& str, -1)) == FAIL)
+ return FAIL;
+
+ if (in_range)
+ {
+ int i;
+
+ if (reg <= cur_reg)
+ {
+ inst.error = _("Bad range in register list");
+ return FAIL;
+ }
+
+ for (i = cur_reg + 1; i < reg; i++)
+ {
+ if (range & (1 << i))
+ as_tsktsk
+ (_("Warning: Duplicated register (r%d) in register list"),
+ i);
+ else
+ range |= 1 << i;
+ }
+ in_range = 0;
+ }
+
+ if (range & (1 << reg))
+ as_tsktsk (_("Warning: Duplicated register (r%d) in register list"),
+ reg);
+ else if (reg <= cur_reg)
+ as_tsktsk (_("Warning: Register range not in ascending order"));
+
+ range |= 1 << reg;
+ cur_reg = reg;
+ }
+ while (skip_past_comma (&str) != FAIL
+ || (in_range = 1, *str++ == '-'));
+ str--;
+ skip_whitespace (str);
+
+ if (*str++ != '}')
+ {
+ inst.error = _("Missing `}'");
+ return FAIL;
+ }
+ }
+ else
+ {
+ expressionS expr;
+
+ if (my_get_expression (&expr, &str))
+ return FAIL;
+
+ if (expr.X_op == O_constant)
+ {
+ if (expr.X_add_number
+ != (expr.X_add_number & 0x0000ffff))
+ {
+ inst.error = _("invalid register mask");
+ return FAIL;
+ }
+
+ if ((range & expr.X_add_number) != 0)
+ {
+ int regno = range & expr.X_add_number;
+
+ regno &= -regno;
+ regno = (1 << regno) - 1;
+ as_tsktsk
+ (_("Warning: Duplicated register (r%d) in register list"),
+ regno);
+ }
+
+ range |= expr.X_add_number;
+ }
+ else
+ {
+ if (inst.reloc.type != 0)
+ {
+ inst.error = _("expression too complex");
+ return FAIL;
+ }
+
+ memcpy (&inst.reloc.exp, &expr, sizeof (expressionS));
+ inst.reloc.type = BFD_RELOC_ARM_MULTI;
+ inst.reloc.pc_rel = 0;
+ }
+ }
+
+ skip_whitespace (str);
+
+ if (*str == '|' || *str == '+')
+ {
+ str++;
+ another_range = 1;
+ }
+ }
+ while (another_range);
+
+ *strp = str;
+ return range;
+}
+
+static void
+do_ldmstm (str, flags)
+ char * str;
+ unsigned long flags;
+{
+ int base_reg;
+ long range;
+
+ skip_whitespace (str);
+
+ if ((base_reg = reg_required_here (&str, 16)) == FAIL)
+ return;
+
+ if (base_reg == REG_PC)
+ {
+ inst.error = _("r15 not allowed as base register");
+ return;
+ }
+
+ skip_whitespace (str);
+
+ if (*str == '!')
+ {
+ flags |= WRITE_BACK;
+ str++;
+ }
+
+ if (skip_past_comma (&str) == FAIL
+ || (range = reg_list (&str)) == FAIL)
+ {
+ if (! inst.error)
+ inst.error = BAD_ARGS;
+ return;
+ }
+
+ if (*str == '^')
+ {
+ str++;
+ flags |= LDM_TYPE_2_OR_3;
+ }
+
+ inst.instruction |= flags | range;
+ end_of_line (str);
+ return;
+}
+
+static void
+do_swi (str, flags)
+ char * str;
+ unsigned long flags;
+{
+ skip_whitespace (str);
+
+ /* Allow optional leading '#'. */
+ if (is_immediate_prefix (*str))
+ str++;
+
+ if (my_get_expression (& inst.reloc.exp, & str))
+ return;
+
+ inst.reloc.type = BFD_RELOC_ARM_SWI;
+ inst.reloc.pc_rel = 0;
+ inst.instruction |= flags;
+
+ end_of_line (str);
+
+ return;
+}
+
+static void
+do_swap (str, flags)
+ char * str;
+ unsigned long flags;
+{
+ int reg;
+
+ skip_whitespace (str);
+
+ if ((reg = reg_required_here (&str, 12)) == FAIL)
+ return;
+
+ if (reg == REG_PC)
+ {
+ inst.error = _("r15 not allowed in swap");
+ return;
+ }
+
+ if (skip_past_comma (&str) == FAIL
+ || (reg = reg_required_here (&str, 0)) == FAIL)
+ {
+ if (!inst.error)
+ inst.error = BAD_ARGS;
+ return;
+ }
+
+ if (reg == REG_PC)
+ {
+ inst.error = _("r15 not allowed in swap");
+ return;
+ }
+
+ if (skip_past_comma (&str) == FAIL
+ || *str++ != '[')
+ {
+ inst.error = BAD_ARGS;
+ return;
+ }
+
+ skip_whitespace (str);
+
+ if ((reg = reg_required_here (&str, 16)) == FAIL)
+ return;
+
+ if (reg == REG_PC)
+ {
+ inst.error = BAD_PC;
+ return;
+ }
+
+ skip_whitespace (str);
+
+ if (*str++ != ']')
+ {
+ inst.error = _("missing ]");
+ return;
+ }
+
+ inst.instruction |= flags;
+ end_of_line (str);
+ return;
+}
+
+static void
+do_branch (str, flags)
+ char * str;
+ unsigned long flags ATTRIBUTE_UNUSED;
+{
+ if (my_get_expression (&inst.reloc.exp, &str))
+ return;
+
+#ifdef OBJ_ELF
+ {
+ char * save_in;
+
+ /* ScottB: February 5, 1998 - Check to see of PLT32 reloc
+ required for the instruction. */
/* arm_parse_reloc () works on input_line_pointer.
We actually want to parse the operands to the branch instruction
}
static void
-do_cdp (str, flags)
+do_cdp (str, flags)
+ char * str;
+ unsigned long flags ATTRIBUTE_UNUSED;
+{
+ /* Co-processor data operation.
+ Format: CDP{cond} CP#,<expr>,CRd,CRn,CRm{,<expr>} */
+ skip_whitespace (str);
+
+ if (co_proc_number (&str) == FAIL)
+ {
+ if (!inst.error)
+ inst.error = BAD_ARGS;
+ return;
+ }
+
+ if (skip_past_comma (&str) == FAIL
+ || cp_opc_expr (&str, 20,4) == FAIL)
+ {
+ if (!inst.error)
+ inst.error = BAD_ARGS;
+ return;
+ }
+
+ if (skip_past_comma (&str) == FAIL
+ || cp_reg_required_here (&str, 12) == FAIL)
+ {
+ if (!inst.error)
+ inst.error = BAD_ARGS;
+ return;
+ }
+
+ if (skip_past_comma (&str) == FAIL
+ || cp_reg_required_here (&str, 16) == FAIL)
+ {
+ if (!inst.error)
+ inst.error = BAD_ARGS;
+ return;
+ }
+
+ if (skip_past_comma (&str) == FAIL
+ || cp_reg_required_here (&str, 0) == FAIL)
+ {
+ if (!inst.error)
+ inst.error = BAD_ARGS;
+ return;
+ }
+
+ if (skip_past_comma (&str) == SUCCESS)
+ {
+ if (cp_opc_expr (&str, 5, 3) == FAIL)
+ {
+ if (!inst.error)
+ inst.error = BAD_ARGS;
+ return;
+ }
+ }
+
+ end_of_line (str);
+ return;
+}
+
+static void
+do_lstc (str, flags)
+ char * str;
+ unsigned long flags;
+{
+ /* Co-processor register load/store.
+ Format: <LDC|STC{cond}[L] CP#,CRd,<address> */
+
+ skip_whitespace (str);
+
+ if (co_proc_number (&str) == FAIL)
+ {
+ if (!inst.error)
+ inst.error = BAD_ARGS;
+ return;
+ }
+
+ if (skip_past_comma (&str) == FAIL
+ || cp_reg_required_here (&str, 12) == FAIL)
+ {
+ if (!inst.error)
+ inst.error = BAD_ARGS;
+ return;
+ }
+
+ if (skip_past_comma (&str) == FAIL
+ || cp_address_required_here (&str) == FAIL)
+ {
+ if (! inst.error)
+ inst.error = BAD_ARGS;
+ return;
+ }
+
+ inst.instruction |= flags;
+ end_of_line (str);
+ return;
+}
+
+static void
+do_co_reg (str, flags)
+ char * str;
+ unsigned long flags;
+{
+ /* Co-processor register transfer.
+ Format: <MCR|MRC>{cond} CP#,<expr1>,Rd,CRn,CRm{,<expr2>} */
+
+ skip_whitespace (str);
+
+ if (co_proc_number (&str) == FAIL)
+ {
+ if (!inst.error)
+ inst.error = BAD_ARGS;
+ return;
+ }
+
+ if (skip_past_comma (&str) == FAIL
+ || cp_opc_expr (&str, 21, 3) == FAIL)
+ {
+ if (!inst.error)
+ inst.error = BAD_ARGS;
+ return;
+ }
+
+ if (skip_past_comma (&str) == FAIL
+ || reg_required_here (&str, 12) == FAIL)
+ {
+ if (!inst.error)
+ inst.error = BAD_ARGS;
+ return;
+ }
+
+ if (skip_past_comma (&str) == FAIL
+ || cp_reg_required_here (&str, 16) == FAIL)
+ {
+ if (!inst.error)
+ inst.error = BAD_ARGS;
+ return;
+ }
+
+ if (skip_past_comma (&str) == FAIL
+ || cp_reg_required_here (&str, 0) == FAIL)
+ {
+ if (!inst.error)
+ inst.error = BAD_ARGS;
+ return;
+ }
+
+ if (skip_past_comma (&str) == SUCCESS)
+ {
+ if (cp_opc_expr (&str, 5, 3) == FAIL)
+ {
+ if (!inst.error)
+ inst.error = BAD_ARGS;
+ return;
+ }
+ }
+ if (flags)
+ {
+ inst.error = BAD_COND;
+ }
+
+ end_of_line (str);
+ return;
+}
+
+static void
+do_fp_ctrl (str, flags)
+ char * str;
+ unsigned long flags ATTRIBUTE_UNUSED;
+{
+ /* FP control registers.
+ Format: <WFS|RFS|WFC|RFC>{cond} Rn */
+
+ skip_whitespace (str);
+
+ if (reg_required_here (&str, 12) == FAIL)
+ {
+ if (!inst.error)
+ inst.error = BAD_ARGS;
+ return;
+ }
+
+ end_of_line (str);
+ return;
+}
+
+static void
+do_fp_ldst (str, flags)
char * str;
unsigned long flags ATTRIBUTE_UNUSED;
{
- /* Co-processor data operation.
- Format: CDP{cond} CP#,<expr>,CRd,CRn,CRm{,<expr>} */
skip_whitespace (str);
- if (co_proc_number (&str) == FAIL)
+ switch (inst.suffix)
+ {
+ case SUFF_S:
+ break;
+ case SUFF_D:
+ inst.instruction |= CP_T_X;
+ break;
+ case SUFF_E:
+ inst.instruction |= CP_T_Y;
+ break;
+ case SUFF_P:
+ inst.instruction |= CP_T_X | CP_T_Y;
+ break;
+ default:
+ abort ();
+ }
+
+ if (fp_reg_required_here (&str, 12) == FAIL)
{
if (!inst.error)
inst.error = BAD_ARGS;
}
if (skip_past_comma (&str) == FAIL
- || cp_opc_expr (&str, 20,4) == FAIL)
+ || cp_address_required_here (&str) == FAIL)
{
if (!inst.error)
inst.error = BAD_ARGS;
return;
}
- if (skip_past_comma (&str) == FAIL
- || cp_reg_required_here (&str, 12) == FAIL)
+ end_of_line (str);
+}
+
+static void
+do_fp_ldmstm (str, flags)
+ char * str;
+ unsigned long flags;
+{
+ int num_regs;
+
+ skip_whitespace (str);
+
+ if (fp_reg_required_here (&str, 12) == FAIL)
{
- if (!inst.error)
+ if (! inst.error)
inst.error = BAD_ARGS;
return;
}
+ /* Get Number of registers to transfer. */
if (skip_past_comma (&str) == FAIL
- || cp_reg_required_here (&str, 16) == FAIL)
+ || my_get_expression (&inst.reloc.exp, &str))
{
- if (!inst.error)
- inst.error = BAD_ARGS;
+ if (! inst.error)
+ inst.error = _("constant expression expected");
return;
}
- if (skip_past_comma (&str) == FAIL
- || cp_reg_required_here (&str, 0) == FAIL)
+ if (inst.reloc.exp.X_op != O_constant)
{
- if (!inst.error)
- inst.error = BAD_ARGS;
+ inst.error = _("Constant value required for number of registers");
return;
}
- if (skip_past_comma (&str) == SUCCESS)
+ num_regs = inst.reloc.exp.X_add_number;
+
+ if (num_regs < 1 || num_regs > 4)
{
- if (cp_opc_expr (&str, 5, 3) == FAIL)
+ inst.error = _("number of registers must be in the range [1:4]");
+ return;
+ }
+
+ switch (num_regs)
+ {
+ case 1:
+ inst.instruction |= CP_T_X;
+ break;
+ case 2:
+ inst.instruction |= CP_T_Y;
+ break;
+ case 3:
+ inst.instruction |= CP_T_Y | CP_T_X;
+ break;
+ case 4:
+ break;
+ default:
+ abort ();
+ }
+
+ if (flags)
+ {
+ int reg;
+ int write_back;
+ int offset;
+
+ /* The instruction specified "ea" or "fd", so we can only accept
+ [Rn]{!}. The instruction does not really support stacking or
+ unstacking, so we have to emulate these by setting appropriate
+ bits and offsets. */
+ if (skip_past_comma (&str) == FAIL
+ || *str != '[')
{
- if (!inst.error)
+ if (! inst.error)
inst.error = BAD_ARGS;
return;
}
+
+ str++;
+ skip_whitespace (str);
+
+ if ((reg = reg_required_here (&str, 16)) == FAIL)
+ return;
+
+ skip_whitespace (str);
+
+ if (*str != ']')
+ {
+ inst.error = BAD_ARGS;
+ return;
+ }
+
+ str++;
+ if (*str == '!')
+ {
+ write_back = 1;
+ str++;
+ if (reg == REG_PC)
+ {
+ inst.error =
+ _("R15 not allowed as base register with write-back");
+ return;
+ }
+ }
+ else
+ write_back = 0;
+
+ if (flags & CP_T_Pre)
+ {
+ /* Pre-decrement. */
+ offset = 3 * num_regs;
+ if (write_back)
+ flags |= CP_T_WB;
+ }
+ else
+ {
+ /* Post-increment. */
+ if (write_back)
+ {
+ flags |= CP_T_WB;
+ offset = 3 * num_regs;
+ }
+ else
+ {
+ /* No write-back, so convert this into a standard pre-increment
+ instruction -- aesthetically more pleasing. */
+ flags = CP_T_Pre | CP_T_UD;
+ offset = 0;
+ }
+ }
+
+ inst.instruction |= flags | offset;
+ }
+ else if (skip_past_comma (&str) == FAIL
+ || cp_address_required_here (&str) == FAIL)
+ {
+ if (! inst.error)
+ inst.error = BAD_ARGS;
+ return;
}
end_of_line (str);
- return;
}
static void
-do_lstc (str, flags)
+do_fp_dyadic (str, flags)
char * str;
unsigned long flags;
{
- /* Co-processor register load/store.
- Format: <LDC|STC{cond}[L] CP#,CRd,<address> */
-
skip_whitespace (str);
- if (co_proc_number (&str) == FAIL)
+ switch (inst.suffix)
{
- if (!inst.error)
+ case SUFF_S:
+ break;
+ case SUFF_D:
+ inst.instruction |= 0x00000080;
+ break;
+ case SUFF_E:
+ inst.instruction |= 0x00080000;
+ break;
+ default:
+ abort ();
+ }
+
+ if (fp_reg_required_here (&str, 12) == FAIL)
+ {
+ if (! inst.error)
inst.error = BAD_ARGS;
return;
}
if (skip_past_comma (&str) == FAIL
- || cp_reg_required_here (&str, 12) == FAIL)
+ || fp_reg_required_here (&str, 16) == FAIL)
{
- if (!inst.error)
+ if (! inst.error)
inst.error = BAD_ARGS;
return;
}
if (skip_past_comma (&str) == FAIL
- || cp_address_required_here (&str) == FAIL)
+ || fp_op2 (&str) == FAIL)
{
if (! inst.error)
inst.error = BAD_ARGS;
}
static void
-do_co_reg (str, flags)
+do_fp_monadic (str, flags)
char * str;
unsigned long flags;
{
- /* Co-processor register transfer.
- Format: <MCR|MRC>{cond} CP#,<expr1>,Rd,CRn,CRm{,<expr2>} */
-
skip_whitespace (str);
- if (co_proc_number (&str) == FAIL)
+ switch (inst.suffix)
{
- if (!inst.error)
+ case SUFF_S:
+ break;
+ case SUFF_D:
+ inst.instruction |= 0x00000080;
+ break;
+ case SUFF_E:
+ inst.instruction |= 0x00080000;
+ break;
+ default:
+ abort ();
+ }
+
+ if (fp_reg_required_here (&str, 12) == FAIL)
+ {
+ if (! inst.error)
inst.error = BAD_ARGS;
return;
}
if (skip_past_comma (&str) == FAIL
- || cp_opc_expr (&str, 21, 3) == FAIL)
+ || fp_op2 (&str) == FAIL)
{
- if (!inst.error)
+ if (! inst.error)
+ inst.error = BAD_ARGS;
+ return;
+ }
+
+ inst.instruction |= flags;
+ end_of_line (str);
+ return;
+}
+
+static void
+do_fp_cmp (str, flags)
+ char * str;
+ unsigned long flags;
+{
+ skip_whitespace (str);
+
+ if (fp_reg_required_here (&str, 16) == FAIL)
+ {
+ if (! inst.error)
inst.error = BAD_ARGS;
return;
}
if (skip_past_comma (&str) == FAIL
- || reg_required_here (&str, 12) == FAIL)
+ || fp_op2 (&str) == FAIL)
{
- if (!inst.error)
+ if (! inst.error)
inst.error = BAD_ARGS;
return;
}
- if (skip_past_comma (&str) == FAIL
- || cp_reg_required_here (&str, 16) == FAIL)
+ inst.instruction |= flags;
+ end_of_line (str);
+ return;
+}
+
+static void
+do_fp_from_reg (str, flags)
+ char * str;
+ unsigned long flags;
+{
+ skip_whitespace (str);
+
+ switch (inst.suffix)
+ {
+ case SUFF_S:
+ break;
+ case SUFF_D:
+ inst.instruction |= 0x00000080;
+ break;
+ case SUFF_E:
+ inst.instruction |= 0x00080000;
+ break;
+ default:
+ abort ();
+ }
+
+ if (fp_reg_required_here (&str, 16) == FAIL)
{
- if (!inst.error)
+ if (! inst.error)
inst.error = BAD_ARGS;
return;
}
if (skip_past_comma (&str) == FAIL
- || cp_reg_required_here (&str, 0) == FAIL)
+ || reg_required_here (&str, 12) == FAIL)
{
- if (!inst.error)
+ if (! inst.error)
inst.error = BAD_ARGS;
return;
}
- if (skip_past_comma (&str) == SUCCESS)
- {
- if (cp_opc_expr (&str, 5, 3) == FAIL)
- {
- if (!inst.error)
- inst.error = BAD_ARGS;
- return;
- }
- }
- if (flags)
- {
- inst.error = BAD_COND;
- }
-
+ inst.instruction |= flags;
end_of_line (str);
return;
}
static void
-do_fp_ctrl (str, flags)
+do_fp_to_reg (str, flags)
char * str;
- unsigned long flags ATTRIBUTE_UNUSED;
+ unsigned long flags;
{
- /* FP control registers.
- Format: <WFS|RFS|WFC|RFC>{cond} Rn */
-
skip_whitespace (str);
if (reg_required_here (&str, 12) == FAIL)
+ return;
+
+ if (skip_past_comma (&str) == FAIL
+ || fp_reg_required_here (&str, 0) == FAIL)
{
- if (!inst.error)
+ if (! inst.error)
inst.error = BAD_ARGS;
return;
}
+ inst.instruction |= flags;
end_of_line (str);
return;
}
-static void
-do_fp_ldst (str, flags)
- char * str;
- unsigned long flags ATTRIBUTE_UNUSED;
+/* Thumb specific routines. */
+
+/* Parse and validate that a register is of the right form, this saves
+ repeated checking of this information in many similar cases.
+ Unlike the 32-bit case we do not insert the register into the opcode
+ here, since the position is often unknown until the full instruction
+ has been parsed. */
+
+static int
+thumb_reg (strp, hi_lo)
+ char ** strp;
+ int hi_lo;
{
- skip_whitespace (str);
+ int reg;
- switch (inst.suffix)
+ if ((reg = reg_required_here (strp, -1)) == FAIL)
+ return FAIL;
+
+ switch (hi_lo)
{
- case SUFF_S:
- break;
- case SUFF_D:
- inst.instruction |= CP_T_X;
- break;
- case SUFF_E:
- inst.instruction |= CP_T_Y;
+ case THUMB_REG_LO:
+ if (reg > 7)
+ {
+ inst.error = _("lo register required");
+ return FAIL;
+ }
break;
- case SUFF_P:
- inst.instruction |= CP_T_X | CP_T_Y;
+
+ case THUMB_REG_HI:
+ if (reg < 8)
+ {
+ inst.error = _("hi register required");
+ return FAIL;
+ }
break;
+
default:
- abort ();
+ break;
}
- if (fp_reg_required_here (&str, 12) == FAIL)
+ return reg;
+}
+
+/* Parse an add or subtract instruction, SUBTRACT is non-zero if the opcode
+ was SUB. */
+
+static void
+thumb_add_sub (str, subtract)
+ char * str;
+ int subtract;
+{
+ int Rd, Rs, Rn = FAIL;
+
+ skip_whitespace (str);
+
+ if ((Rd = thumb_reg (&str, THUMB_REG_ANY)) == FAIL
+ || skip_past_comma (&str) == FAIL)
{
- if (!inst.error)
+ if (! inst.error)
inst.error = BAD_ARGS;
return;
}
- if (skip_past_comma (&str) == FAIL
- || cp_address_required_here (&str) == FAIL)
+ if (is_immediate_prefix (*str))
{
- if (!inst.error)
- inst.error = BAD_ARGS;
- return;
+ Rs = Rd;
+ str++;
+ if (my_get_expression (&inst.reloc.exp, &str))
+ return;
+ }
+ else
+ {
+ if ((Rs = thumb_reg (&str, THUMB_REG_ANY)) == FAIL)
+ return;
+
+ if (skip_past_comma (&str) == FAIL)
+ {
+ /* Two operand format, shuffle the registers
+ and pretend there are 3. */
+ Rn = Rs;
+ Rs = Rd;
+ }
+ else if (is_immediate_prefix (*str))
+ {
+ str++;
+ if (my_get_expression (&inst.reloc.exp, &str))
+ return;
+ }
+ else if ((Rn = thumb_reg (&str, THUMB_REG_ANY)) == FAIL)
+ return;
+ }
+
+ /* We now have Rd and Rs set to registers, and Rn set to a register or FAIL;
+ for the latter case, EXPR contains the immediate that was found. */
+ if (Rn != FAIL)
+ {
+ /* All register format. */
+ if (Rd > 7 || Rs > 7 || Rn > 7)
+ {
+ if (Rs != Rd)
+ {
+ inst.error = _("dest and source1 must be the same register");
+ return;
+ }
+
+ /* Can't do this for SUB. */
+ if (subtract)
+ {
+ inst.error = _("subtract valid only on lo regs");
+ return;
+ }
+
+ inst.instruction = (T_OPCODE_ADD_HI
+ | (Rd > 7 ? THUMB_H1 : 0)
+ | (Rn > 7 ? THUMB_H2 : 0));
+ inst.instruction |= (Rd & 7) | ((Rn & 7) << 3);
+ }
+ else
+ {
+ inst.instruction = subtract ? T_OPCODE_SUB_R3 : T_OPCODE_ADD_R3;
+ inst.instruction |= Rd | (Rs << 3) | (Rn << 6);
+ }
+ }
+ else
+ {
+ /* Immediate expression, now things start to get nasty. */
+
+ /* First deal with HI regs, only very restricted cases allowed:
+ Adjusting SP, and using PC or SP to get an address. */
+ if ((Rd > 7 && (Rd != REG_SP || Rs != REG_SP))
+ || (Rs > 7 && Rs != REG_SP && Rs != REG_PC))
+ {
+ inst.error = _("invalid Hi register with immediate");
+ return;
+ }
+
+ if (inst.reloc.exp.X_op != O_constant)
+ {
+ /* Value isn't known yet, all we can do is store all the fragments
+ we know about in the instruction and let the reloc hacking
+ work it all out. */
+ inst.instruction = (subtract ? 0x8000 : 0) | (Rd << 4) | Rs;
+ inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
+ }
+ else
+ {
+ int offset = inst.reloc.exp.X_add_number;
+
+ if (subtract)
+ offset = -offset;
+
+ if (offset < 0)
+ {
+ offset = -offset;
+ subtract = 1;
+
+ /* Quick check, in case offset is MIN_INT. */
+ if (offset < 0)
+ {
+ inst.error = _("immediate value out of range");
+ return;
+ }
+ }
+ else
+ subtract = 0;
+
+ if (Rd == REG_SP)
+ {
+ if (offset & ~0x1fc)
+ {
+ inst.error = _("invalid immediate value for stack adjust");
+ return;
+ }
+ inst.instruction = subtract ? T_OPCODE_SUB_ST : T_OPCODE_ADD_ST;
+ inst.instruction |= offset >> 2;
+ }
+ else if (Rs == REG_PC || Rs == REG_SP)
+ {
+ if (subtract
+ || (offset & ~0x3fc))
+ {
+ inst.error = _("invalid immediate for address calculation");
+ return;
+ }
+ inst.instruction = (Rs == REG_PC ? T_OPCODE_ADD_PC
+ : T_OPCODE_ADD_SP);
+ inst.instruction |= (Rd << 8) | (offset >> 2);
+ }
+ else if (Rs == Rd)
+ {
+ if (offset & ~0xff)
+ {
+ inst.error = _("immediate value out of range");
+ return;
+ }
+ inst.instruction = subtract ? T_OPCODE_SUB_I8 : T_OPCODE_ADD_I8;
+ inst.instruction |= (Rd << 8) | offset;
+ }
+ else
+ {
+ if (offset & ~0x7)
+ {
+ inst.error = _("immediate value out of range");
+ return;
+ }
+ inst.instruction = subtract ? T_OPCODE_SUB_I3 : T_OPCODE_ADD_I3;
+ inst.instruction |= Rd | (Rs << 3) | (offset << 6);
+ }
+ }
}
end_of_line (str);
}
static void
-do_fp_ldmstm (str, flags)
+thumb_shift (str, shift)
char * str;
- unsigned long flags;
+ int shift;
{
- int num_regs;
+ int Rd, Rs, Rn = FAIL;
skip_whitespace (str);
- if (fp_reg_required_here (&str, 12) == FAIL)
+ if ((Rd = thumb_reg (&str, THUMB_REG_LO)) == FAIL
+ || skip_past_comma (&str) == FAIL)
{
if (! inst.error)
inst.error = BAD_ARGS;
return;
}
- /* Get Number of registers to transfer. */
- if (skip_past_comma (&str) == FAIL
- || my_get_expression (&inst.reloc.exp, &str))
+ if (is_immediate_prefix (*str))
{
- if (! inst.error)
- inst.error = _("constant expression expected");
- return;
+ /* Two operand immediate format, set Rs to Rd. */
+ Rs = Rd;
+ str ++;
+ if (my_get_expression (&inst.reloc.exp, &str))
+ return;
}
-
- if (inst.reloc.exp.X_op != O_constant)
+ else
{
- inst.error = _("Constant value required for number of registers");
- return;
- }
-
- num_regs = inst.reloc.exp.X_add_number;
+ if ((Rs = thumb_reg (&str, THUMB_REG_LO)) == FAIL)
+ return;
- if (num_regs < 1 || num_regs > 4)
- {
- inst.error = _("number of registers must be in the range [1:4]");
- return;
+ if (skip_past_comma (&str) == FAIL)
+ {
+ /* Two operand format, shuffle the registers
+ and pretend there are 3. */
+ Rn = Rs;
+ Rs = Rd;
+ }
+ else if (is_immediate_prefix (*str))
+ {
+ str++;
+ if (my_get_expression (&inst.reloc.exp, &str))
+ return;
+ }
+ else if ((Rn = thumb_reg (&str, THUMB_REG_LO)) == FAIL)
+ return;
}
- switch (num_regs)
- {
- case 1:
- inst.instruction |= CP_T_X;
- break;
- case 2:
- inst.instruction |= CP_T_Y;
- break;
- case 3:
- inst.instruction |= CP_T_Y | CP_T_X;
- break;
- case 4:
- break;
- default:
- abort ();
- }
+ /* We now have Rd and Rs set to registers, and Rn set to a register or FAIL;
+ for the latter case, EXPR contains the immediate that was found. */
- if (flags)
+ if (Rn != FAIL)
{
- int reg;
- int write_back;
- int offset;
-
- /* The instruction specified "ea" or "fd", so we can only accept
- [Rn]{!}. The instruction does not really support stacking or
- unstacking, so we have to emulate these by setting appropriate
- bits and offsets. */
- if (skip_past_comma (&str) == FAIL
- || *str != '[')
+ if (Rs != Rd)
{
- if (! inst.error)
- inst.error = BAD_ARGS;
+ inst.error = _("source1 and dest must be same register");
return;
}
- str++;
- skip_whitespace (str);
-
- if ((reg = reg_required_here (&str, 16)) == FAIL)
- return;
-
- skip_whitespace (str);
-
- if (*str != ']')
+ switch (shift)
{
- inst.error = BAD_ARGS;
- return;
+ case THUMB_ASR: inst.instruction = T_OPCODE_ASR_R; break;
+ case THUMB_LSL: inst.instruction = T_OPCODE_LSL_R; break;
+ case THUMB_LSR: inst.instruction = T_OPCODE_LSR_R; break;
}
- str++;
- if (*str == '!')
+ inst.instruction |= Rd | (Rn << 3);
+ }
+ else
+ {
+ switch (shift)
{
- write_back = 1;
- str++;
- if (reg == REG_PC)
- {
- inst.error =
- _("R15 not allowed as base register with write-back");
- return;
- }
+ case THUMB_ASR: inst.instruction = T_OPCODE_ASR_I; break;
+ case THUMB_LSL: inst.instruction = T_OPCODE_LSL_I; break;
+ case THUMB_LSR: inst.instruction = T_OPCODE_LSR_I; break;
}
- else
- write_back = 0;
- if (flags & CP_T_Pre)
+ if (inst.reloc.exp.X_op != O_constant)
{
- /* Pre-decrement. */
- offset = 3 * num_regs;
- if (write_back)
- flags |= CP_T_WB;
+ /* Value isn't known yet, create a dummy reloc and let reloc
+ hacking fix it up. */
+ inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
}
else
{
- /* Post-increment. */
- if (write_back)
- {
- flags |= CP_T_WB;
- offset = 3 * num_regs;
- }
- else
+ unsigned shift_value = inst.reloc.exp.X_add_number;
+
+ if (shift_value > 32 || (shift_value == 32 && shift == THUMB_LSL))
{
- /* No write-back, so convert this into a standard pre-increment
- instruction -- aesthetically more pleasing. */
- flags = CP_T_Pre | CP_T_UD;
- offset = 0;
+ inst.error = _("Invalid immediate for shift");
+ return;
}
+
+ /* Shifts of zero are handled by converting to LSL. */
+ if (shift_value == 0)
+ inst.instruction = T_OPCODE_LSL_I;
+
+ /* Shifts of 32 are encoded as a shift of zero. */
+ if (shift_value == 32)
+ shift_value = 0;
+
+ inst.instruction |= shift_value << 6;
}
- inst.instruction |= flags | offset;
- }
- else if (skip_past_comma (&str) == FAIL
- || cp_address_required_here (&str) == FAIL)
- {
- if (! inst.error)
- inst.error = BAD_ARGS;
- return;
+ inst.instruction |= Rd | (Rs << 3);
}
end_of_line (str);
}
static void
-do_fp_dyadic (str, flags)
+thumb_mov_compare (str, move)
char * str;
- unsigned long flags;
+ int move;
{
- skip_whitespace (str);
+ int Rd, Rs = FAIL;
- switch (inst.suffix)
- {
- case SUFF_S:
- break;
- case SUFF_D:
- inst.instruction |= 0x00000080;
- break;
- case SUFF_E:
- inst.instruction |= 0x00080000;
- break;
- default:
- abort ();
- }
+ skip_whitespace (str);
- if (fp_reg_required_here (&str, 12) == FAIL)
+ if ((Rd = thumb_reg (&str, THUMB_REG_ANY)) == FAIL
+ || skip_past_comma (&str) == FAIL)
{
if (! inst.error)
inst.error = BAD_ARGS;
return;
}
- if (skip_past_comma (&str) == FAIL
- || fp_reg_required_here (&str, 16) == FAIL)
+ if (is_immediate_prefix (*str))
{
- if (! inst.error)
- inst.error = BAD_ARGS;
- return;
+ str++;
+ if (my_get_expression (&inst.reloc.exp, &str))
+ return;
+ }
+ else if ((Rs = thumb_reg (&str, THUMB_REG_ANY)) == FAIL)
+ return;
+
+ if (Rs != FAIL)
+ {
+ if (Rs < 8 && Rd < 8)
+ {
+ if (move == THUMB_MOVE)
+ /* A move of two lowregs is encoded as ADD Rd, Rs, #0
+ since a MOV instruction produces unpredictable results. */
+ inst.instruction = T_OPCODE_ADD_I3;
+ else
+ inst.instruction = T_OPCODE_CMP_LR;
+ inst.instruction |= Rd | (Rs << 3);
+ }
+ else
+ {
+ if (move == THUMB_MOVE)
+ inst.instruction = T_OPCODE_MOV_HR;
+ else
+ inst.instruction = T_OPCODE_CMP_HR;
+
+ if (Rd > 7)
+ inst.instruction |= THUMB_H1;
+
+ if (Rs > 7)
+ inst.instruction |= THUMB_H2;
+
+ inst.instruction |= (Rd & 7) | ((Rs & 7) << 3);
+ }
}
+ else
+ {
+ if (Rd > 7)
+ {
+ inst.error = _("only lo regs allowed with immediate");
+ return;
+ }
+
+ if (move == THUMB_MOVE)
+ inst.instruction = T_OPCODE_MOV_I8;
+ else
+ inst.instruction = T_OPCODE_CMP_I8;
+
+ inst.instruction |= Rd << 8;
+
+ if (inst.reloc.exp.X_op != O_constant)
+ inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM;
+ else
+ {
+ unsigned value = inst.reloc.exp.X_add_number;
+
+ if (value > 255)
+ {
+ inst.error = _("invalid immediate");
+ return;
+ }
- if (skip_past_comma (&str) == FAIL
- || fp_op2 (&str) == FAIL)
- {
- if (! inst.error)
- inst.error = BAD_ARGS;
- return;
+ inst.instruction |= value;
+ }
}
- inst.instruction |= flags;
end_of_line (str);
- return;
}
static void
-do_fp_monadic (str, flags)
+thumb_load_store (str, load_store, size)
char * str;
- unsigned long flags;
+ int load_store;
+ int size;
{
- skip_whitespace (str);
+ int Rd, Rb, Ro = FAIL;
- switch (inst.suffix)
- {
- case SUFF_S:
- break;
- case SUFF_D:
- inst.instruction |= 0x00000080;
- break;
- case SUFF_E:
- inst.instruction |= 0x00080000;
- break;
- default:
- abort ();
- }
+ skip_whitespace (str);
- if (fp_reg_required_here (&str, 12) == FAIL)
+ if ((Rd = thumb_reg (&str, THUMB_REG_LO)) == FAIL
+ || skip_past_comma (&str) == FAIL)
{
if (! inst.error)
inst.error = BAD_ARGS;
return;
}
- if (skip_past_comma (&str) == FAIL
- || fp_op2 (&str) == FAIL)
+ if (*str == '[')
{
- if (! inst.error)
- inst.error = BAD_ARGS;
- return;
+ str++;
+ if ((Rb = thumb_reg (&str, THUMB_REG_ANY)) == FAIL)
+ return;
+
+ if (skip_past_comma (&str) != FAIL)
+ {
+ if (is_immediate_prefix (*str))
+ {
+ str++;
+ if (my_get_expression (&inst.reloc.exp, &str))
+ return;
+ }
+ else if ((Ro = thumb_reg (&str, THUMB_REG_LO)) == FAIL)
+ return;
+ }
+ else
+ {
+ inst.reloc.exp.X_op = O_constant;
+ inst.reloc.exp.X_add_number = 0;
+ }
+
+ if (*str != ']')
+ {
+ inst.error = _("expected ']'");
+ return;
+ }
+ str++;
}
+ else if (*str == '=')
+ {
+ /* Parse an "ldr Rd, =expr" instruction; this is another pseudo op. */
+ str++;
- inst.instruction |= flags;
- end_of_line (str);
- return;
-}
+ skip_whitespace (str);
-static void
-do_fp_cmp (str, flags)
- char * str;
- unsigned long flags;
-{
- skip_whitespace (str);
+ if (my_get_expression (& inst.reloc.exp, & str))
+ return;
+
+ end_of_line (str);
+
+ if ( inst.reloc.exp.X_op != O_constant
+ && inst.reloc.exp.X_op != O_symbol)
+ {
+ inst.error = "Constant expression expected";
+ return;
+ }
+
+ if (inst.reloc.exp.X_op == O_constant
+ && ((inst.reloc.exp.X_add_number & ~0xFF) == 0))
+ {
+ /* This can be done with a mov instruction. */
+
+ inst.instruction = T_OPCODE_MOV_I8 | (Rd << 8);
+ inst.instruction |= inst.reloc.exp.X_add_number;
+ return;
+ }
+
+ /* Insert into literal pool. */
+ if (add_to_lit_pool () == FAIL)
+ {
+ if (!inst.error)
+ inst.error = "literal pool insertion failed";
+ return;
+ }
+
+ inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
+ inst.reloc.pc_rel = 1;
+ inst.instruction = T_OPCODE_LDR_PC | (Rd << 8);
+ /* Adjust ARM pipeline offset to Thumb. */
+ inst.reloc.exp.X_add_number += 4;
- if (fp_reg_required_here (&str, 16) == FAIL)
- {
- if (! inst.error)
- inst.error = BAD_ARGS;
return;
}
-
- if (skip_past_comma (&str) == FAIL
- || fp_op2 (&str) == FAIL)
+ else
{
- if (! inst.error)
- inst.error = BAD_ARGS;
+ if (my_get_expression (&inst.reloc.exp, &str))
+ return;
+
+ inst.instruction = T_OPCODE_LDR_PC | (Rd << 8);
+ inst.reloc.pc_rel = 1;
+ inst.reloc.exp.X_add_number -= 4; /* Pipeline offset. */
+ inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
+ end_of_line (str);
return;
}
- inst.instruction |= flags;
- end_of_line (str);
- return;
-}
+ if (Rb == REG_PC || Rb == REG_SP)
+ {
+ if (size != THUMB_WORD)
+ {
+ inst.error = _("byte or halfword not valid for base register");
+ return;
+ }
+ else if (Rb == REG_PC && load_store != THUMB_LOAD)
+ {
+ inst.error = _("R15 based store not allowed");
+ return;
+ }
+ else if (Ro != FAIL)
+ {
+ inst.error = _("Invalid base register for register offset");
+ return;
+ }
-static void
-do_fp_from_reg (str, flags)
- char * str;
- unsigned long flags;
-{
- skip_whitespace (str);
+ if (Rb == REG_PC)
+ inst.instruction = T_OPCODE_LDR_PC;
+ else if (load_store == THUMB_LOAD)
+ inst.instruction = T_OPCODE_LDR_SP;
+ else
+ inst.instruction = T_OPCODE_STR_SP;
- switch (inst.suffix)
- {
- case SUFF_S:
- break;
- case SUFF_D:
- inst.instruction |= 0x00000080;
- break;
- case SUFF_E:
- inst.instruction |= 0x00080000;
- break;
- default:
- abort ();
- }
+ inst.instruction |= Rd << 8;
+ if (inst.reloc.exp.X_op == O_constant)
+ {
+ unsigned offset = inst.reloc.exp.X_add_number;
- if (fp_reg_required_here (&str, 16) == FAIL)
- {
- if (! inst.error)
- inst.error = BAD_ARGS;
- return;
- }
+ if (offset & ~0x3fc)
+ {
+ inst.error = _("invalid offset");
+ return;
+ }
- if (skip_past_comma (&str) == FAIL
- || reg_required_here (&str, 12) == FAIL)
+ inst.instruction |= offset >> 2;
+ }
+ else
+ inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
+ }
+ else if (Rb > 7)
{
- if (! inst.error)
- inst.error = BAD_ARGS;
+ inst.error = _("invalid base register in load/store");
return;
}
+ else if (Ro == FAIL)
+ {
+ /* Immediate offset. */
+ if (size == THUMB_WORD)
+ inst.instruction = (load_store == THUMB_LOAD
+ ? T_OPCODE_LDR_IW : T_OPCODE_STR_IW);
+ else if (size == THUMB_HALFWORD)
+ inst.instruction = (load_store == THUMB_LOAD
+ ? T_OPCODE_LDR_IH : T_OPCODE_STR_IH);
+ else
+ inst.instruction = (load_store == THUMB_LOAD
+ ? T_OPCODE_LDR_IB : T_OPCODE_STR_IB);
- inst.instruction |= flags;
- end_of_line (str);
- return;
-}
+ inst.instruction |= Rd | (Rb << 3);
-static void
-do_fp_to_reg (str, flags)
- char * str;
- unsigned long flags;
-{
- skip_whitespace (str);
+ if (inst.reloc.exp.X_op == O_constant)
+ {
+ unsigned offset = inst.reloc.exp.X_add_number;
- if (reg_required_here (&str, 12) == FAIL)
- return;
+ if (offset & ~(0x1f << size))
+ {
+ inst.error = _("Invalid offset");
+ return;
+ }
+ inst.instruction |= (offset >> size) << 6;
+ }
+ else
+ inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
+ }
+ else
+ {
+ /* Register offset. */
+ if (size == THUMB_WORD)
+ inst.instruction = (load_store == THUMB_LOAD
+ ? T_OPCODE_LDR_RW : T_OPCODE_STR_RW);
+ else if (size == THUMB_HALFWORD)
+ inst.instruction = (load_store == THUMB_LOAD
+ ? T_OPCODE_LDR_RH : T_OPCODE_STR_RH);
+ else
+ inst.instruction = (load_store == THUMB_LOAD
+ ? T_OPCODE_LDR_RB : T_OPCODE_STR_RB);
- if (skip_past_comma (&str) == FAIL
- || fp_reg_required_here (&str, 0) == FAIL)
- {
- if (! inst.error)
- inst.error = BAD_ARGS;
- return;
+ inst.instruction |= Rd | (Rb << 3) | (Ro << 6);
}
- inst.instruction |= flags;
end_of_line (str);
- return;
}
-/* Thumb specific routines. */
-
-/* Parse and validate that a register is of the right form, this saves
- repeated checking of this information in many similar cases.
- Unlike the 32-bit case we do not insert the register into the opcode
- here, since the position is often unknown until the full instruction
- has been parsed. */
+/* Given a register and a register type, return 1 if
+ the register is of the given type, else return 0. */
static int
-thumb_reg (strp, hi_lo)
- char ** strp;
- int hi_lo;
+cirrus_valid_reg (reg, regtype)
+ int reg;
+ enum cirrus_regtype regtype;
{
- int reg;
+ switch (regtype)
+ {
+ case CIRRUS_REGTYPE_ANY:
+ return 1;
- if ((reg = reg_required_here (strp, -1)) == FAIL)
- return FAIL;
+ case CIRRUS_REGTYPE_MVF:
+ return cirrus_mvf_register (reg);
- switch (hi_lo)
- {
- case THUMB_REG_LO:
- if (reg > 7)
- {
- inst.error = _("lo register required");
- return FAIL;
- }
- break;
+ case CIRRUS_REGTYPE_MVFX:
+ return cirrus_mvfx_register (reg);
- case THUMB_REG_HI:
- if (reg < 8)
- {
- inst.error = _("hi register required");
- return FAIL;
- }
- break;
+ case CIRRUS_REGTYPE_MVD:
+ return cirrus_mvd_register (reg);
- default:
- break;
+ case CIRRUS_REGTYPE_MVDX:
+ return cirrus_mvdx_register (reg);
+
+ case CIRRUS_REGTYPE_MVAX:
+ return cirrus_mvax_register (reg);
+
+ case CIRRUS_REGTYPE_DSPSC:
+ return ARM_EXT_MAVERICKsc_register (reg);
}
- return reg;
+ return 0;
}
-/* Parse an add or subtract instruction, SUBTRACT is non-zero if the opcode
- was SUB. */
+/* A register must be given at this point.
-static void
-thumb_add_sub (str, subtract)
- char * str;
- int subtract;
-{
- int Rd, Rs, Rn = FAIL;
+ If the register is a Cirrus register, convert it's reg# appropriately.
- skip_whitespace (str);
+ Shift is the place to put it in inst.instruction.
- if ((Rd = thumb_reg (&str, THUMB_REG_ANY)) == FAIL
- || skip_past_comma (&str) == FAIL)
- {
- if (! inst.error)
- inst.error = BAD_ARGS;
- return;
- }
+ regtype is type register type expected, and is:
+ CIRRUS_REGTYPE_MVF
+ CIRRUS_REGTYPE_MVFX
+ CIRRUS_REGTYPE_MVD
+ CIRRUS_REGTYPE_MVDX
+ CIRRUS_REGTYPE_MVAX
+ CIRRUS_REGTYPE_DSPSC
- if (is_immediate_prefix (*str))
- {
- Rs = Rd;
- str++;
- if (my_get_expression (&inst.reloc.exp, &str))
- return;
- }
- else
+ Restores input start point on err.
+ Returns the reg#, or FAIL. */
+
+static int
+cirrus_reg_required_here (str, shift, regtype)
+ char ** str;
+ int shift;
+ enum cirrus_regtype regtype;
+{
+ static char buff [135]; /* XXX */
+ int reg;
+ char * start = * str;
+
+ if ((reg = arm_reg_parse (str)) != FAIL
+ && (int_register (reg)
+ || cirrus_register (reg)))
{
- if ((Rs = thumb_reg (&str, THUMB_REG_ANY)) == FAIL)
- return;
+ int orig_reg = reg;
- if (skip_past_comma (&str) == FAIL)
+ /* Calculate actual register # for opcode. */
+ if (cirrus_register (reg)
+ && !ARM_EXT_MAVERICKsc_register (reg)) /* Leave this one as is. */
{
- /* Two operand format, shuffle the registers
- and pretend there are 3. */
- Rn = Rs;
- Rs = Rd;
+ if (reg >= 130)
+ reg -= 130;
+ else if (reg >= 110)
+ reg -= 110;
+ else if (reg >= 90)
+ reg -= 90;
+ else if (reg >= 70)
+ reg -= 70;
+ else if (reg >= 50)
+ reg -= 50;
}
- else if (is_immediate_prefix (*str))
+
+ if (!cirrus_valid_reg (orig_reg, regtype))
{
- str++;
- if (my_get_expression (&inst.reloc.exp, &str))
- return;
+ sprintf (buff, _("invalid register type at '%.100s'"), start);
+ inst.error = buff;
+ return FAIL;
}
- else if ((Rn = thumb_reg (&str, THUMB_REG_ANY)) == FAIL)
- return;
+
+ if (shift >= 0)
+ inst.instruction |= reg << shift;
+
+ return orig_reg;
}
- /* We now have Rd and Rs set to registers, and Rn set to a register or FAIL;
- for the latter case, EXPR contains the immediate that was found. */
- if (Rn != FAIL)
- {
- /* All register format. */
- if (Rd > 7 || Rs > 7 || Rn > 7)
- {
- if (Rs != Rd)
- {
- inst.error = _("dest and source1 must be the same register");
- return;
- }
+ /* Restore the start point, we may have got a reg of the wrong class. */
+ *str = start;
+
+ /* In the few cases where we might be able to accept something else
+ this error can be overridden. */
+ sprintf (buff, _("Cirrus register expected, not '%.100s'"), start);
+ inst.error = buff;
+
+ return FAIL;
+}
- /* Can't do this for SUB. */
- if (subtract)
- {
- inst.error = _("subtract valid only on lo regs");
- return;
- }
+/* Cirrus Instructions. */
- inst.instruction = (T_OPCODE_ADD_HI
- | (Rd > 7 ? THUMB_H1 : 0)
- | (Rn > 7 ? THUMB_H2 : 0));
- inst.instruction |= (Rd & 7) | ((Rn & 7) << 3);
- }
- else
- {
- inst.instruction = subtract ? T_OPCODE_SUB_R3 : T_OPCODE_ADD_R3;
- inst.instruction |= Rd | (Rs << 3) | (Rn << 6);
- }
- }
- else
- {
- /* Immediate expression, now things start to get nasty. */
+/* Wrapper functions. */
- /* First deal with HI regs, only very restricted cases allowed:
- Adjusting SP, and using PC or SP to get an address. */
- if ((Rd > 7 && (Rd != REG_SP || Rs != REG_SP))
- || (Rs > 7 && Rs != REG_SP && Rs != REG_PC))
- {
- inst.error = _("invalid Hi register with immediate");
- return;
- }
+static void
+do_c_binops_1 (str, flags)
+ char * str;
+ unsigned long flags;
+{
+ do_c_binops (str, flags, CIRRUS_MODE1);
+}
- if (inst.reloc.exp.X_op != O_constant)
- {
- /* Value isn't known yet, all we can do is store all the fragments
- we know about in the instruction and let the reloc hacking
- work it all out. */
- inst.instruction = (subtract ? 0x8000 : 0) | (Rd << 4) | Rs;
- inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
- }
- else
- {
- int offset = inst.reloc.exp.X_add_number;
+static void
+do_c_binops_2 (str, flags)
+ char * str;
+ unsigned long flags;
+{
+ do_c_binops (str, flags, CIRRUS_MODE2);
+}
- if (subtract)
- offset = -offset;
+static void
+do_c_binops_3 (str, flags)
+ char * str;
+ unsigned long flags;
+{
+ do_c_binops (str, flags, CIRRUS_MODE3);
+}
- if (offset < 0)
- {
- offset = -offset;
- subtract = 1;
+static void
+do_c_triple_4 (str, flags)
+ char * str;
+ unsigned long flags;
+{
+ do_c_triple (str, flags, CIRRUS_MODE4);
+}
- /* Quick check, in case offset is MIN_INT. */
- if (offset < 0)
- {
- inst.error = _("immediate value out of range");
- return;
- }
- }
- else
- subtract = 0;
+static void
+do_c_triple_5 (str, flags)
+ char * str;
+ unsigned long flags;
+{
+ do_c_triple (str, flags, CIRRUS_MODE5);
+}
- if (Rd == REG_SP)
- {
- if (offset & ~0x1fc)
- {
- inst.error = _("invalid immediate value for stack adjust");
- return;
- }
- inst.instruction = subtract ? T_OPCODE_SUB_ST : T_OPCODE_ADD_ST;
- inst.instruction |= offset >> 2;
- }
- else if (Rs == REG_PC || Rs == REG_SP)
- {
- if (subtract
- || (offset & ~0x3fc))
- {
- inst.error = _("invalid immediate for address calculation");
- return;
- }
- inst.instruction = (Rs == REG_PC ? T_OPCODE_ADD_PC
- : T_OPCODE_ADD_SP);
- inst.instruction |= (Rd << 8) | (offset >> 2);
- }
- else if (Rs == Rd)
- {
- if (offset & ~0xff)
- {
- inst.error = _("immediate value out of range");
- return;
- }
- inst.instruction = subtract ? T_OPCODE_SUB_I8 : T_OPCODE_ADD_I8;
- inst.instruction |= (Rd << 8) | offset;
- }
- else
- {
- if (offset & ~0x7)
- {
- inst.error = _("immediate value out of range");
- return;
- }
- inst.instruction = subtract ? T_OPCODE_SUB_I3 : T_OPCODE_ADD_I3;
- inst.instruction |= Rd | (Rs << 3) | (offset << 6);
- }
- }
- }
+static void
+do_c_quad_6 (str, flags)
+ char * str;
+ unsigned long flags;
+{
+ do_c_quad (str, flags, CIRRUS_MODE6);
+}
+
+static void
+do_c_dspsc_1 (str, flags)
+ char * str;
+ unsigned long flags;
+{
+ do_c_dspsc (str, flags, CIRRUS_MODE1);
+}
- end_of_line (str);
+static void
+do_c_dspsc_2 (str, flags)
+ char * str;
+ unsigned long flags;
+{
+ do_c_dspsc (str, flags, CIRRUS_MODE2);
}
static void
-thumb_shift (str, shift)
+do_c_shift_1 (str, flags)
char * str;
- int shift;
+ unsigned long flags;
{
- int Rd, Rs, Rn = FAIL;
+ do_c_shift (str, flags, CIRRUS_MODE1);
+}
+
+static void
+do_c_shift_2 (str, flags)
+ char * str;
+ unsigned long flags;
+{
+ do_c_shift (str, flags, CIRRUS_MODE2);
+}
+
+static void
+do_c_ldst_1 (str, flags)
+ char * str;
+ unsigned long flags;
+{
+ do_c_ldst (str, flags, CIRRUS_MODE1);
+}
+
+static void
+do_c_ldst_2 (str, flags)
+ char * str;
+ unsigned long flags;
+{
+ do_c_ldst (str, flags, CIRRUS_MODE2);
+}
+
+static void
+do_c_ldst_3 (str, flags)
+ char * str;
+ unsigned long flags;
+{
+ do_c_ldst (str, flags, CIRRUS_MODE3);
+}
+
+static void
+do_c_ldst_4 (str, flags)
+ char * str;
+ unsigned long flags;
+{
+ do_c_ldst (str, flags, CIRRUS_MODE4);
+}
+
+/* Isnsn like "foo X,Y". */
+
+static void
+do_c_binops (str, flags, mode)
+ char * str;
+ unsigned long flags;
+ int mode;
+{
+ int shift1, shift2;
+
+ shift1 = mode & 0xff;
+ shift2 = (mode >> 8) & 0xff;
skip_whitespace (str);
- if ((Rd = thumb_reg (&str, THUMB_REG_LO)) == FAIL
- || skip_past_comma (&str) == FAIL)
+ if (cirrus_reg_required_here (&str, shift1, CIRRUS_REGTYPE_ANY) == FAIL
+ || skip_past_comma (&str) == FAIL
+ || cirrus_reg_required_here (&str, shift2, CIRRUS_REGTYPE_ANY) == FAIL)
{
- if (! inst.error)
+ if (!inst.error)
inst.error = BAD_ARGS;
- return;
}
+ else
+ end_of_line (str);
+
+ inst.instruction |= flags;
+ return;
+}
- if (is_immediate_prefix (*str))
+/* Isnsn like "foo X,Y,Z". */
+
+static void
+do_c_triple (str, flags, mode)
+ char * str;
+ unsigned long flags;
+ int mode;
+{
+ int shift1, shift2, shift3;
+
+ shift1 = mode & 0xff;
+ shift2 = (mode >> 8) & 0xff;
+ shift3 = (mode >> 16) & 0xff;
+
+ skip_whitespace (str);
+
+ if (cirrus_reg_required_here (&str, shift1, CIRRUS_REGTYPE_ANY) == FAIL
+ || skip_past_comma (&str) == FAIL
+ || cirrus_reg_required_here (&str, shift2, CIRRUS_REGTYPE_ANY) == FAIL
+ || skip_past_comma (&str) == FAIL
+ || cirrus_reg_required_here (&str, shift3, CIRRUS_REGTYPE_ANY) == FAIL)
{
- /* Two operand immediate format, set Rs to Rd. */
- Rs = Rd;
- str ++;
- if (my_get_expression (&inst.reloc.exp, &str))
- return;
+ if (!inst.error)
+ inst.error = BAD_ARGS;
}
else
- {
- if ((Rs = thumb_reg (&str, THUMB_REG_LO)) == FAIL)
- return;
+ end_of_line (str);
+
+ inst.instruction |= flags;
+ return;
+}
- if (skip_past_comma (&str) == FAIL)
- {
- /* Two operand format, shuffle the registers
- and pretend there are 3. */
- Rn = Rs;
- Rs = Rd;
- }
- else if (is_immediate_prefix (*str))
- {
- str++;
- if (my_get_expression (&inst.reloc.exp, &str))
- return;
- }
- else if ((Rn = thumb_reg (&str, THUMB_REG_LO)) == FAIL)
- return;
- }
+/* Isnsn like "foo W,X,Y,Z".
+ where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
- /* We now have Rd and Rs set to registers, and Rn set to a register or FAIL;
- for the latter case, EXPR contains the immediate that was found. */
+static void
+do_c_quad (str, flags, mode)
+ char * str;
+ unsigned long flags;
+ int mode;
+{
+ int shift1, shift2, shift3, shift4;
+ enum cirrus_regtype rt;
- if (Rn != FAIL)
- {
- if (Rs != Rd)
- {
- inst.error = _("source1 and dest must be same register");
- return;
- }
+ rt = (inst.instruction << 4 == 0xe2006000
+ || inst.instruction << 4 == 0xe3006000) ? CIRRUS_REGTYPE_MVAX
+ : CIRRUS_REGTYPE_MVFX;
- switch (shift)
- {
- case THUMB_ASR: inst.instruction = T_OPCODE_ASR_R; break;
- case THUMB_LSL: inst.instruction = T_OPCODE_LSL_R; break;
- case THUMB_LSR: inst.instruction = T_OPCODE_LSR_R; break;
- }
+ shift1 = mode & 0xff;
+ shift2 = (mode >> 8) & 0xff;
+ shift3 = (mode >> 16) & 0xff;
+ shift4 = (mode >> 24) & 0xff;
- inst.instruction |= Rd | (Rn << 3);
+ skip_whitespace (str);
+
+ if (cirrus_reg_required_here (&str, shift1, CIRRUS_REGTYPE_MVAX) == FAIL
+ || skip_past_comma (&str) == FAIL
+ || cirrus_reg_required_here (&str, shift2, rt) == FAIL
+ || skip_past_comma (&str) == FAIL
+ || cirrus_reg_required_here (&str, shift3, CIRRUS_REGTYPE_MVFX) == FAIL
+ || skip_past_comma (&str) == FAIL
+ || cirrus_reg_required_here (&str, shift4, CIRRUS_REGTYPE_MVFX) == FAIL)
+ {
+ if (!inst.error)
+ inst.error = BAD_ARGS;
}
else
- {
- switch (shift)
- {
- case THUMB_ASR: inst.instruction = T_OPCODE_ASR_I; break;
- case THUMB_LSL: inst.instruction = T_OPCODE_LSL_I; break;
- case THUMB_LSR: inst.instruction = T_OPCODE_LSR_I; break;
- }
+ end_of_line (str);
+
+ inst.instruction |= flags;
+ return;
+}
- if (inst.reloc.exp.X_op != O_constant)
- {
- /* Value isn't known yet, create a dummy reloc and let reloc
- hacking fix it up. */
- inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
- }
- else
- {
- unsigned shift_value = inst.reloc.exp.X_add_number;
+/* cfmvsc32<cond> DSPSC,MVFX[15:0].
+ cfmv32sc<cond> MVFX[15:0],DSPSC. */
- if (shift_value > 32 || (shift_value == 32 && shift == THUMB_LSL))
- {
- inst.error = _("Invalid immediate for shift");
- return;
- }
+static void
+do_c_dspsc (str, flags, mode)
+ char * str;
+ unsigned long flags;
+ int mode;
+{
+ int error;
- /* Shifts of zero are handled by converting to LSL. */
- if (shift_value == 0)
- inst.instruction = T_OPCODE_LSL_I;
+ skip_whitespace (str);
- /* Shifts of 32 are encoded as a shift of zero. */
- if (shift_value == 32)
- shift_value = 0;
+ error = 0;
- inst.instruction |= shift_value << 6;
- }
+ if (mode == CIRRUS_MODE1)
+ {
+ /* cfmvsc32. */
+ if (cirrus_reg_required_here (&str, -1, CIRRUS_REGTYPE_DSPSC) == FAIL
+ || skip_past_comma (&str) == FAIL
+ || cirrus_reg_required_here (&str, 16, CIRRUS_REGTYPE_MVFX) == FAIL)
+ error = 1;
+ }
+ else
+ {
+ /* cfmv32sc. */
+ if (cirrus_reg_required_here (&str, 0, CIRRUS_REGTYPE_MVFX) == FAIL
+ || skip_past_comma (&str) == FAIL
+ || cirrus_reg_required_here (&str, -1, CIRRUS_REGTYPE_DSPSC) == FAIL)
+ error = 1;
+ }
- inst.instruction |= Rd | (Rs << 3);
+ if (error)
+ {
+ if (!inst.error)
+ inst.error = BAD_ARGS;
+ }
+ else
+ {
+ inst.instruction |= flags;
+ end_of_line (str);
}
- end_of_line (str);
+ return;
}
+/* Cirrus shift immediate instructions.
+ cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
+ cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
+
static void
-thumb_mov_compare (str, move)
+do_c_shift (str, flags, mode)
char * str;
- int move;
+ unsigned long flags;
+ int mode;
{
- int Rd, Rs = FAIL;
+ int error;
+ int imm, neg = 0;
skip_whitespace (str);
- if ((Rd = thumb_reg (&str, THUMB_REG_ANY)) == FAIL
- || skip_past_comma (&str) == FAIL)
+ error = 0;
+
+ if (cirrus_reg_required_here (&str, 12,
+ (mode == CIRRUS_MODE1)
+ ? CIRRUS_REGTYPE_MVFX
+ : CIRRUS_REGTYPE_MVDX) == FAIL
+ || skip_past_comma (&str) == FAIL
+ || cirrus_reg_required_here (&str, 16,
+ (mode == CIRRUS_MODE1)
+ ? CIRRUS_REGTYPE_MVFX
+ : CIRRUS_REGTYPE_MVDX) == FAIL
+ || skip_past_comma (&str) == FAIL)
{
- if (! inst.error)
+ if (!inst.error)
inst.error = BAD_ARGS;
return;
}
- if (is_immediate_prefix (*str))
+ /* Calculate the immediate operand.
+ The operand is a 7bit signed number. */
+ skip_whitespace (str);
+
+ if (*str == '#')
+ ++str;
+
+ if (!isdigit (*str) && *str != '-')
{
- str++;
- if (my_get_expression (&inst.reloc.exp, &str))
- return;
+ inst.error = _("expecting immediate, 7bit operand");
+ return;
}
- else if ((Rs = thumb_reg (&str, THUMB_REG_ANY)) == FAIL)
- return;
- if (Rs != FAIL)
+ if (*str == '-')
{
- if (Rs < 8 && Rd < 8)
- {
- if (move == THUMB_MOVE)
- /* A move of two lowregs is encoded as ADD Rd, Rs, #0
- since a MOV instruction produces unpredictable results. */
- inst.instruction = T_OPCODE_ADD_I3;
- else
- inst.instruction = T_OPCODE_CMP_LR;
- inst.instruction |= Rd | (Rs << 3);
- }
- else
- {
- if (move == THUMB_MOVE)
- inst.instruction = T_OPCODE_MOV_HR;
- else
- inst.instruction = T_OPCODE_CMP_HR;
-
- if (Rd > 7)
- inst.instruction |= THUMB_H1;
-
- if (Rs > 7)
- inst.instruction |= THUMB_H2;
-
- inst.instruction |= (Rd & 7) | ((Rs & 7) << 3);
- }
+ neg = 1;
+ ++str;
}
- else
- {
- if (Rd > 7)
- {
- inst.error = _("only lo regs allowed with immediate");
- return;
- }
- if (move == THUMB_MOVE)
- inst.instruction = T_OPCODE_MOV_I8;
- else
- inst.instruction = T_OPCODE_CMP_I8;
+ for (imm = 0; *str && isdigit (*str); ++str)
+ imm = imm * 10 + *str - '0';
- inst.instruction |= Rd << 8;
+ if (imm > 64)
+ {
+ inst.error = _("immediate out of range");
+ return;
+ }
- if (inst.reloc.exp.X_op != O_constant)
- inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM;
- else
- {
- unsigned value = inst.reloc.exp.X_add_number;
+ /* Make negative imm's into 7bit signed numbers. */
+ if (neg)
+ {
+ imm = -imm;
+ imm &= 0x0000007f;
+ }
- if (value > 255)
- {
- inst.error = _("invalid immediate");
- return;
- }
+ /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
+ Bits 5-7 of the insn should have bits 4-6 of the immediate.
+ Bit 4 should be 0. */
+ imm = (imm & 0xf) | ((imm & 0x70) << 1);
- inst.instruction |= value;
- }
- }
+ inst.instruction |= imm;
+ inst.instruction |= flags;
end_of_line (str);
+
+ return;
}
-static void
-thumb_load_store (str, load_store, size)
- char * str;
- int load_store;
- int size;
+static int
+cirrus_parse_offset (str, negative)
+ char ** str;
+ int *negative;
{
- int Rd, Rb, Ro = FAIL;
+ char * p = *str;
+ int offset;
- skip_whitespace (str);
+ *negative = 0;
- if ((Rd = thumb_reg (&str, THUMB_REG_LO)) == FAIL
- || skip_past_comma (&str) == FAIL)
+ skip_whitespace (p);
+
+ if (*p == '#')
+ ++p;
+
+ if (*p == '-')
{
- if (! inst.error)
- inst.error = BAD_ARGS;
- return;
+ *negative = 1;
+ ++p;
}
- if (*str == '[')
+ if (!isdigit (*p))
{
- str++;
- if ((Rb = thumb_reg (&str, THUMB_REG_ANY)) == FAIL)
- return;
+ inst.error = _("offset expected");
+ return 0;
+ }
- if (skip_past_comma (&str) != FAIL)
- {
- if (is_immediate_prefix (*str))
- {
- str++;
- if (my_get_expression (&inst.reloc.exp, &str))
- return;
- }
- else if ((Ro = thumb_reg (&str, THUMB_REG_LO)) == FAIL)
- return;
- }
- else
- {
- inst.reloc.exp.X_op = O_constant;
- inst.reloc.exp.X_add_number = 0;
- }
+ for (offset = 0; *p && isdigit (*p); ++p)
+ offset = offset * 10 + *p - '0';
- if (*str != ']')
- {
- inst.error = _("expected ']'");
- return;
- }
- str++;
- }
- else if (*str == '=')
+ if (offset > 0xff)
{
- /* Parse an "ldr Rd, =expr" instruction; this is another pseudo op. */
- str++;
-
- skip_whitespace (str);
+ inst.error = _("offset out of range");
+ return 0;
+ }
- if (my_get_expression (& inst.reloc.exp, & str))
- return;
+ *str = p;
- end_of_line (str);
+ return *negative ? -offset : offset;
+}
- if ( inst.reloc.exp.X_op != O_constant
- && inst.reloc.exp.X_op != O_symbol)
- {
- inst.error = "Constant expression expected";
- return;
- }
+/* Cirrus load/store instructions.
+ <insn><cond> CRd,[Rn,<offset>]{!}.
+ <insn><cond> CRd,[Rn],<offset>. */
- if (inst.reloc.exp.X_op == O_constant
- && ((inst.reloc.exp.X_add_number & ~0xFF) == 0))
- {
- /* This can be done with a mov instruction. */
+static void
+do_c_ldst (str, flags, mode)
+ char * str;
+ unsigned long flags;
+ int mode;
+{
+ int offset, negative;
+ enum cirrus_regtype rt;
- inst.instruction = T_OPCODE_MOV_I8 | (Rd << 8);
- inst.instruction |= inst.reloc.exp.X_add_number;
- return;
- }
+ rt = mode == CIRRUS_MODE1 ? CIRRUS_REGTYPE_MVF
+ : mode == CIRRUS_MODE2 ? CIRRUS_REGTYPE_MVD
+ : mode == CIRRUS_MODE3 ? CIRRUS_REGTYPE_MVFX
+ : mode == CIRRUS_MODE4 ? CIRRUS_REGTYPE_MVDX : CIRRUS_REGTYPE_MVF;
- /* Insert into literal pool. */
- if (add_to_lit_pool () == FAIL)
- {
- if (!inst.error)
- inst.error = "literal pool insertion failed";
- return;
- }
+ skip_whitespace (str);
- inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
- inst.reloc.pc_rel = 1;
- inst.instruction = T_OPCODE_LDR_PC | (Rd << 8);
- /* Adjust ARM pipeline offset to Thumb. */
- inst.reloc.exp.X_add_number += 4;
+ if (cirrus_reg_required_here (& str, 12, rt) == FAIL
+ || skip_past_comma (& str) == FAIL
+ || *str++ != '['
+ || reg_required_here (& str, 16) == FAIL)
+ goto fail_ldst;
- return;
- }
- else
+ if (skip_past_comma (& str) == SUCCESS)
{
- if (my_get_expression (&inst.reloc.exp, &str))
- return;
+ /* You are here: "<offset>]{!}". */
+ inst.instruction |= PRE_INDEX;
- inst.instruction = T_OPCODE_LDR_PC | (Rd << 8);
- inst.reloc.pc_rel = 1;
- inst.reloc.exp.X_add_number -= 4; /* Pipeline offset. */
- inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
- end_of_line (str);
- return;
- }
+ offset = cirrus_parse_offset (&str, &negative);
- if (Rb == REG_PC || Rb == REG_SP)
- {
- if (size != THUMB_WORD)
+ if (inst.error)
+ return;
+
+ if (*str++ != ']')
{
- inst.error = _("byte or halfword not valid for base register");
+ inst.error = _("missing ]");
return;
}
- else if (Rb == REG_PC && load_store != THUMB_LOAD)
+
+ if (*str == '!')
{
- inst.error = _("R15 based store not allowed");
- return;
+ inst.instruction |= WRITE_BACK;
+ ++str;
}
- else if (Ro != FAIL)
+ }
+ else
+ {
+ /* You are here: "], <offset>". */
+ if (*str++ != ']')
{
- inst.error = _("Invalid base register for register offset");
+ inst.error = _("missing ]");
return;
}
- if (Rb == REG_PC)
- inst.instruction = T_OPCODE_LDR_PC;
- else if (load_store == THUMB_LOAD)
- inst.instruction = T_OPCODE_LDR_SP;
- else
- inst.instruction = T_OPCODE_STR_SP;
-
- inst.instruction |= Rd << 8;
- if (inst.reloc.exp.X_op == O_constant)
- {
- unsigned offset = inst.reloc.exp.X_add_number;
-
- if (offset & ~0x3fc)
- {
- inst.error = _("invalid offset");
- return;
- }
+ if (skip_past_comma (&str) == FAIL
+ || (offset = cirrus_parse_offset (&str, &negative), inst.error))
+ goto fail_ldst;
- inst.instruction |= offset >> 2;
- }
- else
- inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
- }
- else if (Rb > 7)
- {
- inst.error = _("invalid base register in load/store");
- return;
+ inst.instruction |= CP_T_WB; /* Post indexed, set bit W. */
}
- else if (Ro == FAIL)
- {
- /* Immediate offset. */
- if (size == THUMB_WORD)
- inst.instruction = (load_store == THUMB_LOAD
- ? T_OPCODE_LDR_IW : T_OPCODE_STR_IW);
- else if (size == THUMB_HALFWORD)
- inst.instruction = (load_store == THUMB_LOAD
- ? T_OPCODE_LDR_IH : T_OPCODE_STR_IH);
- else
- inst.instruction = (load_store == THUMB_LOAD
- ? T_OPCODE_LDR_IB : T_OPCODE_STR_IB);
-
- inst.instruction |= Rd | (Rb << 3);
-
- if (inst.reloc.exp.X_op == O_constant)
- {
- unsigned offset = inst.reloc.exp.X_add_number;
- if (offset & ~(0x1f << size))
- {
- inst.error = _("Invalid offset");
- return;
- }
- inst.instruction |= (offset >> size) << 6;
- }
- else
- inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
- }
+ if (negative)
+ offset = -offset;
else
- {
- /* Register offset. */
- if (size == THUMB_WORD)
- inst.instruction = (load_store == THUMB_LOAD
- ? T_OPCODE_LDR_RW : T_OPCODE_STR_RW);
- else if (size == THUMB_HALFWORD)
- inst.instruction = (load_store == THUMB_LOAD
- ? T_OPCODE_LDR_RH : T_OPCODE_STR_RH);
- else
- inst.instruction = (load_store == THUMB_LOAD
- ? T_OPCODE_LDR_RB : T_OPCODE_STR_RB);
+ inst.instruction |= CP_T_UD; /* Postive, so set bit U. */
- inst.instruction |= Rd | (Rb << 3) | (Ro << 6);
- }
+ inst.instruction |= offset >> 2;
+ inst.instruction |= flags;
end_of_line (str);
+ return;
+
+fail_ldst:
+ if (!inst.error)
+ inst.error = BAD_ARGS;
+ return;
}
static void
if (Rs != Rd)
{
- inst.error = _("dest and source1 one must be the same register");
+ inst.error = _("dest and source1 must be the same register");
return;
}
Rs = Rn;
strcpy (buf + i, reg_table[entry].name);
for (i = 0; buf[i]; i++)
- buf2[i] = islower (buf[i]) ? toupper (buf[i]) : buf[i];
+ buf2[i] = TOUPPER (buf[i]);
buf2[i] = '\0';
if ((cpu_variant & FPU_ALL) == FPU_NONE) flags |= F_SOFT_FLOAT;
bfd_set_private_flags (stdoutput, flags);
+
+ /* We have run out flags in the COFF header to encode the
+ status of ATPCS support, so instead we create a dummy,
+ empty, debug section called .arm.atpcs. */
+ if (atpcs)
+ {
+ asection * sec;
+
+ sec = bfd_make_section (stdoutput, ".arm.atpcs");
+
+ if (sec != NULL)
+ {
+ bfd_set_section_flags
+ (stdoutput, sec, SEC_READONLY | SEC_DEBUGGING /* | SEC_HAS_CONTENTS */);
+ bfd_set_section_size (stdoutput, sec, 0);
+ bfd_set_section_contents (stdoutput, sec, NULL, 0, 0);
+ }
+ }
}
#endif
}
/* Catch special cases. */
- if (cpu_variant != (FPU_DEFAULT | CPU_DEFAULT))
+ if (cpu_variant & ARM_EXT_XSCALE)
+ mach = bfd_mach_arm_XScale;
+ else if (cpu_variant & ARM_EXT_V5E)
+ mach = bfd_mach_arm_5TE;
+ else if (cpu_variant & ARM_EXT_V5)
{
- if (cpu_variant & (ARM_EXT_V5 & ARM_THUMB))
+ if (cpu_variant & ARM_EXT_THUMB)
mach = bfd_mach_arm_5T;
- else if (cpu_variant & ARM_EXT_V5)
+ else
mach = bfd_mach_arm_5;
- else if (cpu_variant & ARM_THUMB)
+ }
+ else if (cpu_variant & ARM_EXT_HALFWORD)
+ {
+ if (cpu_variant & ARM_EXT_THUMB)
mach = bfd_mach_arm_4T;
- else if ((cpu_variant & ARM_ARCH_V4) == ARM_ARCH_V4)
+ else
mach = bfd_mach_arm_4;
- else if (cpu_variant & ARM_LONGMUL)
- mach = bfd_mach_arm_3M;
}
+ else if (cpu_variant & ARM_EXT_LONGMUL)
+ mach = bfd_mach_arm_3M;
bfd_set_arch_mach (stdoutput, TARGET_ARCH, mach);
}
p++, start++;
#endif
#endif
- if (!isalpha (*p) || !is_name_beginner (*p))
+ if (!ISALPHA (*p) || !is_name_beginner (*p))
return FAIL;
c = *p++;
- while (isalpha (c) || isdigit (c) || c == '_')
+ while (ISALPHA (c) || ISDIGIT (c) || c == '_')
c = *p++;
*--p = 0;
else
{
as_bad_where (fixP->fx_file, fixP->fx_line,
- _("Unable to compute ADRL instructions for PC offset of 0x%x"),
+ _("Unable to compute ADRL instructions for PC offset of 0x%lx"),
value);
break;
}
newval = (newval & 0xf800) | ((value & 0x7fffff) >> 12);
newval2 = (newval2 & 0xf800) | ((value & 0xfff) >> 1);
+ if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX)
+ /* Remove bit zero of the adjusted offset. Bit zero can only be
+ set if the upper insn is at a half-word boundary, since the
+ destination address, an ARM instruction, must always be on a
+ word boundary. The semantics of the BLX (1) instruction, however,
+ are that bit zero in the offset must always be zero, and the
+ corresponding bit one in the target address will be set from bit
+ one of the source address. */
+ newval2 &= ~1;
md_number_to_chars (buf, newval, THUMB_SIZE);
md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
}
if ((value + 2) & ~0x3fe)
as_bad_where (fixP->fx_file, fixP->fx_line,
- _("Invalid offset, value too big (0x%08X)"), value);
+ _("Invalid offset, value too big (0x%08lX)"), value);
/* Round up, since pc will be rounded down. */
newval |= (value + 2) >> 2;
case 9: /* SP load/store. */
if (value & ~0x3fc)
as_bad_where (fixP->fx_file, fixP->fx_line,
- _("Invalid offset, value too big (0x%08X)"), value);
+ _("Invalid offset, value too big (0x%08lX)"), value);
newval |= value >> 2;
break;
case 6: /* Word load/store. */
if (value & ~0x7c)
as_bad_where (fixP->fx_file, fixP->fx_line,
- _("Invalid offset, value too big (0x%08X)"), value);
+ _("Invalid offset, value too big (0x%08lX)"), value);
newval |= value << 4; /* 6 - 2. */
break;
case 7: /* Byte load/store. */
if (value & ~0x1f)
as_bad_where (fixP->fx_file, fixP->fx_line,
- _("Invalid offset, value too big (0x%08X)"), value);
+ _("Invalid offset, value too big (0x%08lX)"), value);
newval |= value << 6;
break;
case 8: /* Halfword load/store. */
if (value & ~0x3e)
as_bad_where (fixP->fx_file, fixP->fx_line,
- _("Invalid offset, value too big (0x%08X)"), value);
+ _("Invalid offset, value too big (0x%08lX)"), value);
newval |= value << 5; /* 6 - 1. */
break;
case BFD_RELOC_ARM_ADRL_IMMEDIATE:
as_bad_where (fixp->fx_file, fixp->fx_line,
- _("ADRL used for a symbol not defined in the same file"),
- fixp->fx_r_type);
+ _("ADRL used for a symbol not defined in the same file"));
return NULL;
case BFD_RELOC_ARM_OFFSET_IMM:
if (thumb_mode)
{
- CONST struct thumb_opcode * opcode;
+ const struct thumb_opcode * opcode;
c = *p;
*p = '\0';
- opcode = (CONST struct thumb_opcode *) hash_find (arm_tops_hsh, str);
+ opcode = (const struct thumb_opcode *) hash_find (arm_tops_hsh, str);
*p = c;
if (opcode)
}
else
{
- CONST struct asm_opcode * opcode;
+ const struct asm_opcode * opcode;
unsigned long cond_code;
inst.size = INSN_SIZE;
c = *q;
*q = '\0';
- opcode = (CONST struct asm_opcode *) hash_find (arm_ops_hsh, str);
+ opcode = (const struct asm_opcode *) hash_find (arm_ops_hsh, str);
*q = c;
if (opcode && opcode->template)
r = q;
if (p - r >= 2)
{
- CONST struct asm_cond *cond;
+ const struct asm_cond *cond;
char d = *(r + 2);
*(r + 2) = '\0';
- cond = (CONST struct asm_cond *) hash_find (arm_cond_hsh, r);
+ cond = (const struct asm_cond *) hash_find (arm_cond_hsh, r);
*(r + 2) = d;
if (cond)
{
before any optional flags. */
if (opcode->comp_suffix && *opcode->comp_suffix != '\0')
{
- CONST char *s = opcode->comp_suffix;
+ const char *s = opcode->comp_suffix;
while (*s)
{
if (r != p)
{
char d;
- CONST struct asm_flg *flag = opcode->flags;
+ const struct asm_flg *flag = opcode->flags;
if (flag)
{
-m[arm]7[xx][t][[d]m] Arm 7 processors
-m[arm]8[10] Arm 8 processors
-m[arm]9[20][tdmi] Arm 9 processors
+ -marm9e Allow Cirrus/DSP instructions
-mstrongarm[110[0]] StrongARM processors
- -m[arm]v[2345[t]] Arm architectures
+ -mxscale XScale processors
+ -m[arm]v[2345[t[e]]] Arm architectures
-mall All (except the ARM1)
FP variants:
-mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
-mapcs-float Pass floats in float regs
-mapcs-reentrant Position independent code
-mthumb-interwork Code supports Arm/Thumb interworking
+ -matpcs ARM/Thumb Procedure Call Standard
-moabi Old ELF ABI */
-CONST char * md_shortopts = "m:k";
+const char * md_shortopts = "m:k";
struct option md_longopts[] =
{
/* Limit assembler to generating only Thumb instructions: */
if (streq (str, "thumb"))
{
- cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_THUMB;
+ cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_EXT_THUMB;
cpu_variant = (cpu_variant & ~FPU_ALL) | FPU_NONE;
thumb_mode = 1;
}
else if (streq (str, "thumb-interwork"))
{
- if ((cpu_variant & ARM_THUMB) == 0)
+ if ((cpu_variant & ARM_EXT_THUMB) == 0)
cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_ARCH_V4T;
#if defined OBJ_COFF || defined OBJ_ELF
support_interwork = true;
as_bad (_("Unrecognised APCS switch -m%s"), arg);
return 0;
}
+
+ if (! strcmp (str, "atpcs"))
+ {
+ atpcs = true;
+ return 1;
+ }
#endif
/* Strip off optional "arm". */
if (! strncmp (str, "arm", 3))
switch (*str)
{
case 't':
- cpu_variant |= (ARM_THUMB | ARM_ARCH_V4);
+ cpu_variant |= ARM_ARCH_V4T;
break;
case 'm':
- cpu_variant |= ARM_LONGMUL;
+ cpu_variant |= ARM_EXT_LONGMUL;
break;
case 'f': /* fe => fp enabled cpu. */
case '8':
if (streq (str, "8") || streq (str, "810"))
cpu_variant = (cpu_variant & ~ARM_ANY)
- | ARM_8 | ARM_ARCH_V4 | ARM_LONGMUL;
+ | ARM_8 | ARM_ARCH_V4;
else
goto bad;
break;
case '9':
if (streq (str, "9"))
cpu_variant = (cpu_variant & ~ARM_ANY)
- | ARM_9 | ARM_ARCH_V4 | ARM_LONGMUL | ARM_THUMB;
+ | ARM_9 | ARM_ARCH_V4T;
else if (streq (str, "920"))
cpu_variant = (cpu_variant & ~ARM_ANY)
- | ARM_9 | ARM_ARCH_V4 | ARM_LONGMUL;
+ | ARM_9 | ARM_ARCH_V4;
else if (streq (str, "920t"))
cpu_variant = (cpu_variant & ~ARM_ANY)
- | ARM_9 | ARM_ARCH_V4 | ARM_LONGMUL | ARM_THUMB;
+ | ARM_9 | ARM_ARCH_V4T;
else if (streq (str, "9tdmi"))
cpu_variant = (cpu_variant & ~ARM_ANY)
- | ARM_9 | ARM_ARCH_V4 | ARM_LONGMUL | ARM_THUMB;
+ | ARM_9 | ARM_ARCH_V4T;
+ else if (streq (str, "9e"))
+ cpu_variant = (cpu_variant & ~ARM_ANY)
+ | ARM_9 | ARM_ARCH_V4T | ARM_EXT_MAVERICK;
else
goto bad;
break;
|| streq (str, "strongarm110")
|| streq (str, "strongarm1100"))
cpu_variant = (cpu_variant & ~ARM_ANY)
- | ARM_8 | ARM_ARCH_V4 | ARM_LONGMUL;
+ | ARM_8 | ARM_ARCH_V4;
else
goto bad;
break;
+ case 'x':
+ if (streq (str, "xscale"))
+ cpu_variant = ARM_9 | ARM_ARCH_XSCALE;
+ else
+ goto bad;
+ break;
+
case 'v':
/* Select variant based on architecture rather than
processor. */
switch (*++str)
{
- case 'm': cpu_variant |= ARM_LONGMUL; break;
+ case 'm': cpu_variant |= ARM_EXT_LONGMUL; break;
case 0: break;
default:
as_bad (_("Invalid architecture variant -m%s"), arg);
break;
case '4':
- cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_ARCH_V4;
+ cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_7 | ARM_ARCH_V4;
switch (*++str)
{
- case 't': cpu_variant |= ARM_THUMB; break;
+ case 't': cpu_variant |= ARM_EXT_THUMB; break;
case 0: break;
default:
as_bad (_("Invalid architecture variant -m%s"), arg);
break;
case '5':
- cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_ARCH_V5;
+ cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_9 | ARM_ARCH_V5;
switch (*++str)
{
- case 't': cpu_variant |= ARM_THUMB; break;
+ case 't': cpu_variant |= ARM_EXT_THUMB; break;
+ case 'e': cpu_variant |= ARM_EXT_V5E; break;
case 0: break;
default:
as_bad (_("Invalid architecture variant -m%s"), arg);
ARM Specific Assembler Options:\n\
-m[arm][<processor name>] select processor variant\n\
-m[arm]v[2|2a|3|3m|4|4t|5[t][e]] select architecture variant\n\
+ -marm9e allow Cirrus/DSP instructions\n\
-mthumb only allow Thumb instructions\n\
-mthumb-interwork mark the assembled code as supporting interworking\n\
-mall allow any instruction\n\
#if defined OBJ_COFF || defined OBJ_ELF
fprintf (fp, _("\
-mapcs-32, -mapcs-26 specify which ARM Procedure Calling Standard to use\n\
+ -matpcs use ARM/Thumb Procedure Calling Standard\n\
-mapcs-float floating point args are passed in FP regs\n\
-mapcs-reentrant the code is position independent/reentrant\n"));
#endif
ARM_SET_INTERWORK (sym, support_interwork);
#endif
- if (label_is_thumb_function_name)
+ /* Note - do not allow local symbols (.Lxxx) to be labeled
+ as Thumb functions. This is because these labels, whilst
+ they exist inside Thumb code, are not the entry points for
+ possible ARM->Thumb calls. Also, these labels can be used
+ as part of a computed goto or switch statement. eg gcc
+ can generate code that looks like this:
+
+ ldr r2, [pc, .Laaa]
+ lsl r3, r3, #2
+ ldr r2, [r3, r2]
+ mov pc, r2
+
+ .Lbbb: .word .Lxxx
+ .Lccc: .word .Lyyy
+ ..etc...
+ .Laaa: .word Lbbb
+
+ The first instruction loads the address of the jump table.
+ The second instruction converts a table index into a byte offset.
+ The third instruction gets the jump address out of the table.
+ The fourth instruction performs the jump.
+
+ If the address stored at .Laaa is that of a symbol which has the
+ Thumb_Func bit set, then the linker will arrange for this address
+ to have the bottom bit set, which in turn would mean that the
+ address computation performed by the third instruction would end
+ up with the bottom bit set. Since the ARM is capable of unaligned
+ word loads, the instruction would then load the incorrect address
+ out of the jump table, and chaos would ensue. */
+ if (label_is_thumb_function_name
+ && (S_GET_NAME (sym)[0] != '.' || S_GET_NAME (sym)[1] != 'L')
+ && (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0)
{
/* When the address of a Thumb function is taken the bottom
bit of that address should be set. This will allow
return false;
}
+#ifdef OBJ_COFF
+/* This is a little hack to help the gas/arm/adrl.s test. It prevents
+ local labels from being added to the output symbol table when they
+ are used with the ADRL pseudo op. The ADRL relocation should always
+ be resolved before the binbary is emitted, so it is safe to say that
+ it is adjustable. */
+
+boolean
+arm_fix_adjustable (fixP)
+ fixS * fixP;
+{
+ if (fixP->fx_r_type == BFD_RELOC_ARM_ADRL_IMMEDIATE)
+ return 1;
+ return 0;
+}
+#endif
#ifdef OBJ_ELF
/* Relocations against Thumb function names must be left unadjusted,
so that the linker can use this information to correctly set the
};
for (i = 0, ip = input_line_pointer;
- i < sizeof (id) && (isalnum (*ip) || ispunct (*ip));
+ i < sizeof (id) && (ISALNUM (*ip) || ISPUNCT (*ip));
i++, ip++)
- id[i] = tolower (*ip);
+ id[i] = TOLOWER (*ip);
for (i = 0; reloc_map[i].str; i++)
if (strncmp (id, reloc_map[i].str, reloc_map[i].len) == 0)
}
#endif /* OBJ_ELF */
+
+/* This is called from HANDLE_ALIGN in write.c. Fill in the contents
+ of an rs_align_code fragment. */
+
+void
+arm_handle_align (fragP)
+ fragS *fragP;
+{
+ static char const arm_noop[4] = { 0x00, 0x00, 0xa0, 0xe1 };
+ static char const thumb_noop[2] = { 0xc0, 0x46 };
+ static char const arm_bigend_noop[4] = { 0xe1, 0xa0, 0x00, 0x00 };
+ static char const thumb_bigend_noop[2] = { 0x46, 0xc0 };
+
+ int bytes, fix, noop_size;
+ char * p;
+ const char * noop;
+
+ if (fragP->fr_type != rs_align_code)
+ return;
+
+ bytes = fragP->fr_next->fr_address - fragP->fr_address - fragP->fr_fix;
+ p = fragP->fr_literal + fragP->fr_fix;
+ fix = 0;
+
+ if (bytes > MAX_MEM_FOR_RS_ALIGN_CODE)
+ bytes &= MAX_MEM_FOR_RS_ALIGN_CODE;
+
+ if (fragP->tc_frag_data)
+ {
+ if (target_big_endian)
+ noop = thumb_bigend_noop;
+ else
+ noop = thumb_noop;
+ noop_size = sizeof (thumb_noop);
+ }
+ else
+ {
+ if (target_big_endian)
+ noop = arm_bigend_noop;
+ else
+ noop = arm_noop;
+ noop_size = sizeof (arm_noop);
+ }
+
+ if (bytes & (noop_size - 1))
+ {
+ fix = bytes & (noop_size - 1);
+ memset (p, 0, fix);
+ p += fix;
+ bytes -= fix;
+ }
+
+ while (bytes >= noop_size)
+ {
+ memcpy (p, noop, noop_size);
+ p += noop_size;
+ bytes -= noop_size;
+ fix += noop_size;
+ }
+
+ fragP->fr_fix += fix;
+ fragP->fr_var = noop_size;
+}
+
+/* Called from md_do_align. Used to create an alignment
+ frag in a code section. */
+
+void
+arm_frag_align_code (n, max)
+ int n;
+ int max;
+{
+ char * p;
+
+ /* We assume that there will never be a requirment
+ to support alignments greater than 32 bytes. */
+ if (max > MAX_MEM_FOR_RS_ALIGN_CODE)
+ as_fatal (_("alignments greater than 32 bytes not supported in .text sections."));
+
+ p = frag_var (rs_align_code,
+ MAX_MEM_FOR_RS_ALIGN_CODE,
+ 1,
+ (relax_substateT) max,
+ (symbolS *) NULL,
+ (offsetT) n,
+ (char *) NULL);
+ *p = 0;
+
+}
+
+/* Perform target specific initialisation of a frag. */
+
+void
+arm_init_frag (fragP)
+ fragS *fragP;
+{
+ /* Record whether this frag is in an ARM or a THUMB area. */
+ fragP->tc_frag_data = thumb_mode;
+}
projects / binutils-gdb.git / blobdiff