/* tc-m68hc11.c -- Assembler code for the Motorola 68HC11 & 68HC12.
- Copyright 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
+ Copyright 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
+ Free Software Foundation, Inc.
Written by Stephane Carrez (stcarrez@nerim.fr)
This file is part of GAS, the GNU Assembler.
GAS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2, or (at your option)
+ the Free Software Foundation; either version 3, or (at your option)
any later version.
GAS is distributed in the hope that it will be useful,
You should have received a copy of the GNU General Public License
along with GAS; see the file COPYING. If not, write to
- the Free Software Foundation, 59 Temple Place - Suite 330,
- Boston, MA 02111-1307, USA. */
+ the Free Software Foundation, 51 Franklin Street - Fifth Floor,
+ Boston, MA 02110-1301, USA. */
-#include <stdio.h>
#include "as.h"
#include "safe-ctype.h"
#include "subsegs.h"
};
/* Local functions. */
-static register_id reg_name_search PARAMS ((char *));
-static register_id register_name PARAMS ((void));
-static int cmp_opcode PARAMS ((struct m68hc11_opcode *,
- struct m68hc11_opcode *));
-static char *print_opcode_format PARAMS ((struct m68hc11_opcode *, int));
-static char *skip_whites PARAMS ((char *));
-static int check_range PARAMS ((long, int));
-static void print_opcode_list PARAMS ((void));
-static void get_default_target PARAMS ((void));
-static void print_insn_format PARAMS ((char *));
-static int get_operand PARAMS ((operand *, int, long));
-static void fixup8 PARAMS ((expressionS *, int, int));
-static void fixup16 PARAMS ((expressionS *, int, int));
-static void fixup24 PARAMS ((expressionS *, int, int));
-static unsigned char convert_branch PARAMS ((unsigned char));
-static char *m68hc11_new_insn PARAMS ((int));
-static void build_dbranch_insn PARAMS ((struct m68hc11_opcode *,
- operand *, int, int));
-static int build_indexed_byte PARAMS ((operand *, int, int));
-static int build_reg_mode PARAMS ((operand *, int));
-
-static struct m68hc11_opcode *find
- PARAMS ((struct m68hc11_opcode_def *, operand *, int));
-static struct m68hc11_opcode *find_opcode
- PARAMS ((struct m68hc11_opcode_def *, operand *, int *));
-static void build_jump_insn
- PARAMS ((struct m68hc11_opcode *, operand *, int, int));
-static void build_insn
- PARAMS ((struct m68hc11_opcode *, operand *, int));
-static int relaxable_symbol PARAMS ((symbolS *));
+static register_id reg_name_search (char *);
+static register_id register_name (void);
+static int cmp_opcode (struct m68hc11_opcode *, struct m68hc11_opcode *);
+static char *print_opcode_format (struct m68hc11_opcode *, int);
+static char *skip_whites (char *);
+static int check_range (long, int);
+static void print_opcode_list (void);
+static void get_default_target (void);
+static void print_insn_format (char *);
+static int get_operand (operand *, int, long);
+static void fixup8 (expressionS *, int, int);
+static void fixup16 (expressionS *, int, int);
+static void fixup24 (expressionS *, int, int);
+static unsigned char convert_branch (unsigned char);
+static char *m68hc11_new_insn (int);
+static void build_dbranch_insn (struct m68hc11_opcode *,
+ operand *, int, int);
+static int build_indexed_byte (operand *, int, int);
+static int build_reg_mode (operand *, int);
+
+static struct m68hc11_opcode *find (struct m68hc11_opcode_def *,
+ operand *, int);
+static struct m68hc11_opcode *find_opcode (struct m68hc11_opcode_def *,
+ operand *, int *);
+static void build_jump_insn (struct m68hc11_opcode *, operand *, int, int);
+static void build_insn (struct m68hc11_opcode *, operand *, int);
+static int relaxable_symbol (symbolS *);
/* Pseudo op to indicate a relax group. */
-static void s_m68hc11_relax PARAMS((int));
+static void s_m68hc11_relax (int);
/* Pseudo op to control the ELF flags. */
-static void s_m68hc11_mode PARAMS ((int));
+static void s_m68hc11_mode (int);
/* Mark the symbols with STO_M68HC12_FAR to indicate the functions
are using 'rtc' for returning. It is necessary to use 'call'
to invoke them. This is also used by the debugger to correctly
find the stack frame. */
-static void s_m68hc11_mark_symbol PARAMS ((int));
+static void s_m68hc11_mark_symbol (int);
/* Controls whether relative branches can be turned into long branches.
When the relative offset is too large, the insn are changed:
jmp L
Setting the flag forbidds this. */
-static short flag_fixed_branchs = 0;
+static short flag_fixed_branches = 0;
/* Force to use long jumps (absolute) instead of relative branches. */
static short flag_force_long_jumps = 0;
static struct hash_control *m68hc11_hash;
/* Current cpu (either cpu6811 or cpu6812). This is determined automagically
- by 'get_default_target' by looking at default BFD vector. This is overriden
+ by 'get_default_target' by looking at default BFD vector. This is overridden
with the -m<cpu> option. */
static int current_architecture = 0;
/* The following pseudo-ops are supported for MRI compatibility. */
{"fcb", cons, 1},
{"fdb", cons, 2},
- {"fcc", stringer, 1},
+ {"fcc", stringer, 8 + 1},
{"rmb", s_space, 0},
- /* Dwarf2 support for Gcc. */
- {"file", (void (*) PARAMS ((int))) dwarf2_directive_file, 0},
- {"loc", dwarf2_directive_loc, 0},
-
/* Motorola ALIS. */
{"xrefb", s_ignore, 0}, /* Same as xref */
struct option md_longopts[] = {
#define OPTION_FORCE_LONG_BRANCH (OPTION_MD_BASE)
- {"force-long-branchs", no_argument, NULL, OPTION_FORCE_LONG_BRANCH},
+ {"force-long-branches", no_argument, NULL, OPTION_FORCE_LONG_BRANCH},
+ {"force-long-branchs", no_argument, NULL, OPTION_FORCE_LONG_BRANCH}, /* Misspelt version kept for backwards compatibility. */
-#define OPTION_SHORT_BRANCHS (OPTION_MD_BASE + 1)
- {"short-branchs", no_argument, NULL, OPTION_SHORT_BRANCHS},
+#define OPTION_SHORT_BRANCHES (OPTION_MD_BASE + 1)
+ {"short-branches", no_argument, NULL, OPTION_SHORT_BRANCHES},
+ {"short-branchs", no_argument, NULL, OPTION_SHORT_BRANCHES}, /* Misspelt version kept for backwards compatibility. */
#define OPTION_STRICT_DIRECT_MODE (OPTION_MD_BASE + 2)
{"strict-direct-mode", no_argument, NULL, OPTION_STRICT_DIRECT_MODE},
options and on the -m68hc11/-m68hc12 option. If no option is specified,
we must get the default. */
const char *
-m68hc11_arch_format ()
+m68hc11_arch_format (void)
{
get_default_target ();
if (current_architecture & cpu6811)
}
enum bfd_architecture
-m68hc11_arch ()
+m68hc11_arch (void)
{
get_default_target ();
if (current_architecture & cpu6811)
}
int
-m68hc11_mach ()
+m68hc11_mach (void)
{
return 0;
}
/* Listing header selected according to cpu. */
const char *
-m68hc11_listing_header ()
+m68hc11_listing_header (void)
{
if (current_architecture & cpu6811)
return "M68HC11 GAS ";
}
void
-md_show_usage (stream)
- FILE *stream;
+md_show_usage (FILE *stream)
{
get_default_target ();
fprintf (stream, _("\
-Motorola 68HC11/68HC12 options:\n\
- -m68hc11 | -m68hc12 specify the processor [default %s]\n\
+Motorola 68HC11/68HC12/68HCS12 options:\n\
+ -m68hc11 | -m68hc12 |\n\
+ -m68hcs12 specify the processor [default %s]\n\
-mshort use 16-bit int ABI (default)\n\
-mlong use 32-bit int ABI\n\
-mshort-double use 32-bit double ABI\n\
-mlong-double use 64-bit double ABI (default)\n\
- --force-long-branchs always turn relative branchs into absolute ones\n\
- -S,--short-branchs do not turn relative branchs into absolute ones\n\
+ --force-long-branches always turn relative branches into absolute ones\n\
+ -S,--short-branches do not turn relative branches into absolute ones\n\
when the offset is out of range\n\
--strict-direct-mode do not turn the direct mode into extended mode\n\
when the instruction does not support direct mode\n\
/* Try to identify the default target based on the BFD library. */
static void
-get_default_target ()
+get_default_target (void)
{
const bfd_target *target;
bfd abfd;
}
void
-m68hc11_print_statistics (file)
- FILE *file;
+m68hc11_print_statistics (FILE *file)
{
int i;
struct m68hc11_opcode_def *opc;
}
int
-md_parse_option (c, arg)
- int c;
- char *arg;
+md_parse_option (int c, char *arg)
{
get_default_target ();
switch (c)
{
/* -S means keep external to 2 bit offset rather than 16 bit one. */
- case OPTION_SHORT_BRANCHS:
+ case OPTION_SHORT_BRANCHES:
case 'S':
- flag_fixed_branchs = 1;
+ flag_fixed_branches = 1;
break;
case OPTION_FORCE_LONG_BRANCH:
current_architecture = cpu6811;
else if (strcasecmp (arg, "68hc12") == 0)
current_architecture = cpu6812;
+ else if (strcasecmp (arg, "68hcs12") == 0)
+ current_architecture = cpu6812 | cpu6812s;
else
as_bad (_("Option `%s' is not recognized."), arg);
break;
}
\f
symbolS *
-md_undefined_symbol (name)
- char *name ATTRIBUTE_UNUSED;
+md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
{
return 0;
}
-/* Equal to MAX_PRECISION in atof-ieee.c. */
-#define MAX_LITTLENUMS 6
-
-/* Turn a string in input_line_pointer into a floating point constant
- of type TYPE, and store the appropriate bytes in *LITP. The number
- of LITTLENUMS emitted is stored in *SIZEP. An error message is
- returned, or NULL on OK. */
char *
-md_atof (type, litP, sizeP)
- char type;
- char *litP;
- int *sizeP;
+md_atof (int type, char *litP, int *sizeP)
{
- int prec;
- LITTLENUM_TYPE words[MAX_LITTLENUMS];
- LITTLENUM_TYPE *wordP;
- char *t;
-
- switch (type)
- {
- case 'f':
- case 'F':
- case 's':
- case 'S':
- prec = 2;
- break;
-
- case 'd':
- case 'D':
- case 'r':
- case 'R':
- prec = 4;
- break;
-
- case 'x':
- case 'X':
- prec = 6;
- break;
-
- case 'p':
- case 'P':
- prec = 6;
- break;
-
- default:
- *sizeP = 0;
- return _("Bad call to MD_ATOF()");
- }
- t = atof_ieee (input_line_pointer, type, words);
- if (t)
- input_line_pointer = t;
-
- *sizeP = prec * sizeof (LITTLENUM_TYPE);
- for (wordP = words; prec--;)
- {
- md_number_to_chars (litP, (long) (*wordP++), sizeof (LITTLENUM_TYPE));
- litP += sizeof (LITTLENUM_TYPE);
- }
- return 0;
+ return ieee_md_atof (type, litP, sizeP, TRUE);
}
valueT
-md_section_align (seg, addr)
- asection *seg;
- valueT addr;
+md_section_align (asection *seg, valueT addr)
{
int align = bfd_get_section_alignment (stdoutput, seg);
return ((addr + (1 << align) - 1) & (-1 << align));
}
static int
-cmp_opcode (op1, op2)
- struct m68hc11_opcode *op1;
- struct m68hc11_opcode *op2;
+cmp_opcode (struct m68hc11_opcode *op1, struct m68hc11_opcode *op2)
{
return strcmp (op1->name, op2->name);
}
(sorted on the names) with the M6811 opcode table
(from opcode library). */
void
-md_begin ()
+md_begin (void)
{
char *prev_name = "";
struct m68hc11_opcode *opcodes;
}
}
qsort (opcodes, num_opcodes, sizeof (struct m68hc11_opcode),
- (int (*) PARAMS ((const PTR, const PTR))) cmp_opcode);
+ (int (*) (const void*, const void*)) cmp_opcode);
opc = (struct m68hc11_opcode_def *)
xmalloc (num_opcodes * sizeof (struct m68hc11_opcode_def));
opc->nb_modes = 0;
opc->opcode = opcodes;
opc->used = 0;
- hash_insert (m68hc11_hash, opcodes->name, (char *) opc);
+ hash_insert (m68hc11_hash, opcodes->name, opc);
}
opc->nb_modes++;
opc->format |= opcodes->format;
}
void
-m68hc11_init_after_args ()
+m68hc11_init_after_args (void)
{
}
\f
When example is true, this generates an example of operand. This is used
to give an example and also to generate a test. */
static char *
-print_opcode_format (opcode, example)
- struct m68hc11_opcode *opcode;
- int example;
+print_opcode_format (struct m68hc11_opcode *opcode, int example)
{
static char buf[128];
int format = opcode->format;
/* Prints the list of instructions with the possible operands. */
static void
-print_opcode_list ()
+print_opcode_list (void)
{
int i;
char *prev_name = "";
instruction is not correct. Instruction format is printed as an
error message. */
static void
-print_insn_format (name)
- char *name;
+print_insn_format (char *name)
{
struct m68hc11_opcode_def *opc;
struct m68hc11_opcode *opcode;
/* reg_name_search() finds the register number given its name.
Returns the register number or REG_NONE on failure. */
static register_id
-reg_name_search (name)
- char *name;
+reg_name_search (char *name)
{
if (strcasecmp (name, "x") == 0 || strcasecmp (name, "ix") == 0)
return REG_X;
}
static char *
-skip_whites (p)
- char *p;
+skip_whites (char *p)
{
while (*p == ' ' || *p == '\t')
p++;
/* Check the string at input_line_pointer
to see if it is a valid register name. */
static register_id
-register_name ()
+register_name (void)
{
register_id reg_number;
char c, *p = input_line_pointer;
return reg_number;
}
+#define M6811_OP_CALL_ADDR 0x00800000
+#define M6811_OP_PAGE_ADDR 0x04000000
/* Parse a string of operands and return an array of expressions.
[D,r] M6811_OP_D_IDX M6812_OP_REG O_register O_register
[n,r] M6811_OP_D_IDX_2 M6812_OP_REG O_constant O_register */
static int
-get_operand (oper, which, opmode)
- operand *oper;
- int which;
- long opmode;
+get_operand (operand *oper, int which, long opmode)
{
char *p = input_line_pointer;
int mode;
p += 3;
mode |= M6811_OP_LOW_ADDR;
}
+ /* %page modifier is used to obtain only the page number
+ of the address of a function. */
+ else if (strncmp (p, "%page", 5) == 0)
+ {
+ p += 5;
+ mode |= M6811_OP_PAGE_ADDR;
+ }
+
+ /* %addr modifier is used to obtain the physical address part
+ of the function (16-bit). For 68HC12 the function will be
+ mapped in the 16K window at 0x8000 and the value will be
+ within that window (although the function address may not fit
+ in 16-bit). See bfd/elf32-m68hc12.c for the translation. */
+ else if (strncmp (p, "%addr", 5) == 0)
+ {
+ p += 5;
+ mode |= M6811_OP_CALL_ADDR;
+ }
}
else if (*p == '.' && (p[1] == '+' || p[1] == '-'))
{
as_bad (_("Spurious `,' or bad indirect register addressing mode."));
return -1;
}
+ /* Handle 68HC12 page specification in 'call foo,%page(bar)'. */
+ else if ((opmode & M6812_OP_PAGE) && strncmp (p, "%page", 5) == 0)
+ {
+ p += 5;
+ mode = M6811_OP_PAGE_ADDR | M6812_OP_PAGE | M6811_OP_IND16;
+ }
input_line_pointer = p;
if (mode == M6811_OP_NONE || mode == M6812_OP_D_IDX)
/* Checks that the number 'num' fits for a given mode. */
static int
-check_range (num, mode)
- long num;
- int mode;
+check_range (long num, int mode)
{
/* Auto increment and decrement are ok for [-8..8] without 0. */
if (mode & M6812_AUTO_INC_DEC)
/* Put a 1 byte expression described by 'oper'. If this expression contains
unresolved symbols, generate an 8-bit fixup. */
static void
-fixup8 (oper, mode, opmode)
- expressionS *oper;
- int mode;
- int opmode;
+fixup8 (expressionS *oper, int mode, int opmode)
{
char *f;
}
else
{
- /* Now create an 8-bit fixup. If there was some %hi or %lo
- modifier, generate the reloc accordingly. */
- fix_new_exp (frag_now, f - frag_now->fr_literal, 1,
- oper, FALSE,
- ((opmode & M6811_OP_HIGH_ADDR)
- ? BFD_RELOC_M68HC11_HI8
- : ((opmode & M6811_OP_LOW_ADDR)
- ? BFD_RELOC_M68HC11_LO8
- : ((mode & M6812_OP_PAGE)
- ? BFD_RELOC_M68HC11_PAGE : BFD_RELOC_8))));
+ fixS *fixp;
+ int reloc;
+
+ /* Now create an 8-bit fixup. If there was some %hi, %lo
+ or %page modifier, generate the reloc accordingly. */
+ if (opmode & M6811_OP_HIGH_ADDR)
+ reloc = BFD_RELOC_M68HC11_HI8;
+ else if (opmode & M6811_OP_LOW_ADDR)
+ reloc = BFD_RELOC_M68HC11_LO8;
+ else if (opmode & M6811_OP_PAGE_ADDR)
+ reloc = BFD_RELOC_M68HC11_PAGE;
+ else
+ reloc = BFD_RELOC_8;
+
+ fixp = fix_new_exp (frag_now, f - frag_now->fr_literal, 1,
+ oper, FALSE, reloc);
+ if (reloc != BFD_RELOC_8)
+ fixp->fx_no_overflow = 1;
}
number_to_chars_bigendian (f, 0, 1);
}
/* Put a 2 byte expression described by 'oper'. If this expression contains
unresolved symbols, generate a 16-bit fixup. */
static void
-fixup16 (oper, mode, opmode)
- expressionS *oper;
- int mode;
- int opmode ATTRIBUTE_UNUSED;
+fixup16 (expressionS *oper, int mode, int opmode ATTRIBUTE_UNUSED)
{
char *f;
else if (oper->X_op != O_register)
{
fixS *fixp;
+ int reloc;
+
+ if ((opmode & M6811_OP_CALL_ADDR) && (mode & M6811_OP_IMM16))
+ reloc = BFD_RELOC_M68HC11_LO16;
+ else if (mode & M6812_OP_JUMP_REL16)
+ reloc = BFD_RELOC_16_PCREL;
+ else if (mode & M6812_OP_PAGE)
+ reloc = BFD_RELOC_M68HC11_LO16;
+ else
+ reloc = BFD_RELOC_16;
/* Now create a 16-bit fixup. */
fixp = fix_new_exp (frag_now, f - frag_now->fr_literal, 2,
oper,
- (mode & M6812_OP_JUMP_REL16 ? TRUE : FALSE),
- (mode & M6812_OP_JUMP_REL16
- ? BFD_RELOC_16_PCREL
- : (mode & M6812_OP_PAGE)
- ? BFD_RELOC_M68HC11_LO16 : BFD_RELOC_16));
+ reloc == BFD_RELOC_16_PCREL,
+ reloc);
number_to_chars_bigendian (f, 0, 2);
- if (mode & M6812_OP_JUMP_REL16)
+ if (reloc == BFD_RELOC_16_PCREL)
fixp->fx_pcrel_adjust = 2;
+ if (reloc == BFD_RELOC_M68HC11_LO16)
+ fixp->fx_no_overflow = 1;
}
else
{
/* Put a 3 byte expression described by 'oper'. If this expression contains
unresolved symbols, generate a 24-bit fixup. */
static void
-fixup24 (oper, mode, opmode)
- expressionS *oper;
- int mode;
- int opmode ATTRIBUTE_UNUSED;
+fixup24 (expressionS *oper, int mode, int opmode ATTRIBUTE_UNUSED)
{
char *f;
fixS *fixp;
/* Now create a 24-bit fixup. */
- fixp = fix_new_exp (frag_now, f - frag_now->fr_literal, 2,
+ fixp = fix_new_exp (frag_now, f - frag_now->fr_literal, 3,
oper, FALSE, BFD_RELOC_M68HC11_24);
number_to_chars_bigendian (f, 0, 3);
}
/* Translate the short branch/bsr instruction into a long branch. */
static unsigned char
-convert_branch (code)
- unsigned char code;
+convert_branch (unsigned char code)
{
if (IS_OPCODE (code, M6812_BSR))
return M6812_JSR;
/* Start a new insn that contains at least 'size' bytes. Record the
line information of that insn in the dwarf2 debug sections. */
static char *
-m68hc11_new_insn (size)
- int size;
+m68hc11_new_insn (int size)
{
char *f;
/* Builds a jump instruction (bra, bcc, bsr). */
static void
-build_jump_insn (opcode, operands, nb_operands, jmp_mode)
- struct m68hc11_opcode *opcode;
- operand operands[];
- int nb_operands;
- int jmp_mode;
+build_jump_insn (struct m68hc11_opcode *opcode, operand operands[],
+ int nb_operands, int jmp_mode)
{
unsigned char code;
char *f;
fragS *frag;
int where;
- /* The relative branch convertion is not supported for
+ /* The relative branch conversion is not supported for
brclr and brset. */
- assert ((opcode->format & M6811_OP_BITMASK) == 0);
- assert (nb_operands == 1);
- assert (operands[0].reg1 == REG_NONE && operands[0].reg2 == REG_NONE);
+ gas_assert ((opcode->format & M6811_OP_BITMASK) == 0);
+ gas_assert (nb_operands == 1);
+ gas_assert (operands[0].reg1 == REG_NONE && operands[0].reg2 == REG_NONE);
code = opcode->opcode;
if ((jmp_mode == 0 && flag_force_long_jumps)
|| (operands[0].exp.X_op == O_constant
&& (!check_range (n, opcode->format) &&
- (jmp_mode == 1 || flag_fixed_branchs == 0))))
+ (jmp_mode == 1 || flag_fixed_branches == 0))))
{
frag = frag_now;
where = frag_now_fix ();
- fix_new (frag_now, frag_now_fix (), 1,
+ fix_new (frag_now, frag_now_fix (), 0,
&abs_symbol, 0, 1, BFD_RELOC_M68HC11_RL_JUMP);
if (code == M6811_BSR || code == M6811_BRA || code == M6812_BSR)
frag = frag_now;
where = frag_now_fix ();
- fix_new (frag_now, frag_now_fix (), 1,
+ fix_new (frag_now, frag_now_fix (), 0,
&abs_symbol, 0, 1, BFD_RELOC_M68HC11_RL_JUMP);
f = m68hc11_new_insn (2);
frag = frag_now;
where = frag_now_fix ();
- fix_new (frag_now, frag_now_fix (), 1,
+ fix_new (frag_now, frag_now_fix (), 0,
&abs_symbol, 0, 1, BFD_RELOC_M68HC11_RL_JUMP);
/* Branch offset must fit in 8-bits, don't do some relax. */
- if (jmp_mode == 0 && flag_fixed_branchs)
+ if (jmp_mode == 0 && flag_fixed_branches)
{
opcode = m68hc11_new_insn (1);
number_to_chars_bigendian (opcode, code, 1);
/* Builds a dbne/dbeq/tbne/tbeq instruction. */
static void
-build_dbranch_insn (opcode, operands, nb_operands, jmp_mode)
- struct m68hc11_opcode *opcode;
- operand operands[];
- int nb_operands;
- int jmp_mode;
+build_dbranch_insn (struct m68hc11_opcode *opcode, operand operands[],
+ int nb_operands, int jmp_mode)
{
unsigned char code;
char *f;
unsigned long n;
- /* The relative branch convertion is not supported for
+ /* The relative branch conversion is not supported for
brclr and brset. */
- assert ((opcode->format & M6811_OP_BITMASK) == 0);
- assert (nb_operands == 2);
- assert (operands[0].reg1 != REG_NONE);
+ gas_assert ((opcode->format & M6811_OP_BITMASK) == 0);
+ gas_assert (nb_operands == 2);
+ gas_assert (operands[0].reg1 != REG_NONE);
code = opcode->opcode & 0x0FF;
if ((jmp_mode == 0 && flag_force_long_jumps)
|| (operands[1].exp.X_op == O_constant
&& (!check_range (n, M6812_OP_IBCC_MARKER) &&
- (jmp_mode == 1 || flag_fixed_branchs == 0))))
+ (jmp_mode == 1 || flag_fixed_branches == 0))))
{
f = frag_more (2);
code ^= 0x20;
else
{
/* Branch offset must fit in 8-bits, don't do some relax. */
- if (jmp_mode == 0 && flag_fixed_branchs)
+ if (jmp_mode == 0 && flag_fixed_branches)
{
fixup8 (&operands[0].exp, M6811_OP_JUMP_REL, M6811_OP_JUMP_REL);
}
/* Assemble the post index byte for 68HC12 extended addressing modes. */
static int
-build_indexed_byte (op, format, move_insn)
- operand *op;
- int format ATTRIBUTE_UNUSED;
- int move_insn;
+build_indexed_byte (operand *op, int format ATTRIBUTE_UNUSED, int move_insn)
{
unsigned char byte = 0;
char *f;
sym = make_expr_symbol (&op->exp);
off = 0;
}
- frag_var (rs_machine_dependent, 2, 2,
- ENCODE_RELAX (STATE_INDEXED_OFFSET, STATE_UNDF),
- sym, off, f);
+ /* movb/movw cannot be relaxed. */
+ if (move_insn)
+ {
+ byte <<= 6;
+ number_to_chars_bigendian (f, byte, 1);
+ fix_new (frag_now, f - frag_now->fr_literal, 1,
+ sym, off, 0, BFD_RELOC_M68HC12_5B);
+ return 1;
+ }
+ else
+ {
+ number_to_chars_bigendian (f, byte, 1);
+ frag_var (rs_machine_dependent, 2, 2,
+ ENCODE_RELAX (STATE_INDEXED_OFFSET, STATE_UNDF),
+ sym, off, f);
+ }
}
else
{
f = frag_more (1);
- number_to_chars_bigendian (f, byte, 1);
- frag_var (rs_machine_dependent, 2, 2,
- ENCODE_RELAX (STATE_INDEXED_PCREL, STATE_UNDF),
- op->exp.X_add_symbol,
- op->exp.X_add_number, f);
+ /* movb/movw cannot be relaxed. */
+ if (move_insn)
+ {
+ byte <<= 6;
+ number_to_chars_bigendian (f, byte, 1);
+ fix_new (frag_now, f - frag_now->fr_literal, 1,
+ op->exp.X_add_symbol, op->exp.X_add_number, 0, BFD_RELOC_M68HC12_5B);
+ return 1;
+ }
+ else
+ {
+ number_to_chars_bigendian (f, byte, 1);
+ frag_var (rs_machine_dependent, 2, 2,
+ ENCODE_RELAX (STATE_INDEXED_PCREL, STATE_UNDF),
+ op->exp.X_add_symbol,
+ op->exp.X_add_number, f);
+ }
}
return 3;
}
/* Assemble the 68HC12 register mode byte. */
static int
-build_reg_mode (op, format)
- operand *op;
- int format;
+build_reg_mode (operand *op, int format)
{
unsigned char byte;
char *f;
}
/* build_insn takes a pointer to the opcode entry in the opcode table,
- the array of operand expressions and builds the correspding instruction.
+ the array of operand expressions and builds the corresponding instruction.
This operation only deals with non relative jumps insn (need special
handling). */
static void
-build_insn (opcode, operands, nb_operands)
- struct m68hc11_opcode *opcode;
- operand operands[];
- int nb_operands ATTRIBUTE_UNUSED;
+build_insn (struct m68hc11_opcode *opcode, operand operands[],
+ int nb_operands ATTRIBUTE_UNUSED)
{
int i;
char *f;
format = opcode->format;
if (format & M6811_OP_BRANCH)
- fix_new (frag_now, frag_now_fix (), 1,
+ fix_new (frag_now, frag_now_fix (), 0,
&abs_symbol, 0, 1, BFD_RELOC_M68HC11_RL_JUMP);
if (format & OP_EXTENDED)
opcodes with the same name and use the operands to choose the correct
opcode. Returns the opcode pointer if there was a match and 0 if none. */
static struct m68hc11_opcode *
-find (opc, operands, nb_operands)
- struct m68hc11_opcode_def *opc;
- operand operands[];
- int nb_operands;
+find (struct m68hc11_opcode_def *opc, operand operands[], int nb_operands)
{
int i, match, pos;
struct m68hc11_opcode *opcode;
Returns the opcode pointer that matches the opcode name in the
source line and the associated operands. */
static struct m68hc11_opcode *
-find_opcode (opc, operands, nb_operands)
- struct m68hc11_opcode_def *opc;
- operand operands[];
- int *nb_operands;
+find_opcode (struct m68hc11_opcode_def *opc, operand operands[],
+ int *nb_operands)
{
struct m68hc11_opcode *opcode;
int i;
if (i >= opc->min_operands)
{
opcode = find (opc, operands, i);
+
+ /* Another special case for 'call foo,page' instructions.
+ Since we support 'call foo' and 'call foo,page' we must look
+ if the optional page specification is present otherwise we will
+ assemble immediately and treat the page spec as garbage. */
if (opcode && !(opcode->format & M6812_OP_PAGE))
return opcode;
points to a machine-dependent instruction. This function is supposed to
emit the frags/bytes it assembles to. */
void
-md_assemble (str)
- char *str;
+md_assemble (char *str)
{
struct m68hc11_opcode_def *opc;
struct m68hc11_opcode *opcode;
- unsigned char *op_start, *save;
- unsigned char *op_end;
+ unsigned char *op_start, *op_end;
+ char *save;
char name[20];
int nlen = 0;
operand operands[M6811_MAX_OPERANDS];
- int nb_operands;
+ int nb_operands = 0;
int branch_optimize = 0;
int alias_id = -1;
/* Find the opcode end and get the opcode in 'name'. The opcode is forced
lower case (the opcode table only has lower case op-codes). */
- for (op_start = op_end = (unsigned char *) (str);
+ for (op_start = op_end = (unsigned char *) str;
*op_end && nlen < 20 && !is_end_of_line[*op_end] && *op_end != ' ';
op_end++)
{
opc = (struct m68hc11_opcode_def *) hash_find (m68hc11_hash, name);
/* If it's not recognized, look for 'jbsr' and 'jbxx'. These are
- pseudo insns for relative branch. For these branchs, we always
- optimize them (turned into absolute branchs) even if --short-branchs
+ pseudo insns for relative branch. For these branches, we always
+ optimize them (turned into absolute branches) even if --short-branches
is given. */
if (opc == NULL && name[0] == 'j' && name[1] == 'b')
{
return;
}
save = input_line_pointer;
- input_line_pointer = op_end;
+ input_line_pointer = (char *) op_end;
if (opc)
{
\f
/* Pseudo op to control the ELF flags. */
static void
-s_m68hc11_mode (x)
- int x ATTRIBUTE_UNUSED;
+s_m68hc11_mode (int x ATTRIBUTE_UNUSED)
{
char *name = input_line_pointer, ch;
to invoke them. This is also used by the debugger to correctly
find the stack frame. */
static void
-s_m68hc11_mark_symbol (mark)
- int mark;
+s_m68hc11_mark_symbol (int mark)
{
char *name;
int c;
bfdsym = symbol_get_bfdsym (symbolP);
elfsym = elf_symbol_from (bfd_asymbol_bfd (bfdsym), bfdsym);
- assert (elfsym);
+ gas_assert (elfsym);
/* Mark the symbol far (using rtc for function return). */
elfsym->internal_elf_sym.st_other |= mark;
}
static void
-s_m68hc11_relax (ignore)
- int ignore ATTRIBUTE_UNUSED;
+s_m68hc11_relax (int ignore ATTRIBUTE_UNUSED)
{
expressionS ex;
return;
}
- fix_new_exp (frag_now, frag_now_fix (), 1, &ex, 1,
+ fix_new_exp (frag_now, frag_now_fix (), 0, &ex, 1,
BFD_RELOC_M68HC11_RL_GROUP);
demand_empty_rest_of_line ();
next instruction. That is, the address of the offset, plus its
size, since the offset is always the last part of the insn. */
long
-md_pcrel_from (fixP)
- fixS *fixP;
+md_pcrel_from (fixS *fixP)
{
if (fixP->fx_r_type == BFD_RELOC_M68HC11_RL_JUMP)
return 0;
/* If while processing a fixup, a reloc really needs to be created
then it is done here. */
arelent *
-tc_gen_reloc (section, fixp)
- asection *section ATTRIBUTE_UNUSED;
- fixS *fixp;
+tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
{
arelent *reloc;
The offset can be 5, 9 or 16 bits long. */
long
-m68hc11_relax_frag (seg, fragP, stretch)
- segT seg ATTRIBUTE_UNUSED;
- fragS *fragP;
- long stretch ATTRIBUTE_UNUSED;
+m68hc11_relax_frag (segT seg ATTRIBUTE_UNUSED, fragS *fragP,
+ long stretch ATTRIBUTE_UNUSED)
{
long growth;
offsetT aim = 0;
}
void
-md_convert_frag (abfd, sec, fragP)
- bfd *abfd ATTRIBUTE_UNUSED;
- asection *sec ATTRIBUTE_UNUSED;
- fragS *fragP;
+md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, asection *sec ATTRIBUTE_UNUSED,
+ fragS *fragP)
{
fixS *fixp;
long value;
case ENCODE_RELAX (STATE_PC_RELATIVE, STATE_WORD):
/* This relax is only for bsr and bra. */
- assert (IS_OPCODE (fragP->fr_opcode[0], M6811_BSR)
+ gas_assert (IS_OPCODE (fragP->fr_opcode[0], M6811_BSR)
|| IS_OPCODE (fragP->fr_opcode[0], M6811_BRA)
|| IS_OPCODE (fragP->fr_opcode[0], M6812_BSR));
relax externally visible symbol because there is no shared library
and such symbol can't be overridden (unless they are weak). */
static int
-relaxable_symbol (symbol)
- symbolS *symbol;
+relaxable_symbol (symbolS *symbol)
{
return ! S_IS_WEAK (symbol);
}
/* Force truly undefined symbols to their maximum size, and generally set up
the frag list to be relaxed. */
int
-md_estimate_size_before_relax (fragP, segment)
- fragS *fragP;
- asection *segment;
+md_estimate_size_before_relax (fragS *fragP, asection *segment)
{
if (RELAX_LENGTH (fragP->fr_subtype) == STATE_UNDF)
{
if (S_GET_SEGMENT (fragP->fr_symbol) != segment
- || !relaxable_symbol (fragP->fr_symbol))
+ || !relaxable_symbol (fragP->fr_symbol)
+ || (segment != absolute_section
+ && RELAX_STATE (fragP->fr_subtype) == STATE_INDEXED_OFFSET))
{
/* Non-relaxable cases. */
int old_fr_fix;
case STATE_PC_RELATIVE:
/* This relax is only for bsr and bra. */
- assert (IS_OPCODE (fragP->fr_opcode[0], M6811_BSR)
+ gas_assert (IS_OPCODE (fragP->fr_opcode[0], M6811_BSR)
|| IS_OPCODE (fragP->fr_opcode[0], M6811_BRA)
|| IS_OPCODE (fragP->fr_opcode[0], M6812_BSR));
- if (flag_fixed_branchs)
+ if (flag_fixed_branches)
as_bad_where (fragP->fr_file, fragP->fr_line,
_("bra or bsr with undefined symbol."));
break;
case STATE_CONDITIONAL_BRANCH:
- assert (current_architecture & cpu6811);
+ gas_assert (current_architecture & cpu6811);
fragP->fr_opcode[0] ^= 1; /* Reverse sense of branch. */
fragP->fr_opcode[1] = 3; /* Skip next jmp insn (3 bytes). */
break;
case STATE_INDEXED_OFFSET:
- assert (current_architecture & cpu6812);
+ gas_assert (current_architecture & cpu6812);
if (fragP->fr_symbol
&& S_GET_SEGMENT (fragP->fr_symbol) == absolute_section)
break;
case STATE_INDEXED_PCREL:
- assert (current_architecture & cpu6812);
+ gas_assert (current_architecture & cpu6812);
if (fragP->fr_symbol
&& S_GET_SEGMENT (fragP->fr_symbol) == absolute_section)
break;
case STATE_XBCC_BRANCH:
- assert (current_architecture & cpu6812);
+ gas_assert (current_architecture & cpu6812);
fragP->fr_opcode[0] ^= 0x20; /* Reverse sense of branch. */
fragP->fr_opcode[1] = 3; /* Skip next jmp insn (3 bytes). */
break;
case STATE_CONDITIONAL_BRANCH_6812:
- assert (current_architecture & cpu6812);
+ gas_assert (current_architecture & cpu6812);
/* Translate into a lbcc branch. */
fragP->fr_opcode[1] = fragP->fr_opcode[0];
{
case STATE_PC_RELATIVE:
/* This relax is only for bsr and bra. */
- assert (IS_OPCODE (fragP->fr_opcode[0], M6811_BSR)
+ gas_assert (IS_OPCODE (fragP->fr_opcode[0], M6811_BSR)
|| IS_OPCODE (fragP->fr_opcode[0], M6811_BRA)
|| IS_OPCODE (fragP->fr_opcode[0], M6812_BSR));
break;
case STATE_CONDITIONAL_BRANCH:
- assert (current_architecture & cpu6811);
+ gas_assert (current_architecture & cpu6811);
fragP->fr_subtype = ENCODE_RELAX (STATE_CONDITIONAL_BRANCH,
STATE_BYTE);
break;
case STATE_INDEXED_OFFSET:
- assert (current_architecture & cpu6812);
+ gas_assert (current_architecture & cpu6812);
fragP->fr_subtype = ENCODE_RELAX (STATE_INDEXED_OFFSET,
STATE_BITS5);
break;
case STATE_INDEXED_PCREL:
- assert (current_architecture & cpu6812);
+ gas_assert (current_architecture & cpu6812);
fragP->fr_subtype = ENCODE_RELAX (STATE_INDEXED_PCREL,
STATE_BITS5);
break;
case STATE_XBCC_BRANCH:
- assert (current_architecture & cpu6812);
+ gas_assert (current_architecture & cpu6812);
fragP->fr_subtype = ENCODE_RELAX (STATE_XBCC_BRANCH, STATE_BYTE);
break;
case STATE_CONDITIONAL_BRANCH_6812:
- assert (current_architecture & cpu6812);
+ gas_assert (current_architecture & cpu6812);
fragP->fr_subtype = ENCODE_RELAX (STATE_CONDITIONAL_BRANCH_6812,
STATE_BYTE);
/* See whether we need to force a relocation into the output file. */
int
-tc_m68hc11_force_relocation (fixP)
- fixS * fixP;
+tc_m68hc11_force_relocation (fixS *fixP)
{
- switch (fixP->fx_r_type)
- {
- case BFD_RELOC_VTABLE_INHERIT:
- case BFD_RELOC_VTABLE_ENTRY:
- case BFD_RELOC_M68HC11_RL_GROUP:
- return 1;
+ if (fixP->fx_r_type == BFD_RELOC_M68HC11_RL_GROUP)
+ return 1;
- default:
- break;
- }
-
- return S_FORCE_RELOC (fixP->fx_addsy);
+ return generic_force_reloc (fixP);
}
/* Here we decide which fixups can be adjusted to make them relative
correctly, so in some cases we force the original symbol to be
used. */
int
-tc_m68hc11_fix_adjustable (fixP)
- fixS *fixP;
+tc_m68hc11_fix_adjustable (fixS *fixP)
{
switch (fixP->fx_r_type)
{
/* For the linker relaxation to work correctly, these relocs
need to be on the symbol itself. */
case BFD_RELOC_16:
- case BFD_RELOC_LO16:
case BFD_RELOC_M68HC11_RL_JUMP:
case BFD_RELOC_M68HC11_RL_GROUP:
case BFD_RELOC_VTABLE_INHERIT:
case BFD_RELOC_VTABLE_ENTRY:
+ case BFD_RELOC_32:
+
+ /* The memory bank addressing translation also needs the original
+ symbol. */
+ case BFD_RELOC_M68HC11_LO16:
+ case BFD_RELOC_M68HC11_PAGE:
+ case BFD_RELOC_M68HC11_24:
return 0;
- case BFD_RELOC_32:
default:
return 1;
}
}
void
-md_apply_fix3 (fixP, valP, seg)
- fixS *fixP;
- valueT *valP;
- segT seg ATTRIBUTE_UNUSED;
+md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
{
char *where;
long value = * valP;
case BFD_RELOC_M68HC11_LO8:
case BFD_RELOC_8:
case BFD_RELOC_M68HC11_PAGE:
-#if 0
- bfd_putb8 ((bfd_vma) value, (unsigned char *) where);
-#endif
((bfd_byte *) where)[0] = (bfd_byte) value;
break;
case BFD_RELOC_8_PCREL:
-#if 0
- bfd_putb8 ((bfd_vma) value, (unsigned char *) where);
-#endif
((bfd_byte *) where)[0] = (bfd_byte) value;
if (value < -128 || value > 127)
where[0] = where[0] | (value & 0x07);
break;
+ case BFD_RELOC_M68HC12_5B:
+ if (value < -16 || value > 15)
+ as_bad_where (fixP->fx_file, fixP->fx_line,
+ _("Offset out of 5-bit range for movw/movb insn: %ld"),
+ value);
+ if (value >= 0)
+ where[0] |= value;
+ else
+ where[0] |= (0x10 | (16 + value));
+ break;
+
case BFD_RELOC_M68HC11_RL_JUMP:
case BFD_RELOC_M68HC11_RL_GROUP:
case BFD_RELOC_VTABLE_INHERIT:
/* Set the ELF specific flags. */
void
-m68hc11_elf_final_processing ()
+m68hc11_elf_final_processing (void)
{
+ if (current_architecture & cpu6812s)
+ elf_flags |= EF_M68HCS12_MACH;
elf_elfheader (stdoutput)->e_flags &= ~EF_M68HC11_ABI;
elf_elfheader (stdoutput)->e_flags |= elf_flags;
}
projects / binutils-gdb.git / blobdiff