/* tc-mips.c -- assemble code for a MIPS chip.
Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
- 2003, 2004, 2005 Free Software Foundation, Inc.
+ 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc.
Contributed by the OSF and Ralph Campbell.
Written by Keith Knowles and Ralph Campbell, working independently.
Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
GAS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2, or (at your option)
+ the Free Software Foundation; either version 3, or (at your option)
any later version.
GAS is distributed in the hope that it will be useful,
#include "subsegs.h"
#include "safe-ctype.h"
-#include <stdarg.h>
-
#include "opcode/mips.h"
#include "itbl-ops.h"
#include "dwarf2dbg.h"
int ase_mdmx;
int ase_smartmips;
int ase_dsp;
+ int ase_dspr2;
int ase_mt;
/* Whether we are assembling for the mips16 processor. 0 if we are
not, 1 if we are, and -1 if the value has not been initialized.
static struct mips_set_options mips_opts =
{
- ISA_UNKNOWN, -1, -1, 0, -1, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0, CPU_UNKNOWN, FALSE
+ ISA_UNKNOWN, -1, -1, 0, -1, -1, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0, CPU_UNKNOWN, FALSE
};
/* These variables are filled in with the masks of registers used.
command line (e.g., by -march). */
static int file_ase_mips16;
+#define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \
+ || mips_opts.isa == ISA_MIPS32R2 \
+ || mips_opts.isa == ISA_MIPS64 \
+ || mips_opts.isa == ISA_MIPS64R2)
+
/* True if -mips3d was passed or implied by arguments passed on the
command line (e.g., by -march). */
static int file_ase_mips3d;
command line (e.g., by -march). */
static int file_ase_smartmips;
-#define ISA_SUPPORT_SMARTMIPS (mips_opts.isa == ISA_MIPS32 \
- || mips_opts.isa == ISA_MIPS32R2)
+#define ISA_SUPPORTS_SMARTMIPS (mips_opts.isa == ISA_MIPS32 \
+ || mips_opts.isa == ISA_MIPS32R2)
/* True if -mdsp was passed or implied by arguments passed on the
command line (e.g., by -march). */
static int file_ase_dsp;
+#define ISA_SUPPORTS_DSP_ASE (mips_opts.isa == ISA_MIPS32R2 \
+ || mips_opts.isa == ISA_MIPS64R2)
+
+#define ISA_SUPPORTS_DSP64_ASE (mips_opts.isa == ISA_MIPS64R2)
+
+/* True if -mdspr2 was passed or implied by arguments passed on the
+ command line (e.g., by -march). */
+static int file_ase_dspr2;
+
+#define ISA_SUPPORTS_DSPR2_ASE (mips_opts.isa == ISA_MIPS32R2 \
+ || mips_opts.isa == ISA_MIPS64R2)
+
/* True if -mmt was passed or implied by arguments passed on the
command line (e.g., by -march). */
static int file_ase_mt;
+#define ISA_SUPPORTS_MT_ASE (mips_opts.isa == ISA_MIPS32R2 \
+ || mips_opts.isa == ISA_MIPS64R2)
+
/* The argument of the -march= flag. The architecture we are assembling. */
static int file_mips_arch = CPU_UNKNOWN;
static const char *mips_arch_string;
|| (ABI) == N64_ABI \
|| (ABI) == O64_ABI)
-/* Return true if ISA supports 64 bit gp register instructions. */
+/* Return true if ISA supports 64 bit wide gp registers. */
#define ISA_HAS_64BIT_REGS(ISA) \
((ISA) == ISA_MIPS3 \
|| (ISA) == ISA_MIPS4 \
|| (ISA) == ISA_MIPS64 \
|| (ISA) == ISA_MIPS64R2)
+/* Return true if ISA supports 64 bit wide float registers. */
+#define ISA_HAS_64BIT_FPRS(ISA) \
+ ((ISA) == ISA_MIPS3 \
+ || (ISA) == ISA_MIPS4 \
+ || (ISA) == ISA_MIPS5 \
+ || (ISA) == ISA_MIPS32R2 \
+ || (ISA) == ISA_MIPS64 \
+ || (ISA) == ISA_MIPS64R2)
+
/* Return true if ISA supports 64-bit right rotate (dror et al.)
instructions. */
#define ISA_HAS_DROR(ISA) \
|| (ISA) == ISA_MIPS64 \
|| (ISA) == ISA_MIPS64R2)
+/* Return true if ISA supports move to/from high part of a 64-bit
+ floating-point register. */
+#define ISA_HAS_MXHC1(ISA) \
+ ((ISA) == ISA_MIPS32R2 \
+ || (ISA) == ISA_MIPS64R2)
+
#define HAVE_32BIT_GPRS \
- (mips_opts.gp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
+ (mips_opts.gp32 || !ISA_HAS_64BIT_REGS (mips_opts.isa))
#define HAVE_32BIT_FPRS \
- (mips_opts.fp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
+ (mips_opts.fp32 || !ISA_HAS_64BIT_FPRS (mips_opts.isa))
-#define HAVE_64BIT_GPRS (! HAVE_32BIT_GPRS)
-#define HAVE_64BIT_FPRS (! HAVE_32BIT_FPRS)
+#define HAVE_64BIT_GPRS (!HAVE_32BIT_GPRS)
+#define HAVE_64BIT_FPRS (!HAVE_32BIT_FPRS)
#define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
(strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
|| strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
-/* Return true if the given CPU supports the MIPS3D ASE. */
-#define CPU_HAS_MIPS3D(cpu) ((cpu) == CPU_SB1 \
- )
-
-/* Return true if the given CPU supports the MDMX ASE. */
-#define CPU_HAS_MDMX(cpu) (FALSE \
- )
-
-/* Return true if the given CPU supports the DSP ASE. */
-#define CPU_HAS_DSP(cpu) (FALSE \
- )
-
-/* Return true if the given CPU supports the MT ASE. */
-#define CPU_HAS_MT(cpu) (FALSE \
- )
-
/* True if CPU has a dror instruction. */
#define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
an mfhi/mflo instruction is read in the next two instructions. */
static int mips_7000_hilo_fix;
-/* The size of the small data section. */
+/* The size of objects in the small data section. */
static unsigned int g_switch_value = 8;
/* Whether the -G option was used. */
static int g_switch_seen = 0;
static void s_cplocal (int);
static void s_cprestore (int);
static void s_cpreturn (int);
+static void s_dtprelword (int);
+static void s_dtpreldword (int);
static void s_gpvalue (int);
static void s_gpword (int);
static void s_gpdword (int);
struct mips_cpu_info
{
const char *name; /* CPU or ISA name. */
- int is_isa; /* Is this an ISA? (If 0, a CPU.) */
+ int flags; /* ASEs available, or ISA flag. */
int isa; /* ISA level. */
int cpu; /* CPU number (default CPU if ISA). */
};
+#define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */
+#define MIPS_CPU_ASE_SMARTMIPS 0x0002 /* CPU implements SmartMIPS ASE */
+#define MIPS_CPU_ASE_DSP 0x0004 /* CPU implements DSP ASE */
+#define MIPS_CPU_ASE_MT 0x0008 /* CPU implements MT ASE */
+#define MIPS_CPU_ASE_MIPS3D 0x0010 /* CPU implements MIPS-3D ASE */
+#define MIPS_CPU_ASE_MDMX 0x0020 /* CPU implements MDMX ASE */
+#define MIPS_CPU_ASE_DSPR2 0x0040 /* CPU implements DSP R2 ASE */
+
static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *);
static const struct mips_cpu_info *mips_cpu_info_from_isa (int);
static const struct mips_cpu_info *mips_cpu_info_from_arch (int);
The following pseudo-ops from the Kane and Heinrich MIPS book are
not MIPS CPU specific, but are also not specific to the object file
format. This file is probably the best place to define them, but
- they are not currently supported: .asm0, .endr, .lab, .repeat,
- .struct. */
+ they are not currently supported: .asm0, .endr, .lab, .struct. */
static const pseudo_typeS mips_pseudo_table[] =
{
{"cplocal", s_cplocal, 0},
{"cprestore", s_cprestore, 0},
{"cpreturn", s_cpreturn, 0},
+ {"dtprelword", s_dtprelword, 0},
+ {"dtpreldword", s_dtpreldword, 0},
{"gpvalue", s_gpvalue, 0},
{"gpword", s_gpword, 0},
{"gpdword", s_gpdword, 0},
/* Relatively generic pseudo-ops that happen to be used on MIPS
chips. */
- {"asciiz", stringer, 1},
+ {"asciiz", stringer, 8 + 1},
{"bss", s_change_sec, 'b'},
{"err", s_err, 0},
{"half", s_cons, 1},
{"dword", s_cons, 3},
{"weakext", s_mips_weakext, 0},
+ {"origin", s_org, 0},
+ {"repeat", s_rept, 0},
/* These pseudo-ops are defined in read.c, but must be overridden
here for one reason or another. */
symbolS *label;
};
-static struct insn_label_list *insn_labels;
static struct insn_label_list *free_insn_labels;
+#define label_list tc_segment_info_data
static void mips_clear_insn_labels (void);
mips_clear_insn_labels (void)
{
register struct insn_label_list **pl;
+ segment_info_type *si;
- for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next)
- ;
- *pl = insn_labels;
- insn_labels = NULL;
+ if (now_seg)
+ {
+ for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next)
+ ;
+
+ si = seg_info (now_seg);
+ *pl = si->label_list;
+ si->label_list = NULL;
+ }
}
+
\f
static char *expr_end;
void
md_begin (void)
{
- register const char *retval = NULL;
+ const char *retval = NULL;
int i = 0;
int broken = 0;
bfd_set_gp_size (stdoutput, g_switch_value);
#ifdef OBJ_ELF
- if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
+ if (IS_ELF)
{
/* On a native system other than VxWorks, sections must be aligned
to 16 byte boundaries. When configured for an embedded ELF
SEC_HAS_CONTENTS | SEC_READONLY);
(void) bfd_set_section_alignment (stdoutput, sec, 2);
}
- else if (OUTPUT_FLAVOR == bfd_target_elf_flavour && mips_flag_pdr)
+ else if (mips_flag_pdr)
{
pdr_seg = subseg_new (".pdr", (subsegT) 0);
(void) bfd_set_section_flags (stdoutput, pdr_seg,
static void
mips_move_labels (void)
{
+ segment_info_type *si = seg_info (now_seg);
struct insn_label_list *l;
valueT val;
- for (l = insn_labels; l != NULL; l = l->next)
+ for (l = si->label_list; l != NULL; l = l->next)
{
assert (S_GET_SEGMENT (l->label) == now_seg);
symbol_set_frag (l->label, frag_now);
}
}
+static bfd_boolean
+s_is_linkonce (symbolS *sym, segT from_seg)
+{
+ bfd_boolean linkonce = FALSE;
+ segT symseg = S_GET_SEGMENT (sym);
+
+ if (symseg != from_seg && !S_IS_LOCAL (sym))
+ {
+ if ((bfd_get_section_flags (stdoutput, symseg) & SEC_LINK_ONCE))
+ linkonce = TRUE;
+#ifdef OBJ_ELF
+ /* The GNU toolchain uses an extension for ELF: a section
+ beginning with the magic string .gnu.linkonce is a
+ linkonce section. */
+ if (strncmp (segment_name (symseg), ".gnu.linkonce",
+ sizeof ".gnu.linkonce" - 1) == 0)
+ linkonce = TRUE;
+#endif
+ }
+ return linkonce;
+}
+
/* Mark instruction labels in mips16 mode. This permits the linker to
handle them specially, such as generating jalx instructions when
needed. We also make them odd for the duration of the assembly, in
static void
mips16_mark_labels (void)
{
- if (mips_opts.mips16)
- {
- struct insn_label_list *l;
- valueT val;
+ segment_info_type *si = seg_info (now_seg);
+ struct insn_label_list *l;
- for (l = insn_labels; l != NULL; l = l->next)
- {
-#ifdef OBJ_ELF
- if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
- S_SET_OTHER (l->label, STO_MIPS16);
+ if (!mips_opts.mips16)
+ return;
+
+ for (l = si->label_list; l != NULL; l = l->next)
+ {
+ symbolS *label = l->label;
+
+#if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF)
+ if (IS_ELF)
+ S_SET_OTHER (label, STO_MIPS16);
#endif
- val = S_GET_VALUE (l->label);
- if ((val & 1) == 0)
- S_SET_VALUE (l->label, val + 1);
- }
+ if ((S_GET_VALUE (label) & 1) == 0
+ /* Don't adjust the address if the label is global or weak, or
+ in a link-once section, since we'll be emitting symbol reloc
+ references to it which will be patched up by the linker, and
+ the final value of the symbol may or may not be MIPS16. */
+ && ! S_IS_WEAK (label)
+ && ! S_IS_EXTERNAL (label)
+ && ! s_is_linkonce (label, now_seg))
+ S_SET_VALUE (label, S_GET_VALUE (label) | 1);
}
}
append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
bfd_reloc_code_real_type *reloc_type)
{
- register unsigned long prev_pinfo, pinfo;
+ unsigned long prev_pinfo, pinfo;
relax_stateT prev_insn_frag_type = 0;
bfd_boolean relaxed_branch = FALSE;
+ segment_info_type *si = seg_info (now_seg);
/* Mark instruction labels in mips16 mode. */
mips16_mark_labels ();
reloc_type[0] == BFD_RELOC_16_PCREL_S2,
reloc_type[0]);
+ /* Tag symbols that have a R_MIPS16_26 relocation against them. */
+ if (reloc_type[0] == BFD_RELOC_MIPS16_JMP
+ && ip->fixp[0]->fx_addsy)
+ *symbol_get_tc (ip->fixp[0]->fx_addsy) = 1;
+
/* These relocations can have an addend that won't fit in
4 octets for 64bit assembly. */
if (HAVE_64BIT_GPRS
whether there is a label on this instruction. If
there are any branches to anything other than a
label, users must use .set noreorder. */
- || insn_labels != NULL
+ || si->label_list != NULL
/* If the previous instruction is in a variant frag
other than this branch's one, we cannot do the swap.
This does not apply to the mips16, which uses variant
if (mips_opts.mips16
&& (pinfo & INSN_UNCOND_BRANCH_DELAY)
&& (pinfo & (MIPS16_INSN_READ_X | MIPS16_INSN_READ_31))
- && (mips_opts.isa == ISA_MIPS32
- || mips_opts.isa == ISA_MIPS32R2
- || mips_opts.isa == ISA_MIPS64
- || mips_opts.isa == ISA_MIPS64R2))
+ && ISA_SUPPORTS_MIPS16E)
{
/* Convert MIPS16 jr/jalr into a "compact" jump. */
ip->insn_opcode |= 0x0080;
assert (mo);
assert (strcmp (name, mo->name) == 0);
- /* Search until we get a match for NAME. It is assumed here that
- macros will never generate MDMX or MIPS-3D instructions. */
- while (strcmp (fmt, mo->args) != 0
- || mo->pinfo == INSN_MACRO
- || !OPCODE_IS_MEMBER (mo,
+ while (1)
+ {
+ /* Search until we get a match for NAME. It is assumed here that
+ macros will never generate MDMX, MIPS-3D, or MT instructions. */
+ if (strcmp (fmt, mo->args) == 0
+ && mo->pinfo != INSN_MACRO
+ && OPCODE_IS_MEMBER (mo,
(mips_opts.isa
| (mips_opts.mips16 ? INSN_MIPS16 : 0)
+ | (mips_opts.ase_dsp ? INSN_DSP : 0)
+ | ((mips_opts.ase_dsp && ISA_SUPPORTS_DSP64_ASE)
+ ? INSN_DSP64 : 0)
+ | (mips_opts.ase_dspr2 ? INSN_DSPR2 : 0)
| (mips_opts.ase_smartmips ? INSN_SMARTMIPS : 0)),
mips_opts.arch)
- || (mips_opts.arch == CPU_R4650 && (mo->pinfo & FP_D) != 0))
- {
+ && (mips_opts.arch != CPU_R4650 || (mo->pinfo & FP_D) == 0))
+ break;
+
++mo;
assert (mo->name);
assert (strcmp (name, mo->name) == 0);
}
continue;
+ case '2':
+ INSERT_OPERAND (BP, insn, va_arg (args, int));
+ continue;
+
case 't':
case 'w':
case 'E':
continue;
case 'C':
- insn.insn_opcode |= va_arg (args, unsigned long);
+ INSERT_OPERAND (COPZ, insn, va_arg (args, unsigned long));
continue;
case 'k':
- insn.insn_opcode |= va_arg (args, unsigned long) << OP_SH_CACHE;
+ INSERT_OPERAND (CACHE, insn, va_arg (args, unsigned long));
continue;
default:
regno = va_arg (args, int);
regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3);
- insn.insn_opcode |= regno << MIPS16OP_SH_REG32R;
+ MIPS16_INSERT_OPERAND (REG32R, insn, regno);
}
continue;
if (high_expr.X_op == O_constant)
{
- /* we can compute the instruction now without a relocation entry */
+ /* We can compute the instruction now without a relocation entry. */
high_expr.X_add_number = ((high_expr.X_add_number + 0x8000)
>> 16) & 0xffff;
*r = BFD_RELOC_UNUSED;
static void
macro (struct mips_cl_insn *ip)
{
- register int treg, sreg, dreg, breg;
+ int treg, sreg, dreg, breg;
int tempreg;
int mask;
int used_at = 0;
macro_build (NULL, s2, "d,v,t", treg, sreg, AT);
break;
+ case M_BALIGN:
+ switch (imm_expr.X_add_number)
+ {
+ case 0:
+ macro_build (NULL, "nop", "");
+ break;
+ case 2:
+ macro_build (NULL, "packrl.ph", "d,s,t", treg, treg, sreg);
+ break;
+ default:
+ macro_build (NULL, "balign", "t,s,2", treg, sreg,
+ (int)imm_expr.X_add_number);
+ break;
+ }
+ break;
+
case M_BEQ_I:
s = "beq";
goto beq_i;
static void
macro2 (struct mips_cl_insn *ip)
{
- register int treg, sreg, dreg, breg;
+ int treg, sreg, dreg, breg;
int tempreg;
int mask;
int used_at;
case '%': USE_BITS (OP_MASK_VECALIGN, OP_SH_VECALIGN); break;
case '[': break;
case ']': break;
+ case '2': USE_BITS (OP_MASK_BP, OP_SH_BP); break;
case '3': USE_BITS (OP_MASK_SA3, OP_SH_SA3); break;
case '4': USE_BITS (OP_MASK_SA4, OP_SH_SA4); break;
case '5': USE_BITS (OP_MASK_IMM8, OP_SH_IMM8); break;
| (file_ase_mips16 ? INSN_MIPS16 : 0)
| (mips_opts.ase_mdmx ? INSN_MDMX : 0)
| (mips_opts.ase_dsp ? INSN_DSP : 0)
+ | ((mips_opts.ase_dsp && ISA_SUPPORTS_DSP64_ASE)
+ ? INSN_DSP64 : 0)
+ | (mips_opts.ase_dspr2 ? INSN_DSPR2 : 0)
| (mips_opts.ase_mt ? INSN_MT : 0)
| (mips_opts.ase_mips3d ? INSN_MIPS3D : 0)
| (mips_opts.ase_smartmips ? INSN_SMARTMIPS : 0)),
return;
break;
+ case '2': /* dsp 2-bit unsigned immediate in bit 11 */
+ my_getExpression (&imm_expr, s);
+ check_absolute_expr (ip, &imm_expr);
+ if ((unsigned long) imm_expr.X_add_number != 1
+ && (unsigned long) imm_expr.X_add_number != 3)
+ {
+ as_bad (_("BALIGN immediate not 1 or 3 (%lu)"),
+ (unsigned long) imm_expr.X_add_number);
+ }
+ INSERT_OPERAND (BP, *ip, imm_expr.X_add_number);
+ imm_expr.X_op = O_absent;
+ s = expr_end;
+ continue;
+
case '3': /* dsp 3-bit unsigned immediate in bit 21 */
my_getExpression (&imm_expr, s);
check_absolute_expr (ip, &imm_expr);
if (imm_expr.X_add_number & ~OP_MASK_SA3)
{
- as_warn (_("DSP immediate not in range 0..%d (%lu)"),
- OP_MASK_SA3, (unsigned long) imm_expr.X_add_number);
- imm_expr.X_add_number &= OP_MASK_SA3;
+ as_bad (_("DSP immediate not in range 0..%d (%lu)"),
+ OP_MASK_SA3, (unsigned long) imm_expr.X_add_number);
}
- ip->insn_opcode |= imm_expr.X_add_number << OP_SH_SA3;
+ INSERT_OPERAND (SA3, *ip, imm_expr.X_add_number);
imm_expr.X_op = O_absent;
s = expr_end;
continue;
check_absolute_expr (ip, &imm_expr);
if (imm_expr.X_add_number & ~OP_MASK_SA4)
{
- as_warn (_("DSP immediate not in range 0..%d (%lu)"),
- OP_MASK_SA4, (unsigned long) imm_expr.X_add_number);
- imm_expr.X_add_number &= OP_MASK_SA4;
+ as_bad (_("DSP immediate not in range 0..%d (%lu)"),
+ OP_MASK_SA4, (unsigned long) imm_expr.X_add_number);
}
- ip->insn_opcode |= imm_expr.X_add_number << OP_SH_SA4;
+ INSERT_OPERAND (SA4, *ip, imm_expr.X_add_number);
imm_expr.X_op = O_absent;
s = expr_end;
continue;
check_absolute_expr (ip, &imm_expr);
if (imm_expr.X_add_number & ~OP_MASK_IMM8)
{
- as_warn (_("DSP immediate not in range 0..%d (%lu)"),
- OP_MASK_IMM8, (unsigned long) imm_expr.X_add_number);
- imm_expr.X_add_number &= OP_MASK_IMM8;
+ as_bad (_("DSP immediate not in range 0..%d (%lu)"),
+ OP_MASK_IMM8, (unsigned long) imm_expr.X_add_number);
}
- ip->insn_opcode |= imm_expr.X_add_number << OP_SH_IMM8;
+ INSERT_OPERAND (IMM8, *ip, imm_expr.X_add_number);
imm_expr.X_op = O_absent;
s = expr_end;
continue;
check_absolute_expr (ip, &imm_expr);
if (imm_expr.X_add_number & ~OP_MASK_RS)
{
- as_warn (_("DSP immediate not in range 0..%d (%lu)"),
- OP_MASK_RS, (unsigned long) imm_expr.X_add_number);
- imm_expr.X_add_number &= OP_MASK_RS;
+ as_bad (_("DSP immediate not in range 0..%d (%lu)"),
+ OP_MASK_RS, (unsigned long) imm_expr.X_add_number);
}
- ip->insn_opcode |= imm_expr.X_add_number << OP_SH_RS;
+ INSERT_OPERAND (RS, *ip, imm_expr.X_add_number);
imm_expr.X_op = O_absent;
s = expr_end;
continue;
{
regno = s[3] - '0';
s += 4;
- ip->insn_opcode |= regno << OP_SH_DSPACC;
+ INSERT_OPERAND (DSPACC, *ip, regno);
continue;
}
else
check_absolute_expr (ip, &imm_expr);
if (imm_expr.X_add_number & ~OP_MASK_WRDSP)
{
- as_warn (_("DSP immediate not in range 0..%d (%lu)"),
- OP_MASK_WRDSP,
- (unsigned long) imm_expr.X_add_number);
- imm_expr.X_add_number &= OP_MASK_WRDSP;
+ as_bad (_("DSP immediate not in range 0..%d (%lu)"),
+ OP_MASK_WRDSP,
+ (unsigned long) imm_expr.X_add_number);
}
- ip->insn_opcode |= imm_expr.X_add_number << OP_SH_WRDSP;
+ INSERT_OPERAND (WRDSP, *ip, imm_expr.X_add_number);
imm_expr.X_op = O_absent;
s = expr_end;
continue;
{
regno = s[3] - '0';
s += 4;
- ip->insn_opcode |= regno << OP_SH_DSPACC_S;
+ INSERT_OPERAND (DSPACC_S, *ip, regno);
continue;
}
else
if (imm_expr.X_add_number < min_range ||
imm_expr.X_add_number > max_range)
{
- as_warn (_("DSP immediate not in range %ld..%ld (%ld)"),
- (long) min_range, (long) max_range,
- (long) imm_expr.X_add_number);
+ as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
+ (long) min_range, (long) max_range,
+ (long) imm_expr.X_add_number);
}
- imm_expr.X_add_number &= OP_MASK_DSPSFT;
- ip->insn_opcode |= ((unsigned long) imm_expr.X_add_number
- << OP_SH_DSPSFT);
+ INSERT_OPERAND (DSPSFT, *ip, imm_expr.X_add_number);
imm_expr.X_op = O_absent;
s = expr_end;
continue;
check_absolute_expr (ip, &imm_expr);
if (imm_expr.X_add_number & ~OP_MASK_RDDSP)
{
- as_warn (_("DSP immediate not in range 0..%d (%lu)"),
- OP_MASK_RDDSP,
- (unsigned long) imm_expr.X_add_number);
- imm_expr.X_add_number &= OP_MASK_RDDSP;
+ as_bad (_("DSP immediate not in range 0..%d (%lu)"),
+ OP_MASK_RDDSP,
+ (unsigned long) imm_expr.X_add_number);
}
- ip->insn_opcode |= imm_expr.X_add_number << OP_SH_RDDSP;
+ INSERT_OPERAND (RDDSP, *ip, imm_expr.X_add_number);
imm_expr.X_op = O_absent;
s = expr_end;
continue;
if (imm_expr.X_add_number < min_range ||
imm_expr.X_add_number > max_range)
{
- as_warn (_("DSP immediate not in range %ld..%ld (%ld)"),
- (long) min_range, (long) max_range,
- (long) imm_expr.X_add_number);
+ as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
+ (long) min_range, (long) max_range,
+ (long) imm_expr.X_add_number);
}
- imm_expr.X_add_number &= OP_MASK_DSPSFT_7;
- ip->insn_opcode |= ((unsigned long) imm_expr.X_add_number
- << OP_SH_DSPSFT_7);
+ INSERT_OPERAND (DSPSFT_7, *ip, imm_expr.X_add_number);
imm_expr.X_op = O_absent;
s = expr_end;
continue;
if (imm_expr.X_add_number < min_range ||
imm_expr.X_add_number > max_range)
{
- as_warn (_("DSP immediate not in range %ld..%ld (%ld)"),
- (long) min_range, (long) max_range,
- (long) imm_expr.X_add_number);
+ as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
+ (long) min_range, (long) max_range,
+ (long) imm_expr.X_add_number);
}
- imm_expr.X_add_number &= OP_MASK_IMM10;
- ip->insn_opcode |= ((unsigned long) imm_expr.X_add_number
- << OP_SH_IMM10);
+ INSERT_OPERAND (IMM10, *ip, imm_expr.X_add_number);
imm_expr.X_op = O_absent;
s = expr_end;
continue;
- case '!': /* mt 1-bit unsigned immediate in bit 5 */
+ case '!': /* MT usermode flag bit. */
my_getExpression (&imm_expr, s);
check_absolute_expr (ip, &imm_expr);
if (imm_expr.X_add_number & ~OP_MASK_MT_U)
- {
- as_warn (_("MT immediate not in range 0..%d (%lu)"),
- OP_MASK_MT_U, (unsigned long) imm_expr.X_add_number);
- imm_expr.X_add_number &= OP_MASK_MT_U;
- }
- ip->insn_opcode |= imm_expr.X_add_number << OP_SH_MT_U;
+ as_bad (_("MT usermode bit not 0 or 1 (%lu)"),
+ (unsigned long) imm_expr.X_add_number);
+ INSERT_OPERAND (MT_U, *ip, imm_expr.X_add_number);
imm_expr.X_op = O_absent;
s = expr_end;
continue;
- case '$': /* mt 1-bit unsigned immediate in bit 4 */
+ case '$': /* MT load high flag bit. */
my_getExpression (&imm_expr, s);
check_absolute_expr (ip, &imm_expr);
if (imm_expr.X_add_number & ~OP_MASK_MT_H)
- {
- as_warn (_("MT immediate not in range 0..%d (%lu)"),
- OP_MASK_MT_H, (unsigned long) imm_expr.X_add_number);
- imm_expr.X_add_number &= OP_MASK_MT_H;
- }
- ip->insn_opcode |= imm_expr.X_add_number << OP_SH_MT_H;
+ as_bad (_("MT load high bit not 0 or 1 (%lu)"),
+ (unsigned long) imm_expr.X_add_number);
+ INSERT_OPERAND (MT_H, *ip, imm_expr.X_add_number);
imm_expr.X_op = O_absent;
s = expr_end;
continue;
{
regno = s[3] - '0';
s += 4;
- ip->insn_opcode |= regno << OP_SH_MTACC_T;
+ INSERT_OPERAND (MTACC_T, *ip, regno);
continue;
}
else
{
regno = s[3] - '0';
s += 4;
- ip->insn_opcode |= regno << OP_SH_MTACC_D;
+ INSERT_OPERAND (MTACC_D, *ip, regno);
continue;
}
else
break;
case ',':
+ ++argnum;
if (*s++ == *args)
continue;
s--;
as_bad (_("Invalid register number (%d)"), regno);
else
{
- ip->insn_opcode |= regno << OP_SH_RT;
+ INSERT_OPERAND (RT, *ip, regno);
continue;
}
}
case 'c': /* break code */
my_getExpression (&imm_expr, s);
check_absolute_expr (ip, &imm_expr);
- if ((unsigned long) imm_expr.X_add_number > 1023)
- as_warn (_("Illegal break code (%lu)"),
+ if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE)
+ as_warn (_("Code for %s not in range 0..1023 (%lu)"),
+ ip->insn_mo->name,
(unsigned long) imm_expr.X_add_number);
INSERT_OPERAND (CODE, *ip, imm_expr.X_add_number);
imm_expr.X_op = O_absent;
case 'q': /* lower break code */
my_getExpression (&imm_expr, s);
check_absolute_expr (ip, &imm_expr);
- if ((unsigned long) imm_expr.X_add_number > 1023)
- as_warn (_("Illegal lower break code (%lu)"),
+ if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE2)
+ as_warn (_("Lower code for %s not in range 0..1023 (%lu)"),
+ ip->insn_mo->name,
(unsigned long) imm_expr.X_add_number);
INSERT_OPERAND (CODE2, *ip, imm_expr.X_add_number);
imm_expr.X_op = O_absent;
my_getExpression (&imm_expr, s);
check_absolute_expr (ip, &imm_expr);
if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE20)
- as_warn (_("Illegal 20-bit code (%lu)"),
+ as_warn (_("Code for %s not in range 0..1048575 (%lu)"),
+ ip->insn_mo->name,
(unsigned long) imm_expr.X_add_number);
INSERT_OPERAND (CODE20, *ip, imm_expr.X_add_number);
imm_expr.X_op = O_absent;
case 'C': /* Coprocessor code */
my_getExpression (&imm_expr, s);
check_absolute_expr (ip, &imm_expr);
- if ((unsigned long) imm_expr.X_add_number >= (1 << 25))
+ if ((unsigned long) imm_expr.X_add_number > OP_MASK_COPZ)
{
as_warn (_("Coproccesor code > 25 bits (%lu)"),
(unsigned long) imm_expr.X_add_number);
- imm_expr.X_add_number &= ((1 << 25) - 1);
+ imm_expr.X_add_number &= OP_MASK_COPZ;
}
- ip->insn_opcode |= imm_expr.X_add_number;
+ INSERT_OPERAND (COPZ, *ip, imm_expr.X_add_number);
imm_expr.X_op = O_absent;
s = expr_end;
continue;
my_getExpression (&imm_expr, s);
check_absolute_expr (ip, &imm_expr);
if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE19)
- as_warn (_("Illegal 19-bit code (%lu)"),
- (unsigned long) imm_expr.X_add_number);
+ {
+ as_warn (_("Illegal 19-bit code (%lu)"),
+ (unsigned long) imm_expr.X_add_number);
+ imm_expr.X_add_number &= OP_MASK_CODE19;
+ }
INSERT_OPERAND (CODE19, *ip, imm_expr.X_add_number);
imm_expr.X_op = O_absent;
s = expr_end;
ok = reg_lookup (&s, RTYPE_NUM | RTYPE_CP0, ®no);
else
ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no);
- ip->insn_opcode |= regno << OP_SH_RD;
+ INSERT_OPERAND (RD, *ip, regno);
if (ok)
{
lastregno = regno;
break;
}
new_seg = subseg_new (newname, (subsegT) 0);
- if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
+ if (IS_ELF)
bfd_set_section_flags (stdoutput, new_seg,
(SEC_ALLOC
| SEC_LOAD
| SEC_READONLY
| SEC_DATA));
frag_align (*args == 'l' ? 2 : 3, 0, 0);
- if (OUTPUT_FLAVOR == bfd_target_elf_flavour
- && strcmp (TARGET_OS, "elf") != 0)
+ if (IS_ELF && strcmp (TARGET_OS, "elf") != 0)
record_alignment (new_seg, 4);
else
record_alignment (new_seg, *args == 'l' ? 2 : 3);
if (c == 'v' || c == 'w')
{
if (c == 'v')
- ip->insn_opcode |= lastregno << MIPS16OP_SH_RX;
+ MIPS16_INSERT_OPERAND (RX, *ip, lastregno);
else
- ip->insn_opcode |= lastregno << MIPS16OP_SH_RY;
+ MIPS16_INSERT_OPERAND (RY, *ip, lastregno);
++args;
continue;
}
{
if (reg1 >= 4 && reg1 <= 7)
{
- if (c == 'm' && !seen_framesz)
+ if (!seen_framesz)
/* args $a0-$a3 */
args |= 1 << (reg1 - 4);
else
unsigned long *insn, bfd_boolean *use_extend,
unsigned short *extend)
{
- register const struct mips16_immed_operand *op;
+ const struct mips16_immed_operand *op;
int mintiny, maxtiny;
bfd_boolean needext;
{"msmartmips", no_argument, NULL, OPTION_SMARTMIPS},
#define OPTION_NO_SMARTMIPS (OPTION_ASE_BASE + 11)
{"mno-smartmips", no_argument, NULL, OPTION_NO_SMARTMIPS},
+#define OPTION_DSPR2 (OPTION_ASE_BASE + 12)
+ {"mdspr2", no_argument, NULL, OPTION_DSPR2},
+#define OPTION_NO_DSPR2 (OPTION_ASE_BASE + 13)
+ {"mno-dspr2", no_argument, NULL, OPTION_NO_DSPR2},
/* Old-style architecture options. Don't add more of these. */
-#define OPTION_COMPAT_ARCH_BASE (OPTION_ASE_BASE + 12)
+#define OPTION_COMPAT_ARCH_BASE (OPTION_ASE_BASE + 14)
#define OPTION_M4650 (OPTION_COMPAT_ARCH_BASE + 0)
{"m4650", no_argument, NULL, OPTION_M4650},
#define OPTION_NO_M4650 (OPTION_COMPAT_ARCH_BASE + 1)
break;
case 'O':
- if (arg && arg[1] == '0')
+ if (arg && arg[0] == '0')
mips_optimize = 1;
else
mips_optimize = 2;
mips_debug = 2;
else
mips_debug = atoi (arg);
- /* When the MIPS assembler sees -g or -g2, it does not do
- optimizations which limit full symbolic debugging. We take
- that to be equivalent to -O0. */
- if (mips_debug == 2)
- mips_optimize = 1;
break;
case OPTION_MIPS1:
case OPTION_DSP:
mips_opts.ase_dsp = 1;
+ mips_opts.ase_dspr2 = 0;
break;
case OPTION_NO_DSP:
+ mips_opts.ase_dsp = 0;
+ mips_opts.ase_dspr2 = 0;
+ break;
+
+ case OPTION_DSPR2:
+ mips_opts.ase_dspr2 = 1;
+ mips_opts.ase_dsp = 1;
+ break;
+
+ case OPTION_NO_DSPR2:
+ mips_opts.ase_dspr2 = 0;
mips_opts.ase_dsp = 0;
break;
select SVR4_PIC, and -non_shared to select no PIC. This is
intended to be compatible with Irix 5. */
case OPTION_CALL_SHARED:
- if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
+ if (!IS_ELF)
{
as_bad (_("-call_shared is supported only for ELF format"));
return 0;
break;
case OPTION_NON_SHARED:
- if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
+ if (!IS_ELF)
{
as_bad (_("-non_shared is supported only for ELF format"));
return 0;
/* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
and -mabi=64. */
case OPTION_32:
- if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
+ if (!IS_ELF)
{
as_bad (_("-32 is supported for ELF format only"));
return 0;
break;
case OPTION_N32:
- if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
+ if (!IS_ELF)
{
as_bad (_("-n32 is supported for ELF format only"));
return 0;
break;
case OPTION_64:
- if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
+ if (!IS_ELF)
{
as_bad (_("-64 is supported for ELF format only"));
return 0;
}
mips_abi = N64_ABI;
- if (! support_64bit_objects())
+ if (!support_64bit_objects())
as_fatal (_("No compiled in support for 64 bit object file format"));
break;
#endif /* OBJ_ELF */
#ifdef OBJ_ELF
case OPTION_MABI:
- if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
+ if (!IS_ELF)
{
as_bad (_("-mabi is supported for ELF format only"));
return 0;
|| !ISA_HAS_64BIT_REGS (mips_opts.isa));
}
- /* ??? GAS treats single-float processors as though they had 64-bit
- float registers (although it complains when double-precision
- instructions are used). As things stand, saying they have 32-bit
- registers would lead to spurious "register must be even" messages.
- So here we assume float registers are always the same size as
- integer ones, unless the user says otherwise. */
- if (file_mips_fp32 < 0)
- file_mips_fp32 = file_mips_gp32;
+ switch (file_mips_fp32)
+ {
+ default:
+ case -1:
+ /* No user specified float register size.
+ ??? GAS treats single-float processors as though they had 64-bit
+ float registers (although it complains when double-precision
+ instructions are used). As things stand, saying they have 32-bit
+ registers would lead to spurious "register must be even" messages.
+ So here we assume float registers are never smaller than the
+ integer ones. */
+ if (file_mips_gp32 == 0)
+ /* 64-bit integer registers implies 64-bit float registers. */
+ file_mips_fp32 = 0;
+ else if ((mips_opts.ase_mips3d > 0 || mips_opts.ase_mdmx > 0)
+ && ISA_HAS_64BIT_FPRS (mips_opts.isa))
+ /* -mips3d and -mdmx imply 64-bit float registers, if possible. */
+ file_mips_fp32 = 0;
+ else
+ /* 32-bit float registers. */
+ file_mips_fp32 = 1;
+ break;
+
+ /* The user specified the size of the float registers. Check if it
+ agrees with the ABI and ISA. */
+ case 0:
+ if (!ISA_HAS_64BIT_FPRS (mips_opts.isa))
+ as_bad (_("-mfp64 used with a 32-bit fpu"));
+ else if (ABI_NEEDS_32BIT_REGS (mips_abi)
+ && !ISA_HAS_MXHC1 (mips_opts.isa))
+ as_warn (_("-mfp64 used with a 32-bit ABI"));
+ break;
+ case 1:
+ if (ABI_NEEDS_64BIT_REGS (mips_abi))
+ as_warn (_("-mfp32 used with a 64-bit ABI"));
+ break;
+ }
/* End of GCC-shared inference code. */
if (mips_opts.mips16 == -1)
mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_arch)) ? 1 : 0;
if (mips_opts.ase_mips3d == -1)
- mips_opts.ase_mips3d = (CPU_HAS_MIPS3D (file_mips_arch)) ? 1 : 0;
+ mips_opts.ase_mips3d = ((arch_info->flags & MIPS_CPU_ASE_MIPS3D)
+ && file_mips_fp32 == 0) ? 1 : 0;
+ if (mips_opts.ase_mips3d && file_mips_fp32 == 1)
+ as_bad (_("-mfp32 used with -mips3d"));
+
if (mips_opts.ase_mdmx == -1)
- mips_opts.ase_mdmx = (CPU_HAS_MDMX (file_mips_arch)) ? 1 : 0;
+ mips_opts.ase_mdmx = ((arch_info->flags & MIPS_CPU_ASE_MDMX)
+ && file_mips_fp32 == 0) ? 1 : 0;
+ if (mips_opts.ase_mdmx && file_mips_fp32 == 1)
+ as_bad (_("-mfp32 used with -mdmx"));
+
+ if (mips_opts.ase_smartmips == -1)
+ mips_opts.ase_smartmips = (arch_info->flags & MIPS_CPU_ASE_SMARTMIPS) ? 1 : 0;
+ if (mips_opts.ase_smartmips && !ISA_SUPPORTS_SMARTMIPS)
+ as_warn ("%s ISA does not support SmartMIPS",
+ mips_cpu_info_from_isa (mips_opts.isa)->name);
+
if (mips_opts.ase_dsp == -1)
- mips_opts.ase_dsp = (CPU_HAS_DSP (file_mips_arch)) ? 1 : 0;
+ mips_opts.ase_dsp = (arch_info->flags & MIPS_CPU_ASE_DSP) ? 1 : 0;
+ if (mips_opts.ase_dsp && !ISA_SUPPORTS_DSP_ASE)
+ as_warn ("%s ISA does not support DSP ASE",
+ mips_cpu_info_from_isa (mips_opts.isa)->name);
+
+ if (mips_opts.ase_dspr2 == -1)
+ {
+ mips_opts.ase_dspr2 = (arch_info->flags & MIPS_CPU_ASE_DSPR2) ? 1 : 0;
+ mips_opts.ase_dsp = (arch_info->flags & MIPS_CPU_ASE_DSP) ? 1 : 0;
+ }
+ if (mips_opts.ase_dspr2 && !ISA_SUPPORTS_DSPR2_ASE)
+ as_warn ("%s ISA does not support DSP R2 ASE",
+ mips_cpu_info_from_isa (mips_opts.isa)->name);
+
if (mips_opts.ase_mt == -1)
- mips_opts.ase_mt = (CPU_HAS_MT (file_mips_arch)) ? 1 : 0;
+ mips_opts.ase_mt = (arch_info->flags & MIPS_CPU_ASE_MT) ? 1 : 0;
+ if (mips_opts.ase_mt && !ISA_SUPPORTS_MT_ASE)
+ as_warn ("%s ISA does not support MT ASE",
+ mips_cpu_info_from_isa (mips_opts.isa)->name);
file_mips_isa = mips_opts.isa;
file_ase_mips16 = mips_opts.mips16;
file_ase_mdmx = mips_opts.ase_mdmx;
file_ase_smartmips = mips_opts.ase_smartmips;
file_ase_dsp = mips_opts.ase_dsp;
+ file_ase_dspr2 = mips_opts.ase_dspr2;
file_ase_mt = mips_opts.ase_mt;
mips_opts.gp32 = file_mips_gp32;
mips_opts.fp32 = file_mips_fp32;
/* Return the address of the delay slot. */
return addr + 4;
default:
+ /* We have no relocation type for PC relative MIPS16 instructions. */
+ if (fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != now_seg)
+ as_bad_where (fixP->fx_file, fixP->fx_line,
+ _("PC relative MIPS16 instruction references a different section"));
return addr;
}
}
|| fixP->fx_r_type == BFD_RELOC_CTOR
|| fixP->fx_r_type == BFD_RELOC_MIPS_SUB
|| fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
- || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY);
+ || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY
+ || fixP->fx_r_type == BFD_RELOC_MIPS_TLS_DTPREL64);
buf = (bfd_byte *) (fixP->fx_frag->fr_literal + fixP->fx_where);
- assert (! fixP->fx_pcrel || fixP->fx_r_type == BFD_RELOC_16_PCREL_S2);
+ assert (!fixP->fx_pcrel || fixP->fx_r_type == BFD_RELOC_16_PCREL_S2);
/* Don't treat parts of a composite relocation as done. There are two
reasons for this:
constants. The easiest way of dealing with the pathological
exceptions is to generate a relocation against STN_UNDEF and
leave everything up to the linker. */
- if (fixP->fx_addsy == NULL && ! fixP->fx_pcrel && fixP->fx_tcbit == 0)
+ if (fixP->fx_addsy == NULL && !fixP->fx_pcrel && fixP->fx_tcbit == 0)
fixP->fx_done = 1;
switch (fixP->fx_r_type)
{
case BFD_RELOC_MIPS_TLS_GD:
case BFD_RELOC_MIPS_TLS_LDM:
+ case BFD_RELOC_MIPS_TLS_DTPREL32:
+ case BFD_RELOC_MIPS_TLS_DTPREL64:
case BFD_RELOC_MIPS_TLS_DTPREL_HI16:
case BFD_RELOC_MIPS_TLS_DTPREL_LO16:
case BFD_RELOC_MIPS_TLS_GOTTPREL:
case BFD_RELOC_MIPS16_GPREL:
case BFD_RELOC_MIPS16_HI16:
case BFD_RELOC_MIPS16_HI16_S:
- /* Nothing needed to do. The value comes from the reloc entry */
- break;
-
case BFD_RELOC_MIPS16_JMP:
- /* We currently always generate a reloc against a symbol, which
- means that we don't want an addend even if the symbol is
- defined. */
- *valP = 0;
+ /* Nothing needed to do. The value comes from the reloc entry. */
break;
case BFD_RELOC_64:
case BFD_RELOC_RVA:
case BFD_RELOC_32:
- /* If we are deleting this reloc entry, we must fill in the
- value now. This can happen if we have a .word which is not
- resolved when it appears but is later defined. */
- if (fixP->fx_done)
- md_number_to_chars ((char *) buf, *valP, 4);
- break;
-
case BFD_RELOC_16:
/* If we are deleting this reloc entry, we must fill in the
- value now. */
+ value now. This can happen if we have a .word which is not
+ resolved when it appears but is later defined. */
if (fixP->fx_done)
- md_number_to_chars ((char *) buf, *valP, 2);
+ md_number_to_chars ((char *) buf, *valP, fixP->fx_size);
break;
case BFD_RELOC_LO16:
as_bad_where (fixP->fx_file, fixP->fx_line,
_("Branch to misaligned address (%lx)"), (long) *valP);
- /*
- * We need to save the bits in the instruction since fixup_segment()
- * might be deleting the relocation entry (i.e., a branch within
- * the current segment).
- */
+ /* We need to save the bits in the instruction since fixup_segment()
+ might be deleting the relocation entry (i.e., a branch within
+ the current segment). */
if (! fixP->fx_done)
break;
- /* update old instruction data */
+ /* Update old instruction data. */
if (target_big_endian)
insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3];
else
static void
s_align (int x ATTRIBUTE_UNUSED)
{
- register int temp;
- register long temp_fill;
- long max_alignment = 15;
-
- /*
+ int temp;
+ long temp_fill;
+ long max_alignment = 28;
- o Note that the assembler pulls down any immediately preceding label
+ /* o Note that the assembler pulls down any immediately preceding label
to the aligned address.
- o It's not documented but auto alignment is reinstated by
+ o It's not documented but auto alignment is reinstated by
a .align pseudo instruction.
- o Note also that after auto alignment is turned off the mips assembler
+ o Note also that after auto alignment is turned off the mips assembler
issues an error on attempt to assemble an improperly aligned data item.
- We don't.
-
- */
+ We don't. */
temp = get_absolute_expression ();
if (temp > max_alignment)
temp_fill = 0;
if (temp)
{
+ segment_info_type *si = seg_info (now_seg);
+ struct insn_label_list *l = si->label_list;
+ /* Auto alignment should be switched on by next section change. */
auto_align = 1;
- mips_align (temp, (int) temp_fill,
- insn_labels != NULL ? insn_labels->label : NULL);
+ mips_align (temp, (int) temp_fill, l != NULL ? l->label : NULL);
}
else
{
as it would not be appropriate to use it in the section changing
functions in read.c, since obj-elf.c intercepts those. FIXME:
This should be cleaner, somehow. */
- obj_elf_section_change_hook ();
+ if (IS_ELF)
+ obj_elf_section_change_hook ();
#endif
mips_emit_delays ();
case 'r':
seg = subseg_new (RDATA_SECTION_NAME,
(subsegT) get_absolute_expression ());
- if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
+ if (IS_ELF)
{
bfd_set_section_flags (stdoutput, seg, (SEC_ALLOC | SEC_LOAD
| SEC_READONLY | SEC_RELOC
case 's':
seg = subseg_new (".sdata", (subsegT) get_absolute_expression ());
- if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
+ if (IS_ELF)
{
bfd_set_section_flags (stdoutput, seg,
SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA);
int section_entry_size;
int section_alignment;
- if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
+ if (!IS_ELF)
return;
section_name = input_line_pointer;
static void
s_cons (int log_size)
{
+ segment_info_type *si = seg_info (now_seg);
+ struct insn_label_list *l = si->label_list;
symbolS *label;
- label = insn_labels != NULL ? insn_labels->label : NULL;
+ label = l != NULL ? l->label : NULL;
mips_emit_delays ();
if (log_size > 0 && auto_align)
mips_align (log_size, 0, label);
static void
s_float_cons (int type)
{
+ segment_info_type *si = seg_info (now_seg);
+ struct insn_label_list *l = si->label_list;
symbolS *label;
- label = insn_labels != NULL ? insn_labels->label : NULL;
+ label = l != NULL ? l->label : NULL;
mips_emit_delays ();
{
mips_opts.nobopt = 1;
}
+ else if (strcmp (name, "gp=default") == 0)
+ mips_opts.gp32 = file_mips_gp32;
+ else if (strcmp (name, "gp=32") == 0)
+ mips_opts.gp32 = 1;
+ else if (strcmp (name, "gp=64") == 0)
+ {
+ if (!ISA_HAS_64BIT_REGS (mips_opts.isa))
+ as_warn ("%s isa does not support 64-bit registers",
+ mips_cpu_info_from_isa (mips_opts.isa)->name);
+ mips_opts.gp32 = 0;
+ }
+ else if (strcmp (name, "fp=default") == 0)
+ mips_opts.fp32 = file_mips_fp32;
+ else if (strcmp (name, "fp=32") == 0)
+ mips_opts.fp32 = 1;
+ else if (strcmp (name, "fp=64") == 0)
+ {
+ if (!ISA_HAS_64BIT_FPRS (mips_opts.isa))
+ as_warn ("%s isa does not support 64-bit floating point registers",
+ mips_cpu_info_from_isa (mips_opts.isa)->name);
+ mips_opts.fp32 = 0;
+ }
else if (strcmp (name, "mips16") == 0
|| strcmp (name, "MIPS-16") == 0)
mips_opts.mips16 = 1;
mips_opts.mips16 = 0;
else if (strcmp (name, "smartmips") == 0)
{
- if (!ISA_SUPPORT_SMARTMIPS)
+ if (!ISA_SUPPORTS_SMARTMIPS)
as_warn ("%s ISA does not support SmartMIPS ASE",
mips_cpu_info_from_isa (mips_opts.isa)->name);
mips_opts.ase_smartmips = 1;
else if (strcmp (name, "nomdmx") == 0)
mips_opts.ase_mdmx = 0;
else if (strcmp (name, "dsp") == 0)
- mips_opts.ase_dsp = 1;
+ {
+ if (!ISA_SUPPORTS_DSP_ASE)
+ as_warn ("%s ISA does not support DSP ASE",
+ mips_cpu_info_from_isa (mips_opts.isa)->name);
+ mips_opts.ase_dsp = 1;
+ mips_opts.ase_dspr2 = 0;
+ }
else if (strcmp (name, "nodsp") == 0)
- mips_opts.ase_dsp = 0;
+ {
+ mips_opts.ase_dsp = 0;
+ mips_opts.ase_dspr2 = 0;
+ }
+ else if (strcmp (name, "dspr2") == 0)
+ {
+ if (!ISA_SUPPORTS_DSPR2_ASE)
+ as_warn ("%s ISA does not support DSP R2 ASE",
+ mips_cpu_info_from_isa (mips_opts.isa)->name);
+ mips_opts.ase_dspr2 = 1;
+ mips_opts.ase_dsp = 1;
+ }
+ else if (strcmp (name, "nodspr2") == 0)
+ {
+ mips_opts.ase_dspr2 = 0;
+ mips_opts.ase_dsp = 0;
+ }
else if (strcmp (name, "mt") == 0)
- mips_opts.ase_mt = 1;
+ {
+ if (!ISA_SUPPORTS_MT_ASE)
+ as_warn ("%s ISA does not support MT ASE",
+ mips_cpu_info_from_isa (mips_opts.isa)->name);
+ mips_opts.ase_mt = 1;
+ }
else if (strcmp (name, "nomt") == 0)
mips_opts.ase_mt = 0;
else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0)
mips_opts.sym32 = TRUE;
else if (strcmp (name, "nosym32") == 0)
mips_opts.sym32 = FALSE;
+ else if (strchr (name, ','))
+ {
+ /* Generic ".set" directive; use the generic handler. */
+ *input_line_pointer = ch;
+ input_line_pointer = name;
+ s_set (0);
+ return;
+ }
else
{
as_warn (_("Tried to set unrecognized symbol: %s\n"), name);
The -mno-shared option replaces the last three instructions with
lui $gp,%hi(_gp)
- addiu $gp,$gp,%lo(_gp)
- */
+ addiu $gp,$gp,%lo(_gp) */
static void
s_cpsetup (int ignore ATTRIBUTE_UNUSED)
s_cplocal (int ignore ATTRIBUTE_UNUSED)
{
/* If we are not generating SVR4 PIC code, or if this is not NewABI code,
- .cplocal is ignored. */
+ .cplocal is ignored. */
if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
{
s_ignore (0);
ld $gp, offset($sp)
If a register $reg2 was given there, it results in:
- daddu $gp, $reg2, $0
- */
+ daddu $gp, $reg2, $0 */
+
static void
s_cpreturn (int ignore ATTRIBUTE_UNUSED)
{
demand_empty_rest_of_line ();
}
+/* Handle the .dtprelword and .dtpreldword pseudo-ops. They generate
+ a 32-bit or 64-bit DTP-relative relocation (BYTES says which) for
+ use in DWARF debug information. */
+
+static void
+s_dtprel_internal (size_t bytes)
+{
+ expressionS ex;
+ char *p;
+
+ expression (&ex);
+
+ if (ex.X_op != O_symbol)
+ {
+ as_bad (_("Unsupported use of %s"), (bytes == 8
+ ? ".dtpreldword"
+ : ".dtprelword"));
+ ignore_rest_of_line ();
+ }
+
+ p = frag_more (bytes);
+ md_number_to_chars (p, 0, bytes);
+ fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, FALSE,
+ (bytes == 8
+ ? BFD_RELOC_MIPS_TLS_DTPREL64
+ : BFD_RELOC_MIPS_TLS_DTPREL32));
+
+ demand_empty_rest_of_line ();
+}
+
+/* Handle .dtprelword. */
+
+static void
+s_dtprelword (int ignore ATTRIBUTE_UNUSED)
+{
+ s_dtprel_internal (4);
+}
+
+/* Handle .dtpreldword. */
+
+static void
+s_dtpreldword (int ignore ATTRIBUTE_UNUSED)
+{
+ s_dtprel_internal (8);
+}
+
/* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
code. It sets the offset to use in gp_rel relocations. */
static void
s_gpword (int ignore ATTRIBUTE_UNUSED)
{
+ segment_info_type *si;
+ struct insn_label_list *l;
symbolS *label;
expressionS ex;
char *p;
return;
}
- label = insn_labels != NULL ? insn_labels->label : NULL;
+ si = seg_info (now_seg);
+ l = si->label_list;
+ label = l != NULL ? l->label : NULL;
mips_emit_delays ();
if (auto_align)
mips_align (2, 0, label);
static void
s_gpdword (int ignore ATTRIBUTE_UNUSED)
{
+ segment_info_type *si;
+ struct insn_label_list *l;
symbolS *label;
expressionS ex;
char *p;
return;
}
- label = insn_labels != NULL ? insn_labels->label : NULL;
+ si = seg_info (now_seg);
+ l = si->label_list;
+ label = l != NULL ? l->label : NULL;
mips_emit_delays ();
if (auto_align)
mips_align (3, 0, label);
s_stab (type);
}
-/* Handle the .weakext pseudo-op as defined in Kane and Heinrich.
- */
+/* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */
static void
s_mips_weakext (int ignore ATTRIBUTE_UNUSED)
{
int align = bfd_get_section_alignment (stdoutput, seg);
-#ifdef OBJ_ELF
- /* We don't need to align ELF sections to the full alignment.
- However, Irix 5 may prefer that we align them at least to a 16
- byte boundary. We don't bother to align the sections if we are
- targeted for an embedded system. */
- if (strcmp (TARGET_OS, "elf") == 0)
- return addr;
- if (align > 4)
- align = 4;
-#endif
+ if (IS_ELF)
+ {
+ /* We don't need to align ELF sections to the full alignment.
+ However, Irix 5 may prefer that we align them at least to a 16
+ byte boundary. We don't bother to align the sections if we
+ are targeted for an embedded system. */
+ if (strcmp (TARGET_OS, "elf") == 0)
+ return addr;
+ if (align > 4)
+ align = 4;
+ }
return ((addr + (1 << align) - 1) & (-1 << align));
}
change = (strcmp (segname, ".sdata") != 0
&& strcmp (segname, ".sbss") != 0
&& strncmp (segname, ".sdata.", 7) != 0
+ && strncmp (segname, ".sbss.", 6) != 0
+ && strncmp (segname, ".gnu.linkonce.sb.", 17) != 0
&& strncmp (segname, ".gnu.linkonce.s.", 16) != 0);
}
return change;
pic_need_relax (symbolS *sym, asection *segtype)
{
asection *symsec;
- bfd_boolean linkonce;
/* Handle the case of a symbol equated to another symbol. */
while (symbol_equated_reloc_p (sym))
{
symbolS *n;
- /* It's possible to get a loop here in a badly written
- program. */
+ /* It's possible to get a loop here in a badly written program. */
n = symbol_get_value_expression (sym)->X_add_symbol;
if (n == sym)
break;
sym = n;
}
- symsec = S_GET_SEGMENT (sym);
-
- /* duplicate the test for LINK_ONCE sections as in adjust_reloc_syms */
- linkonce = FALSE;
- if (symsec != segtype && ! S_IS_LOCAL (sym))
- {
- if ((bfd_get_section_flags (stdoutput, symsec) & SEC_LINK_ONCE)
- != 0)
- linkonce = TRUE;
+ if (symbol_section_p (sym))
+ return TRUE;
- /* The GNU toolchain uses an extension for ELF: a section
- beginning with the magic string .gnu.linkonce is a linkonce
- section. */
- if (strncmp (segment_name (symsec), ".gnu.linkonce",
- sizeof ".gnu.linkonce" - 1) == 0)
- linkonce = TRUE;
- }
+ symsec = S_GET_SEGMENT (sym);
/* This must duplicate the test in adjust_reloc_syms. */
return (symsec != &bfd_und_section
&& symsec != &bfd_abs_section
- && ! bfd_is_com_section (symsec)
- && !linkonce
+ && !bfd_is_com_section (symsec)
+ && !s_is_linkonce (sym, segtype)
#ifdef OBJ_ELF
/* A global or weak symbol is treated as external. */
- && (OUTPUT_FLAVOR != bfd_target_elf_flavour
- || (! S_IS_WEAK (sym) && ! S_IS_EXTERNAL (sym)))
+ && (!IS_ELF || (! S_IS_WEAK (sym) && ! S_IS_EXTERNAL (sym)))
#endif
);
}
mips16_extended_frag (fragS *fragp, asection *sec, long stretch)
{
int type;
- register const struct mips16_immed_operand *op;
+ const struct mips16_immed_operand *op;
offsetT val;
int mintiny, maxtiny;
segT symsec;
int
mips_fix_adjustable (fixS *fixp)
{
- /* Don't adjust MIPS16 jump relocations, so we don't have to worry
- about the format of the offset in the .o file. */
- if (fixp->fx_r_type == BFD_RELOC_MIPS16_JMP)
- return 0;
-
if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
|| fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
return 0;
return 0;
#ifdef OBJ_ELF
- /* Don't adjust relocations against mips16 symbols, so that the linker
- can find them if it needs to set up a stub. */
- if (OUTPUT_FLAVOR == bfd_target_elf_flavour
- && S_GET_OTHER (fixp->fx_addsy) == STO_MIPS16
- && fixp->fx_subsy == NULL)
+ /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve
+ to a floating-point stub. The same is true for non-R_MIPS16_26
+ relocations against MIPS16 functions; in this case, the stub becomes
+ the function's canonical address.
+
+ Floating-point stubs are stored in unique .mips16.call.* or
+ .mips16.fn.* sections. If a stub T for function F is in section S,
+ the first relocation in section S must be against F; this is how the
+ linker determines the target function. All relocations that might
+ resolve to T must also be against F. We therefore have the following
+ restrictions, which are given in an intentionally-redundant way:
+
+ 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16
+ symbols.
+
+ 2. We cannot reduce a stub's relocations against non-MIPS16 symbols
+ if that stub might be used.
+
+ 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16
+ symbols.
+
+ 4. We cannot reduce a stub's relocations against MIPS16 symbols if
+ that stub might be used.
+
+ There is a further restriction:
+
+ 5. We cannot reduce R_MIPS16_26 relocations against MIPS16 symbols
+ on targets with in-place addends; the relocation field cannot
+ encode the low bit.
+
+ For simplicity, we deal with (3)-(5) by not reducing _any_ relocation
+ against a MIPS16 symbol.
+
+ We deal with (1)-(2) by saying that, if there's a R_MIPS16_26
+ relocation against some symbol R, no relocation against R may be
+ reduced. (Note that this deals with (2) as well as (1) because
+ relocations against global symbols will never be reduced on ELF
+ targets.) This approach is a little simpler than trying to detect
+ stub sections, and gives the "all or nothing" per-symbol consistency
+ that we have for MIPS16 symbols. */
+ if (IS_ELF
+ && fixp->fx_subsy == NULL
+ && (S_GET_OTHER (fixp->fx_addsy) == STO_MIPS16
+ || *symbol_get_tc (fixp->fx_addsy)))
return 0;
#endif
/* At this point, fx_addnumber is "symbol offset - pcrel address".
Relocations want only the symbol offset. */
reloc->addend = fixp->fx_addnumber + reloc->address;
- if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
+ if (!IS_ELF)
{
/* A gruesome hack which is a result of the gruesome gas
reloc handling. What's worse, for COFF (as opposed to
exp.X_add_number = fragp->fr_offset;
fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
- 4, &exp, 1, BFD_RELOC_16_PCREL_S2);
+ 4, &exp, TRUE, BFD_RELOC_16_PCREL_S2);
fixp->fx_file = fragp->fr_file;
fixp->fx_line = fragp->fr_line;
case 0:
/* bltz 0x04000000 bgez 0x04010000
- bltzal 0x04100000 bgezal 0x04110000 */
+ bltzal 0x04100000 bgezal 0x04110000 */
assert ((insn & 0xfc0e0000) == 0x04000000);
insn ^= 0x00010000;
break;
case 1:
/* beq 0x10000000 bne 0x14000000
- blez 0x18000000 bgtz 0x1c000000 */
+ blez 0x18000000 bgtz 0x1c000000 */
insn ^= 0x04000000;
break;
/* Clear the and-link bit. */
assert ((insn & 0xfc1c0000) == 0x04100000);
- /* bltzal 0x04100000 bgezal 0x04110000
- bltzall 0x04120000 bgezall 0x04130000 */
+ /* bltzal 0x04100000 bgezal 0x04110000
+ bltzall 0x04120000 bgezall 0x04130000 */
insn &= ~0x00100000;
}
md_number_to_chars ((char *) buf, insn, 4);
buf += 4;
- /* Nop */
+ /* nop */
md_number_to_chars ((char *) buf, 0, 4);
buf += 4;
exp.X_add_number = fragp->fr_offset;
fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
- 4, &exp, 0, BFD_RELOC_MIPS_JMP);
+ 4, &exp, FALSE, BFD_RELOC_MIPS_JMP);
fixp->fx_file = fragp->fr_file;
fixp->fx_line = fragp->fr_line;
}
fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
- 4, &exp, 0, BFD_RELOC_MIPS_GOT16);
+ 4, &exp, FALSE, BFD_RELOC_MIPS_GOT16);
fixp->fx_file = fragp->fr_file;
fixp->fx_line = fragp->fr_line;
insn = HAVE_64BIT_ADDRESSES ? 0x64210000 : 0x24210000;
fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
- 4, &exp, 0, BFD_RELOC_LO16);
+ 4, &exp, FALSE, BFD_RELOC_LO16);
fixp->fx_file = fragp->fr_file;
fixp->fx_line = fragp->fr_line;
if (RELAX_MIPS16_P (fragp->fr_subtype))
{
int type;
- register const struct mips16_immed_operand *op;
+ const struct mips16_immed_operand *op;
bfd_boolean small, ext;
offsetT val;
bfd_byte *buf;
asymbol **syms;
unsigned int count, i;
- if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
+ if (!IS_ELF)
return;
syms = bfd_get_outsymbols (stdoutput);
void
mips_define_label (symbolS *sym)
{
+ segment_info_type *si = seg_info (now_seg);
struct insn_label_list *l;
if (free_insn_labels == NULL)
}
l->label = sym;
- l->next = insn_labels;
- insn_labels = l;
+ l->next = si->label_list;
+ si->label_list = l;
#ifdef OBJ_ELF
dwarf2_emit_label (sym);
/* Set MIPS ELF flags for ASEs. */
/* We may need to define a new flag for DSP ASE, and set this flag when
file_ase_dsp is true. */
+ /* Same for DSP R2. */
/* We may need to define a new flag for MT ASE, and set this flag when
file_ase_mt is true. */
if (file_ase_mips16)
if (mips_32bitmode)
elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE;
+
+#if 0 /* XXX FIXME */
+ /* 32 bit code with 64 bit FP registers. */
+ if (!file_mips_fp32 && ABI_NEEDS_32BIT_REGS (mips_abi))
+ elf_elfheader (stdoutput)->e_flags |= ???;
+#endif
}
#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
static void
md_obj_end (void)
{
- /* check for premature end, nesting errors, etc */
+ /* Check for premature end, nesting errors, etc. */
if (cur_proc_ptr)
as_warn (_("missing .end at end of assembly"));
}
}
/* Generate a .pdr section. */
- if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING
- && mips_flag_pdr)
+ if (IS_ELF && !ECOFF_DEBUGGING && mips_flag_pdr)
{
segT saved_seg = now_seg;
subsegT saved_subseg = now_subseg;
s_mips_frame (int ignore ATTRIBUTE_UNUSED)
{
#ifdef OBJ_ELF
- if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING)
+ if (IS_ELF && !ECOFF_DEBUGGING)
{
long val;
s_mips_mask (int reg_type)
{
#ifdef OBJ_ELF
- if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING)
+ if (IS_ELF && !ECOFF_DEBUGGING)
{
long mask, off;
static const struct mips_cpu_info mips_cpu_info_table[] =
{
/* Entries for generic ISAs */
- { "mips1", 1, ISA_MIPS1, CPU_R3000 },
- { "mips2", 1, ISA_MIPS2, CPU_R6000 },
- { "mips3", 1, ISA_MIPS3, CPU_R4000 },
- { "mips4", 1, ISA_MIPS4, CPU_R8000 },
- { "mips5", 1, ISA_MIPS5, CPU_MIPS5 },
- { "mips32", 1, ISA_MIPS32, CPU_MIPS32 },
- { "mips32r2", 1, ISA_MIPS32R2, CPU_MIPS32R2 },
- { "mips64", 1, ISA_MIPS64, CPU_MIPS64 },
- { "mips64r2", 1, ISA_MIPS64R2, CPU_MIPS64R2 },
+ { "mips1", MIPS_CPU_IS_ISA, ISA_MIPS1, CPU_R3000 },
+ { "mips2", MIPS_CPU_IS_ISA, ISA_MIPS2, CPU_R6000 },
+ { "mips3", MIPS_CPU_IS_ISA, ISA_MIPS3, CPU_R4000 },
+ { "mips4", MIPS_CPU_IS_ISA, ISA_MIPS4, CPU_R8000 },
+ { "mips5", MIPS_CPU_IS_ISA, ISA_MIPS5, CPU_MIPS5 },
+ { "mips32", MIPS_CPU_IS_ISA, ISA_MIPS32, CPU_MIPS32 },
+ { "mips32r2", MIPS_CPU_IS_ISA, ISA_MIPS32R2, CPU_MIPS32R2 },
+ { "mips64", MIPS_CPU_IS_ISA, ISA_MIPS64, CPU_MIPS64 },
+ { "mips64r2", MIPS_CPU_IS_ISA, ISA_MIPS64R2, CPU_MIPS64R2 },
/* MIPS I */
- { "r3000", 0, ISA_MIPS1, CPU_R3000 },
- { "r2000", 0, ISA_MIPS1, CPU_R3000 },
- { "r3900", 0, ISA_MIPS1, CPU_R3900 },
+ { "r3000", 0, ISA_MIPS1, CPU_R3000 },
+ { "r2000", 0, ISA_MIPS1, CPU_R3000 },
+ { "r3900", 0, ISA_MIPS1, CPU_R3900 },
/* MIPS II */
- { "r6000", 0, ISA_MIPS2, CPU_R6000 },
+ { "r6000", 0, ISA_MIPS2, CPU_R6000 },
/* MIPS III */
- { "r4000", 0, ISA_MIPS3, CPU_R4000 },
- { "r4010", 0, ISA_MIPS2, CPU_R4010 },
- { "vr4100", 0, ISA_MIPS3, CPU_VR4100 },
- { "vr4111", 0, ISA_MIPS3, CPU_R4111 },
- { "vr4120", 0, ISA_MIPS3, CPU_VR4120 },
- { "vr4130", 0, ISA_MIPS3, CPU_VR4120 },
- { "vr4181", 0, ISA_MIPS3, CPU_R4111 },
- { "vr4300", 0, ISA_MIPS3, CPU_R4300 },
- { "r4400", 0, ISA_MIPS3, CPU_R4400 },
- { "r4600", 0, ISA_MIPS3, CPU_R4600 },
- { "orion", 0, ISA_MIPS3, CPU_R4600 },
- { "r4650", 0, ISA_MIPS3, CPU_R4650 },
+ { "r4000", 0, ISA_MIPS3, CPU_R4000 },
+ { "r4010", 0, ISA_MIPS2, CPU_R4010 },
+ { "vr4100", 0, ISA_MIPS3, CPU_VR4100 },
+ { "vr4111", 0, ISA_MIPS3, CPU_R4111 },
+ { "vr4120", 0, ISA_MIPS3, CPU_VR4120 },
+ { "vr4130", 0, ISA_MIPS3, CPU_VR4120 },
+ { "vr4181", 0, ISA_MIPS3, CPU_R4111 },
+ { "vr4300", 0, ISA_MIPS3, CPU_R4300 },
+ { "r4400", 0, ISA_MIPS3, CPU_R4400 },
+ { "r4600", 0, ISA_MIPS3, CPU_R4600 },
+ { "orion", 0, ISA_MIPS3, CPU_R4600 },
+ { "r4650", 0, ISA_MIPS3, CPU_R4650 },
/* MIPS IV */
- { "r8000", 0, ISA_MIPS4, CPU_R8000 },
- { "r10000", 0, ISA_MIPS4, CPU_R10000 },
- { "r12000", 0, ISA_MIPS4, CPU_R12000 },
- { "vr5000", 0, ISA_MIPS4, CPU_R5000 },
- { "vr5400", 0, ISA_MIPS4, CPU_VR5400 },
- { "vr5500", 0, ISA_MIPS4, CPU_VR5500 },
- { "rm5200", 0, ISA_MIPS4, CPU_R5000 },
- { "rm5230", 0, ISA_MIPS4, CPU_R5000 },
- { "rm5231", 0, ISA_MIPS4, CPU_R5000 },
- { "rm5261", 0, ISA_MIPS4, CPU_R5000 },
- { "rm5721", 0, ISA_MIPS4, CPU_R5000 },
- { "rm7000", 0, ISA_MIPS4, CPU_RM7000 },
- { "rm9000", 0, ISA_MIPS4, CPU_RM9000 },
+ { "r8000", 0, ISA_MIPS4, CPU_R8000 },
+ { "r10000", 0, ISA_MIPS4, CPU_R10000 },
+ { "r12000", 0, ISA_MIPS4, CPU_R12000 },
+ { "vr5000", 0, ISA_MIPS4, CPU_R5000 },
+ { "vr5400", 0, ISA_MIPS4, CPU_VR5400 },
+ { "vr5500", 0, ISA_MIPS4, CPU_VR5500 },
+ { "rm5200", 0, ISA_MIPS4, CPU_R5000 },
+ { "rm5230", 0, ISA_MIPS4, CPU_R5000 },
+ { "rm5231", 0, ISA_MIPS4, CPU_R5000 },
+ { "rm5261", 0, ISA_MIPS4, CPU_R5000 },
+ { "rm5721", 0, ISA_MIPS4, CPU_R5000 },
+ { "rm7000", 0, ISA_MIPS4, CPU_RM7000 },
+ { "rm9000", 0, ISA_MIPS4, CPU_RM9000 },
/* MIPS 32 */
- { "4kc", 0, ISA_MIPS32, CPU_MIPS32 },
- { "4km", 0, ISA_MIPS32, CPU_MIPS32 },
- { "4kp", 0, ISA_MIPS32, CPU_MIPS32 },
-
- /* MIPS32 Release 2 */
- { "m4k", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
- { "24k", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
- { "24kc", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
- { "24kf", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
- { "24kx", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
+ { "4kc", 0, ISA_MIPS32, CPU_MIPS32 },
+ { "4km", 0, ISA_MIPS32, CPU_MIPS32 },
+ { "4kp", 0, ISA_MIPS32, CPU_MIPS32 },
+ { "4ksc", MIPS_CPU_ASE_SMARTMIPS, ISA_MIPS32, CPU_MIPS32 },
+
+ /* MIPS 32 Release 2 */
+ { "4kec", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
+ { "4kem", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
+ { "4kep", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
+ { "4ksd", MIPS_CPU_ASE_SMARTMIPS, ISA_MIPS32R2, CPU_MIPS32R2 },
+ { "m4k", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
+ { "m4kp", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
+ { "24kc", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
+ { "24kf2_1", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
+ { "24kf", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
+ { "24kf1_1", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
+ /* Deprecated forms of the above. */
+ { "24kfx", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
+ { "24kx", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
+ /* 24KE is a 24K with DSP ASE, other ASEs are optional. */
+ { "24kec", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
+ { "24kef2_1", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
+ { "24kef", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
+ { "24kef1_1", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
+ /* Deprecated forms of the above. */
+ { "24kefx", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
+ { "24kex", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
+ /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */
+ { "34kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
+ ISA_MIPS32R2, CPU_MIPS32R2 },
+ { "34kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
+ ISA_MIPS32R2, CPU_MIPS32R2 },
+ { "34kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
+ ISA_MIPS32R2, CPU_MIPS32R2 },
+ { "34kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
+ ISA_MIPS32R2, CPU_MIPS32R2 },
+ /* Deprecated forms of the above. */
+ { "34kfx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
+ ISA_MIPS32R2, CPU_MIPS32R2 },
+ { "34kx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
+ ISA_MIPS32R2, CPU_MIPS32R2 },
+ /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */
+ { "74kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
+ ISA_MIPS32R2, CPU_MIPS32R2 },
+ { "74kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
+ ISA_MIPS32R2, CPU_MIPS32R2 },
+ { "74kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
+ ISA_MIPS32R2, CPU_MIPS32R2 },
+ { "74kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
+ ISA_MIPS32R2, CPU_MIPS32R2 },
+ { "74kf3_2", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
+ ISA_MIPS32R2, CPU_MIPS32R2 },
+ /* Deprecated forms of the above. */
+ { "74kfx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
+ ISA_MIPS32R2, CPU_MIPS32R2 },
+ { "74kx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
+ ISA_MIPS32R2, CPU_MIPS32R2 },
/* MIPS 64 */
- { "5kc", 0, ISA_MIPS64, CPU_MIPS64 },
- { "5kf", 0, ISA_MIPS64, CPU_MIPS64 },
- { "20kc", 0, ISA_MIPS64, CPU_MIPS64 },
+ { "5kc", 0, ISA_MIPS64, CPU_MIPS64 },
+ { "5kf", 0, ISA_MIPS64, CPU_MIPS64 },
+ { "20kc", MIPS_CPU_ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 },
+ { "25kf", MIPS_CPU_ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 },
+
+ /* MIPS 64 Release 2 */
/* Broadcom SB-1 CPU core */
- { "sb1", 0, ISA_MIPS64, CPU_SB1 },
+ { "sb1", MIPS_CPU_ASE_MIPS3D | MIPS_CPU_ASE_MDMX,
+ ISA_MIPS64, CPU_SB1 },
+ /* Broadcom SB-1A CPU core */
+ { "sb1a", MIPS_CPU_ASE_MIPS3D | MIPS_CPU_ASE_MDMX,
+ ISA_MIPS64, CPU_SB1 },
/* End marker */
{ NULL, 0, 0, 0 }
int i;
for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
- if (mips_cpu_info_table[i].is_isa
+ if ((mips_cpu_info_table[i].flags & MIPS_CPU_IS_ISA)
&& isa == mips_cpu_info_table[i].isa)
return (&mips_cpu_info_table[i]);
-mdsp generate DSP instructions\n\
-mno-dsp do not generate DSP instructions\n"));
fprintf (stream, _("\
+-mdspr2 generate DSP R2 instructions\n\
+-mno-dspr2 do not generate DSP R2 instructions\n"));
+ fprintf (stream, _("\
-mmt generate MT instructions\n\
-mno-mt do not generate MT instructions\n"));
fprintf (stream, _("\
-mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
-mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
-mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
--mno-shared optimize output for executables\n\
-msym32 assume all symbols have 32-bit values\n\
-O0 remove unneeded NOPs, do not swap branches\n\
-O remove unneeded NOPs and swap branches\n\
#ifdef OBJ_ELF
fprintf (stream, _("\
-KPIC, -call_shared generate SVR4 position independent code\n\
+-mvxworks-pic generate VxWorks position independent code\n\
-non_shared do not generate position independent code\n\
-xgot assume a 32 bit GOT\n\
-mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
-mshared, -mno-shared disable/enable .cpload optimization for\n\
- non-shared code\n\
+ position dependent (non shared) code\n\
-mabi=ABI create ABI conformant object file for:\n"));
first = 1;
enum dwarf2_format
mips_dwarf2_format (void)
{
- if (mips_abi == N64_ABI)
+ if (HAVE_64BIT_SYMBOLS)
{
#ifdef TE_IRIX
return dwarf2_format_64bit_irix;
int
mips_dwarf2_addr_size (void)
{
- if (mips_abi == N64_ABI)
+ if (HAVE_64BIT_SYMBOLS)
return 8;
else
return 4;
projects / binutils-gdb.git / blobdiff