/* tc-nds32.c -- Assemble for the nds32
- Copyright (C) 2012-2019 Free Software Foundation, Inc.
+ Copyright (C) 2012-2021 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GAS, the GNU Assembler.
static int enable_16bit = 1;
/* Save for md_assemble to distinguish if this instruction is
expanded from the pseudo instruction. */
-static bfd_boolean pseudo_opcode = FALSE;
+static bool pseudo_opcode = false;
static struct nds32_relocs_pattern *relocs_list = NULL;
/* Save instruction relation to inserting relaxation relocation. */
struct nds32_relocs_pattern
".flag verbatim" at beginning of the content. We have
'nds32_flag' to parse it and set this field to be non-zero. */
static int verbatim = 0;
-static struct hash_control *nds32_gprs_hash;
-static struct hash_control *nds32_hint_hash;
+static htab_t nds32_gprs_hash;
+static htab_t nds32_hint_hash;
#define TLS_REG "$r27"
#define GOT_NAME "_GLOBAL_OFFSET_TABLE_"
static int in_omit_fp = 0;
extern struct nds32_keyword keyword_gpr[];
/* Tag there is relax relocation having to link. */
-static bfd_boolean relaxing = FALSE;
+static bool relaxing = false;
/* ICT model. */
enum ict_option {
ICT_NONE = 0,
static enum ict_option ict_flag = ICT_NONE;
\f
-static struct hash_control *nds32_relax_info_hash;
+static htab_t nds32_relax_info_hash;
/* Branch patterns. */
static relax_info_t relax_table[] =
.br_range = BR_RANGE_S16M,
.cond_field =
{
- {0, 0, 0, FALSE}
+ {0, 0, 0, false}
},
.relax_code_seq[BR_RANGE_S256] =
{
.br_range = BR_RANGE_S64K,
.cond_field =
{
- {0, 20, 0x1F, FALSE},
- {0, 0, 0, FALSE}
+ {0, 20, 0x1F, false},
+ {0, 0, 0, false}
},
.relax_code_seq[BR_RANGE_S256] =
{
},
.relax_code_condition[BR_RANGE_S256] =
{
- {0, 20, 0x1F, FALSE},
- {0, 0, 0, FALSE},
+ {0, 20, 0x1F, false},
+ {0, 0, 0, false},
},
.relax_code_size[BR_RANGE_S256] = 4,
.relax_branch_isize[BR_RANGE_S256] = 4,
},
.relax_code_condition[BR_RANGE_S16K] =
{
- {0, 20, 0x1F, FALSE},
- {0, 0, 0, FALSE},
+ {0, 20, 0x1F, false},
+ {0, 0, 0, false},
},
.relax_code_size[BR_RANGE_S16K] = 4,
.relax_branch_isize[BR_RANGE_S16K] = 4,
},
.relax_code_condition[BR_RANGE_S64K] =
{
- {0, 20, 0x1F, FALSE},
- {0, 0, 0, FALSE},
+ {0, 20, 0x1F, false},
+ {0, 0, 0, false},
},
.relax_code_size[BR_RANGE_S64K] = 4,
.relax_branch_isize[BR_RANGE_S64K] = 4,
},
.relax_code_condition[BR_RANGE_S16M] =
{
- {0, 20, 0x1F, FALSE},
- {0, 0, 0, FALSE},
+ {0, 20, 0x1F, false},
+ {0, 0, 0, false},
},
.relax_code_size[BR_RANGE_S16M] = 8,
.relax_branch_isize[BR_RANGE_S16M] = 4,
},
.relax_code_condition[BR_RANGE_U4G] =
{
- {0, 20, 0x1F, FALSE},
- {0, 0, 0, FALSE},
+ {0, 20, 0x1F, false},
+ {0, 0, 0, false},
},
.relax_code_size[BR_RANGE_U4G] = 16,
.relax_branch_isize[BR_RANGE_U4G] = 4,
.br_range = BR_RANGE_S64K,
.cond_field =
{
- {0, 20, 0x1F, FALSE},
- {0, 0, 0, FALSE}
+ {0, 20, 0x1F, false},
+ {0, 0, 0, false}
},
.relax_code_seq[BR_RANGE_S256] =
{
},
.relax_code_condition[BR_RANGE_S256] =
{
- {0, 20, 0x1F, FALSE},
- {0, 0, 0, FALSE},
+ {0, 20, 0x1F, false},
+ {0, 0, 0, false},
},
.relax_code_size[BR_RANGE_S256] = 4,
.relax_branch_isize[BR_RANGE_S256] = 4,
},
.relax_code_condition[BR_RANGE_S16K] =
{
- {0, 20, 0x1F, FALSE},
- {0, 0, 0, FALSE},
+ {0, 20, 0x1F, false},
+ {0, 0, 0, false},
},
.relax_code_size[BR_RANGE_S16K] = 4,
.relax_branch_isize[BR_RANGE_S16K] = 4,
},
.relax_code_condition[BR_RANGE_S64K] =
{
- {0, 20, 0x1F, FALSE},
- {0, 0, 0, FALSE},
+ {0, 20, 0x1F, false},
+ {0, 0, 0, false},
},
.relax_code_size[BR_RANGE_S64K] = 4,
.relax_branch_isize[BR_RANGE_S64K] = 4,
},
.relax_code_condition[BR_RANGE_S16M] =
{
- {0, 20, 0x1F, FALSE},
- {0, 0, 0, FALSE},
+ {0, 20, 0x1F, false},
+ {0, 0, 0, false},
},
.relax_code_size[BR_RANGE_S16M] = 8,
.relax_branch_isize[BR_RANGE_S16M] = 4,
},
.relax_code_condition[BR_RANGE_U4G] =
{
- {0, 20, 0x1F, FALSE},
- {0, 0, 0, FALSE},
+ {0, 20, 0x1F, false},
+ {0, 0, 0, false},
},
.relax_code_size[BR_RANGE_U4G] = 16,
.relax_branch_isize[BR_RANGE_U4G] = 4,
.br_range = BR_RANGE_S16M,
.cond_field =
{
- {0, 0, 0, FALSE}
+ {0, 0, 0, false}
},
.relax_code_seq[BR_RANGE_S256] =
{
.br_range = BR_RANGE_S256,
.cond_field =
{
- {0, 0, 0, FALSE}
+ {0, 0, 0, false}
},
.relax_code_seq[BR_RANGE_S256] =
{
.br_range = BR_RANGE_S64K,
.cond_field =
{
- {0, 20, 0x1F, FALSE},
- {0, 0, 0, FALSE}
+ {0, 20, 0x1F, false},
+ {0, 0, 0, false}
},
/* We do not use beqz38 and beqzs8 here directly because we
don't want to check register number for specail condition. */
},
.relax_code_condition[BR_RANGE_S256] =
{
- {0, 20, 0x1F, FALSE},
- {0, 0, 0, FALSE},
+ {0, 20, 0x1F, false},
+ {0, 0, 0, false},
},
.relax_code_size[BR_RANGE_S256] = 4,
.relax_branch_isize[BR_RANGE_S256] = 4,
},
.relax_code_condition[BR_RANGE_S16K] =
{
- {0, 20, 0x1F, FALSE},
- {0, 0, 0, FALSE},
+ {0, 20, 0x1F, false},
+ {0, 0, 0, false},
},
.relax_code_size[BR_RANGE_S16K] = 4,
.relax_branch_isize[BR_RANGE_S16K] = 4,
},
.relax_code_condition[BR_RANGE_S64K] =
{
- {0, 20, 0x1F, FALSE},
- {0, 0, 0, FALSE},
+ {0, 20, 0x1F, false},
+ {0, 0, 0, false},
},
.relax_code_size[BR_RANGE_S64K] = 4,
.relax_branch_isize[BR_RANGE_S64K] = 4,
},
.relax_code_condition[BR_RANGE_S16M] =
{
- {0, 20, 0x1F, FALSE},
- {0, 0, 0, FALSE},
+ {0, 20, 0x1F, false},
+ {0, 0, 0, false},
},
.relax_code_size[BR_RANGE_S16M] = 8,
.relax_branch_isize[BR_RANGE_S16M] = 4,
},
.relax_code_condition[BR_RANGE_U4G] =
{
- {0, 20, 0x1F, FALSE},
- {0, 0, 0, FALSE},
+ {0, 20, 0x1F, false},
+ {0, 0, 0, false},
},
.relax_code_size[BR_RANGE_U4G] = 16,
.relax_branch_isize[BR_RANGE_U4G] = 4,
.br_range = BR_RANGE_S64K,
.cond_field =
{
- {0, 20, 0x1F, FALSE},
- {0, 0, 0, FALSE}
+ {0, 20, 0x1F, false},
+ {0, 0, 0, false}
},
.relax_code_seq[BR_RANGE_S256] =
{
},
.relax_code_condition[BR_RANGE_S256] =
{
- {0, 20, 0x1F, FALSE},
- {0, 0, 0, FALSE},
+ {0, 20, 0x1F, false},
+ {0, 0, 0, false},
},
.relax_code_size[BR_RANGE_S256] = 4,
.relax_branch_isize[BR_RANGE_S256] = 4,
},
.relax_code_condition[BR_RANGE_S16K] =
{
- {0, 20, 0x1F, FALSE},
- {0, 0, 0, FALSE},
+ {0, 20, 0x1F, false},
+ {0, 0, 0, false},
},
.relax_code_size[BR_RANGE_S16K] = 4,
.relax_branch_isize[BR_RANGE_S16K] = 4,
},
.relax_code_condition[BR_RANGE_S64K] =
{
- {0, 20, 0x1F, FALSE},
- {0, 0, 0, FALSE},
+ {0, 20, 0x1F, false},
+ {0, 0, 0, false},
},
.relax_code_size[BR_RANGE_S64K] = 4,
.relax_branch_isize[BR_RANGE_S64K] = 4,
},
.relax_code_condition[BR_RANGE_S16M] =
{
- {0, 20, 0x1F, FALSE},
- {0, 0, 0, FALSE},
+ {0, 20, 0x1F, false},
+ {0, 0, 0, false},
},
.relax_code_size[BR_RANGE_S16M] = 8,
.relax_branch_isize[BR_RANGE_S16M] = 4,
},
.relax_code_condition[BR_RANGE_U4G] =
{
- {0, 20, 0x1F, FALSE},
- {0, 0, 0, FALSE},
+ {0, 20, 0x1F, false},
+ {0, 0, 0, false},
},
.relax_code_size[BR_RANGE_U4G] = 16,
.relax_branch_isize[BR_RANGE_U4G] = 4,
.br_range = BR_RANGE_S64K,
.cond_field =
{
- {0, 20, 0x1F, FALSE},
- {0, 0, 0, FALSE}
+ {0, 20, 0x1F, false},
+ {0, 0, 0, false}
},
.relax_code_seq[BR_RANGE_S256] =
{
},
.relax_code_condition[BR_RANGE_S256] =
{
- {0, 20, 0x1F, FALSE},
- {0, 0, 0, FALSE},
+ {0, 20, 0x1F, false},
+ {0, 0, 0, false},
},
.relax_code_size[BR_RANGE_S256] = 4,
.relax_branch_isize[BR_RANGE_S256] = 4,
},
.relax_code_condition[BR_RANGE_S16K] =
{
- {0, 20, 0x1F, FALSE},
- {0, 0, 0, FALSE},
+ {0, 20, 0x1F, false},
+ {0, 0, 0, false},
},
.relax_code_size[BR_RANGE_S16K] = 4,
.relax_branch_isize[BR_RANGE_S16K] = 4,
},
.relax_code_condition[BR_RANGE_S64K] =
{
- {0, 20, 0x1F, FALSE},
- {0, 0, 0, FALSE},
+ {0, 20, 0x1F, false},
+ {0, 0, 0, false},
},
.relax_code_size[BR_RANGE_S64K] = 4,
.relax_branch_isize[BR_RANGE_S64K] = 4,
},
.relax_code_condition[BR_RANGE_S16M] =
{
- {0, 20, 0x1F, FALSE},
- {0, 0, 0, FALSE},
+ {0, 20, 0x1F, false},
+ {0, 0, 0, false},
},
.relax_code_size[BR_RANGE_S16M] = 8,
.relax_branch_isize[BR_RANGE_S16M] = 4,
},
.relax_code_condition[BR_RANGE_U4G] =
{
- {0, 20, 0x1F, FALSE},
- {0, 0, 0, FALSE},
+ {0, 20, 0x1F, false},
+ {0, 0, 0, false},
},
.relax_code_size[BR_RANGE_U4G] = 16,
.relax_branch_isize[BR_RANGE_U4G] = 4,
.br_range = BR_RANGE_S64K,
.cond_field =
{
- {0, 20, 0x1F, FALSE},
- {0, 0, 0, FALSE}
+ {0, 20, 0x1F, false},
+ {0, 0, 0, false}
},
.relax_code_seq[BR_RANGE_S256] =
{
},
.relax_code_condition[BR_RANGE_S256] =
{
- {0, 20, 0x1F, FALSE},
- {0, 0, 0, FALSE},
+ {0, 20, 0x1F, false},
+ {0, 0, 0, false},
},
.relax_code_size[BR_RANGE_S256] = 4,
.relax_branch_isize[BR_RANGE_S256] = 4,
},
.relax_code_condition[BR_RANGE_S16K] =
{
- {0, 20, 0x1F, FALSE},
- {0, 0, 0, FALSE},
+ {0, 20, 0x1F, false},
+ {0, 0, 0, false},
},
.relax_code_size[BR_RANGE_S16K] = 4,
.relax_branch_isize[BR_RANGE_S16K] = 4,
},
.relax_code_condition[BR_RANGE_S64K] =
{
- {0, 20, 0x1F, FALSE},
- {0, 0, 0, FALSE},
+ {0, 20, 0x1F, false},
+ {0, 0, 0, false},
},
.relax_code_size[BR_RANGE_S64K] = 4,
.relax_branch_isize[BR_RANGE_S64K] = 4,
},
.relax_code_condition[BR_RANGE_S16M] =
{
- {0, 20, 0x1F, FALSE},
- {0, 0, 0, FALSE},
+ {0, 20, 0x1F, false},
+ {0, 0, 0, false},
},
.relax_code_size[BR_RANGE_S16M] = 8,
.relax_branch_isize[BR_RANGE_S16M] = 4,
},
.relax_code_condition[BR_RANGE_U4G] =
{
- {0, 20, 0x1F, FALSE},
- {0, 0, 0, FALSE},
+ {0, 20, 0x1F, false},
+ {0, 0, 0, false},
},
.relax_code_size[BR_RANGE_U4G] = 16,
.relax_branch_isize[BR_RANGE_U4G] = 4,
.br_range = BR_RANGE_S64K,
.cond_field =
{
- {0, 20, 0x1F, FALSE},
- {0, 0, 0, FALSE}
+ {0, 20, 0x1F, false},
+ {0, 0, 0, false}
},
.relax_code_seq[BR_RANGE_S256] =
{
},
.relax_code_condition[BR_RANGE_S256] =
{
- {0, 20, 0x1F, FALSE},
- {0, 0, 0, FALSE},
+ {0, 20, 0x1F, false},
+ {0, 0, 0, false},
},
.relax_code_size[BR_RANGE_S256] = 4,
.relax_branch_isize[BR_RANGE_S256] = 4,
},
.relax_code_condition[BR_RANGE_S16K] =
{
- {0, 20, 0x1F, FALSE},
- {0, 0, 0, FALSE},
+ {0, 20, 0x1F, false},
+ {0, 0, 0, false},
},
.relax_code_size[BR_RANGE_S16K] = 4,
.relax_branch_isize[BR_RANGE_S16K] = 4,
},
.relax_code_condition[BR_RANGE_S64K] =
{
- {0, 20, 0x1F, FALSE},
- {0, 0, 0, FALSE},
+ {0, 20, 0x1F, false},
+ {0, 0, 0, false},
},
.relax_code_size[BR_RANGE_S64K] = 4,
.relax_branch_isize[BR_RANGE_S64K] = 4,
},
.relax_code_condition[BR_RANGE_S16M] =
{
- {0, 20, 0x1F, FALSE},
- {0, 0, 0, FALSE},
+ {0, 20, 0x1F, false},
+ {0, 0, 0, false},
},
.relax_code_size[BR_RANGE_S16M] = 8,
.relax_branch_isize[BR_RANGE_S16M] = 4,
},
.relax_code_condition[BR_RANGE_U4G] =
{
- {0, 20, 0x1F, FALSE},
- {0, 0, 0, FALSE},
+ {0, 20, 0x1F, false},
+ {0, 0, 0, false},
},
.relax_code_size[BR_RANGE_U4G] = 16,
.relax_branch_isize[BR_RANGE_U4G] = 4,
.br_range = BR_RANGE_S64K,
.cond_field =
{
- {0, 20, 0x1F, FALSE},
- {0, 0, 0, FALSE}
+ {0, 20, 0x1F, false},
+ {0, 0, 0, false}
},
.relax_code_seq[BR_RANGE_S256] =
{
},
.relax_code_condition[BR_RANGE_S256] =
{
- {0, 20, 0x1F, FALSE},
- {0, 0, 0, FALSE},
+ {0, 20, 0x1F, false},
+ {0, 0, 0, false},
},
.relax_code_size[BR_RANGE_S256] = 4,
.relax_branch_isize[BR_RANGE_S256] = 4,
},
.relax_code_condition[BR_RANGE_S16K] =
{
- {0, 20, 0x1F, FALSE},
- {0, 0, 0, FALSE},
+ {0, 20, 0x1F, false},
+ {0, 0, 0, false},
},
.relax_code_size[BR_RANGE_S16K] = 4,
.relax_branch_isize[BR_RANGE_S16K] = 4,
},
.relax_code_condition[BR_RANGE_S64K] =
{
- {0, 20, 0x1F, FALSE},
- {0, 0, 0, FALSE},
+ {0, 20, 0x1F, false},
+ {0, 0, 0, false},
},
.relax_code_size[BR_RANGE_S64K] = 4,
.relax_branch_isize[BR_RANGE_S64K] = 4,
},
.relax_code_condition[BR_RANGE_S16M] =
{
- {0, 20, 0x1F, FALSE},
- {0, 0, 0, FALSE},
+ {0, 20, 0x1F, false},
+ {0, 0, 0, false},
},
.relax_code_size[BR_RANGE_S16M] = 8,
.relax_branch_isize[BR_RANGE_S16M] = 4,
},
.relax_code_condition[BR_RANGE_U4G] =
{
- {0, 20, 0x1F, FALSE},
- {0, 0, 0, FALSE},
+ {0, 20, 0x1F, false},
+ {0, 0, 0, false},
},
.relax_code_size[BR_RANGE_U4G] = 16,
.relax_branch_isize[BR_RANGE_U4G] = 4,
.br_range = BR_RANGE_S16K,
.cond_field =
{
- {0, 20, 0x1F, FALSE},
- {0, 15, 0x1F, FALSE},
- {0, 0, 0, FALSE}
+ {0, 20, 0x1F, false},
+ {0, 15, 0x1F, false},
+ {0, 0, 0, false}
},
.relax_code_seq[BR_RANGE_S256] =
{
},
.relax_code_condition[BR_RANGE_S256] =
{
- {0, 20, 0x1F, FALSE},
- {0, 15, 0x1F, FALSE},
- {0, 0, 0, FALSE}
+ {0, 20, 0x1F, false},
+ {0, 15, 0x1F, false},
+ {0, 0, 0, false}
},
.relax_code_size[BR_RANGE_S256] = 4,
.relax_branch_isize[BR_RANGE_S256] = 4,
},
.relax_code_condition[BR_RANGE_S16K] =
{
- {0, 20, 0x1F, FALSE},
- {0, 15, 0x1F, FALSE},
- {0, 0, 0, FALSE}
+ {0, 20, 0x1F, false},
+ {0, 15, 0x1F, false},
+ {0, 0, 0, false}
},
.relax_code_size[BR_RANGE_S16K] = 4,
.relax_branch_isize[BR_RANGE_S16K] = 4,
},
.relax_code_condition[BR_RANGE_S64K] =
{
- {0, 20, 0x1F, FALSE},
- {0, 15, 0x1F, FALSE},
- {0, 0, 0, FALSE}
+ {0, 20, 0x1F, false},
+ {0, 15, 0x1F, false},
+ {0, 0, 0, false}
},
.relax_code_size[BR_RANGE_S64K] = 8,
.relax_branch_isize[BR_RANGE_S64K] = 4,
},
.relax_code_condition[BR_RANGE_S16M] =
{
- {0, 20, 0x1F, FALSE},
- {0, 15, 0x1F, FALSE},
- {0, 0, 0, FALSE}
+ {0, 20, 0x1F, false},
+ {0, 15, 0x1F, false},
+ {0, 0, 0, false}
},
.relax_code_size[BR_RANGE_S16M] = 8,
.relax_branch_isize[BR_RANGE_S16M] = 4,
},
.relax_code_condition[BR_RANGE_U4G] =
{
- {0, 20, 0x1F, FALSE},
- {0, 15, 0x1F, FALSE},
- {0, 0, 0, FALSE}
+ {0, 20, 0x1F, false},
+ {0, 15, 0x1F, false},
+ {0, 0, 0, false}
},
.relax_code_size[BR_RANGE_U4G] = 16,
.relax_branch_isize[BR_RANGE_U4G] = 4,
.br_range = BR_RANGE_S16K,
.cond_field =
{
- {0, 20, 0x1F, FALSE},
- {0, 15, 0x1F, FALSE},
- {0, 0, 0, FALSE}
+ {0, 20, 0x1F, false},
+ {0, 15, 0x1F, false},
+ {0, 0, 0, false}
},
.relax_code_seq[BR_RANGE_S256] =
{
},
.relax_code_condition[BR_RANGE_S256] =
{
- {0, 20, 0x1F, FALSE},
- {0, 15, 0x1F, FALSE},
- {0, 0, 0, FALSE}
+ {0, 20, 0x1F, false},
+ {0, 15, 0x1F, false},
+ {0, 0, 0, false}
},
.relax_code_size[BR_RANGE_S256] = 4,
.relax_branch_isize[BR_RANGE_S256] = 4,
},
.relax_code_condition[BR_RANGE_S16K] =
{
- {0, 20, 0x1F, FALSE},
- {0, 15, 0x1F, FALSE},
- {0, 0, 0, FALSE}
+ {0, 20, 0x1F, false},
+ {0, 15, 0x1F, false},
+ {0, 0, 0, false}
},
.relax_code_size[BR_RANGE_S16K] = 4,
.relax_branch_isize[BR_RANGE_S16K] = 4,
},
.relax_code_condition[BR_RANGE_S64K] =
{
- {0, 20, 0x1F, FALSE},
- {0, 15, 0x1F, FALSE},
- {0, 0, 0, FALSE}
+ {0, 20, 0x1F, false},
+ {0, 15, 0x1F, false},
+ {0, 0, 0, false}
},
.relax_code_size[BR_RANGE_S64K] = 8,
.relax_branch_isize[BR_RANGE_S64K] = 4,
},
.relax_code_condition[BR_RANGE_S16M] =
{
- {0, 20, 0x1F, FALSE},
- {0, 15, 0x1F, FALSE},
- {0, 0, 0, FALSE}
+ {0, 20, 0x1F, false},
+ {0, 15, 0x1F, false},
+ {0, 0, 0, false}
},
.relax_code_size[BR_RANGE_S16M] = 8,
.relax_branch_isize[BR_RANGE_S16M] = 4,
},
.relax_code_condition[BR_RANGE_U4G] =
{
- {0, 20, 0x1F, FALSE},
- {0, 15, 0x1F, FALSE},
- {0, 0, 0, FALSE}
+ {0, 20, 0x1F, false},
+ {0, 15, 0x1F, false},
+ {0, 0, 0, false}
},
.relax_code_size[BR_RANGE_U4G] = 16,
.relax_branch_isize[BR_RANGE_U4G] = 4,
.br_range = BR_RANGE_S256,
.cond_field =
{
- {0, 8, 0x7, FALSE},
- {0, 0, 0, FALSE}
+ {0, 8, 0x7, false},
+ {0, 0, 0, false}
},
.relax_code_seq[BR_RANGE_S256] =
{
},
.relax_code_condition[BR_RANGE_S256] =
{
- {0, 8, 0x7, FALSE},
- {0, 0, 0, FALSE}
+ {0, 8, 0x7, false},
+ {0, 0, 0, false}
},
.relax_code_size[BR_RANGE_S256] = 2,
.relax_branch_isize[BR_RANGE_S256] = 2,
},
.relax_code_condition[BR_RANGE_S16K] =
{
- {0, 20, 0x1F, FALSE},
- {0, 0, 0, FALSE}
+ {0, 20, 0x1F, false},
+ {0, 0, 0, false}
},
.relax_code_size[BR_RANGE_S16K] = 4,
.relax_branch_isize[BR_RANGE_S16K] = 4,
},
.relax_code_condition[BR_RANGE_S64K] =
{
- {0, 20, 0x1F, FALSE},
- {0, 0, 0, FALSE}
+ {0, 20, 0x1F, false},
+ {0, 0, 0, false}
},
.relax_code_size[BR_RANGE_S64K] = 4,
.relax_branch_isize[BR_RANGE_S64K] = 4,
},
.relax_code_condition[BR_RANGE_S16M] =
{
- {0, 20, 0x1F, FALSE},
- {0, 0, 0, FALSE}
+ {0, 20, 0x1F, false},
+ {0, 0, 0, false}
},
.relax_code_size[BR_RANGE_S16M] = 8,
.relax_branch_isize[BR_RANGE_S16M] = 4,
},
.relax_code_condition[BR_RANGE_U4G] =
{
- {0, 20, 0x1F, FALSE},
- {0, 0, 0, FALSE}
+ {0, 20, 0x1F, false},
+ {0, 0, 0, false}
},
.relax_code_size[BR_RANGE_U4G] = 16,
.relax_branch_isize[BR_RANGE_U4G] = 4,
.br_range = BR_RANGE_S256,
.cond_field =
{
- {0, 8, 0x7, FALSE},
- {0, 0, 0, FALSE}
+ {0, 8, 0x7, false},
+ {0, 0, 0, false}
},
.relax_code_seq[BR_RANGE_S256] =
{
},
.relax_code_condition[BR_RANGE_S256] =
{
- {0, 8, 0x7, FALSE},
- {0, 0, 0, FALSE}
+ {0, 8, 0x7, false},
+ {0, 0, 0, false}
},
.relax_code_size[BR_RANGE_S256] = 2,
.relax_branch_isize[BR_RANGE_S256] = 2,
},
.relax_code_condition[BR_RANGE_S16K] =
{
- {0, 20, 0x1F, FALSE},
- {0, 0, 0, FALSE}
+ {0, 20, 0x1F, false},
+ {0, 0, 0, false}
},
.relax_code_size[BR_RANGE_S16K] = 4,
.relax_branch_isize[BR_RANGE_S16K] = 4,
},
.relax_code_condition[BR_RANGE_S64K] =
{
- {0, 20, 0x1F, FALSE},
- {0, 0, 0, FALSE}
+ {0, 20, 0x1F, false},
+ {0, 0, 0, false}
},
.relax_code_size[BR_RANGE_S64K] = 4,
.relax_branch_isize[BR_RANGE_S64K] = 4,
},
.relax_code_condition[BR_RANGE_S16M] =
{
- {0, 20, 0x1F, FALSE},
- {0, 0, 0, FALSE}
+ {0, 20, 0x1F, false},
+ {0, 0, 0, false}
},
.relax_code_size[BR_RANGE_S16M] = 8,
.relax_branch_isize[BR_RANGE_S16M] = 4,
},
.relax_code_condition[BR_RANGE_U4G] =
{
- {0, 20, 0x1F, FALSE},
- {0, 0, 0, FALSE}
+ {0, 20, 0x1F, false},
+ {0, 0, 0, false}
},
.relax_code_size[BR_RANGE_U4G] = 16,
.relax_branch_isize[BR_RANGE_U4G] = 4,
.br_range = BR_RANGE_S256,
.cond_field =
{
- {0, 0, 0, FALSE}
+ {0, 0, 0, false}
},
.relax_code_seq[BR_RANGE_S256] =
{
.br_range = BR_RANGE_S256,
.cond_field =
{
- {0, 0, 0, FALSE}
+ {0, 0, 0, false}
},
.relax_code_seq[BR_RANGE_S256] =
{
.br_range = BR_RANGE_S256,
.cond_field =
{
- {0, 8, 0x7, FALSE},
- {0, 0, 0, FALSE}
+ {0, 8, 0x7, false},
+ {0, 0, 0, false}
},
.relax_code_seq[BR_RANGE_S256] =
{
},
.relax_code_condition[BR_RANGE_S256] =
{
- {0, 8, 0x7, FALSE},
- {0, 0, 0, FALSE}
+ {0, 8, 0x7, false},
+ {0, 0, 0, false}
},
.relax_code_size[BR_RANGE_S256] = 2,
.relax_branch_isize[BR_RANGE_S256] = 2,
},
.relax_code_condition[BR_RANGE_S16K] =
{
- {0, 20, 0x1F, FALSE},
- {0, 0, 0, FALSE}
+ {0, 20, 0x1F, false},
+ {0, 0, 0, false}
},
.relax_code_size[BR_RANGE_S16K] = 4,
.relax_branch_isize[BR_RANGE_S16K] = 4,
},
.relax_code_condition[BR_RANGE_S64K] =
{
- {0, 20, 0x1F, FALSE},
- {0, 0, 0, FALSE}
+ {0, 20, 0x1F, false},
+ {0, 0, 0, false}
},
.relax_code_size[BR_RANGE_S64K] = 8,
.relax_branch_isize[BR_RANGE_S64K] = 4,
},
.relax_code_condition[BR_RANGE_S16M] =
{
- {0, 20, 0x1F, FALSE},
- {0, 0, 0, FALSE}
+ {0, 20, 0x1F, false},
+ {0, 0, 0, false}
},
.relax_code_size[BR_RANGE_S16M] = 8,
.relax_branch_isize[BR_RANGE_S16M] = 4,
},
.relax_code_condition[BR_RANGE_U4G] =
{
- {0, 20, 0x1F, FALSE},
- {0, 0, 0, FALSE}
+ {0, 20, 0x1F, false},
+ {0, 0, 0, false}
},
.relax_code_size[BR_RANGE_U4G] = 16,
.relax_branch_isize[BR_RANGE_U4G] = 4,
.br_range = BR_RANGE_S256,
.cond_field =
{
- {0, 8, 0x7, FALSE},
- {0, 0, 0, FALSE}
+ {0, 8, 0x7, false},
+ {0, 0, 0, false}
},
.relax_code_seq[BR_RANGE_S256] =
{
},
.relax_code_condition[BR_RANGE_S256] =
{
- {0, 8, 0x7, FALSE},
- {0, 0, 0, FALSE}
+ {0, 8, 0x7, false},
+ {0, 0, 0, false}
},
.relax_code_size[BR_RANGE_S256] = 2,
.relax_branch_isize[BR_RANGE_S256] = 2,
},
.relax_code_condition[BR_RANGE_S16K] =
{
- {0, 20, 0x1F, FALSE},
- {0, 0, 0, FALSE}
+ {0, 20, 0x1F, false},
+ {0, 0, 0, false}
},
.relax_code_size[BR_RANGE_S16K] = 4,
.relax_branch_isize[BR_RANGE_S16K] = 4,
},
.relax_code_condition[BR_RANGE_S64K] =
{
- {0, 20, 0x1F, FALSE},
- {0, 0, 0, FALSE}
+ {0, 20, 0x1F, false},
+ {0, 0, 0, false}
},
.relax_code_size[BR_RANGE_S64K] = 8,
.relax_branch_isize[BR_RANGE_S64K] = 4,
},
.relax_code_condition[BR_RANGE_S16M] =
{
- {0, 20, 0x1F, FALSE},
- {0, 0, 0, FALSE}
+ {0, 20, 0x1F, false},
+ {0, 0, 0, false}
},
.relax_code_size[BR_RANGE_S16M] = 8,
.relax_branch_isize[BR_RANGE_S16M] = 4,
},
.relax_code_condition[BR_RANGE_U4G] =
{
- {0, 20, 0x1F, FALSE},
- {0, 0, 0, FALSE}
+ {0, 20, 0x1F, false},
+ {0, 0, 0, false}
},
.relax_code_size[BR_RANGE_U4G] = 16,
.relax_branch_isize[BR_RANGE_U4G] = 4,
.br_range = BR_RANGE_S256,
.cond_field =
{
- {0, 8, 0x7FF, TRUE},
- {0, 20, 0x1F, FALSE},
- {0, 0, 0, FALSE}
+ {0, 8, 0x7FF, true},
+ {0, 20, 0x1F, false},
+ {0, 0, 0, false}
},
.relax_code_seq[BR_RANGE_S256] =
{
},
.relax_code_condition[BR_RANGE_S256] =
{
- {0, 8, 0x7FF, FALSE},
- {0, 20, 0x1F, FALSE},
- {0, 0, 0, FALSE}
+ {0, 8, 0x7FF, false},
+ {0, 20, 0x1F, false},
+ {0, 0, 0, false}
},
.relax_code_size[BR_RANGE_S256] = 4,
.relax_branch_isize[BR_RANGE_S256] = 4,
},
.relax_code_condition[BR_RANGE_S16K] =
{
- {0, 0, 0xFFFFF, FALSE},
- {4, 20, 0x1F, FALSE},
- {0, 0, 0, FALSE}
+ {0, 0, 0xFFFFF, false},
+ {4, 20, 0x1F, false},
+ {0, 0, 0, false}
},
.relax_code_size[BR_RANGE_S16K] = 8,
.relax_branch_isize[BR_RANGE_S16K] = 4,
},
.relax_code_condition[BR_RANGE_S64K] =
{
- {0, 8, 0x7FF, FALSE},
- {0, 20, 0x1F, FALSE},
- {0, 0, 0, FALSE}
+ {0, 8, 0x7FF, false},
+ {0, 20, 0x1F, false},
+ {0, 0, 0, false}
},
.relax_code_size[BR_RANGE_S64K] = 8,
.relax_branch_isize[BR_RANGE_S64K] = 4,
},
.relax_code_condition[BR_RANGE_S16M] =
{
- {0, 8, 0x7FF, FALSE},
- {0, 20, 0x1F, FALSE},
- {0, 0, 0, FALSE}
+ {0, 8, 0x7FF, false},
+ {0, 20, 0x1F, false},
+ {0, 0, 0, false}
},
.relax_code_size[BR_RANGE_S16M] = 8,
.relax_branch_isize[BR_RANGE_S16M] = 4,
},
.relax_code_condition[BR_RANGE_U4G] =
{
- {0, 8, 0x7FF, FALSE},
- {0, 20, 0x1F, FALSE},
- {0, 0, 0, FALSE}
+ {0, 8, 0x7FF, false},
+ {0, 20, 0x1F, false},
+ {0, 0, 0, false}
},
.relax_code_size[BR_RANGE_U4G] = 16,
.relax_branch_isize[BR_RANGE_U4G] = 4,
.br_range = BR_RANGE_S256,
.cond_field =
{
- {0, 8, 0x7FF, TRUE},
- {0, 20, 0x1F, FALSE},
- {0, 0, 0, FALSE}
+ {0, 8, 0x7FF, true},
+ {0, 20, 0x1F, false},
+ {0, 0, 0, false}
},
.relax_code_seq[BR_RANGE_S256] =
{
},
.relax_code_condition[BR_RANGE_S256] =
{
- {0, 8, 0x7FF, FALSE},
- {0, 20, 0x1F, FALSE},
- {0, 0, 0, FALSE}
+ {0, 8, 0x7FF, false},
+ {0, 20, 0x1F, false},
+ {0, 0, 0, false}
},
.relax_code_size[BR_RANGE_S256] = 4,
.relax_branch_isize[BR_RANGE_S256] = 4,
},
.relax_code_condition[BR_RANGE_S16K] =
{
- {0, 0, 0xFFFFF, FALSE},
- {4, 20, 0x1F, FALSE},
- {0, 0, 0, FALSE}
+ {0, 0, 0xFFFFF, false},
+ {4, 20, 0x1F, false},
+ {0, 0, 0, false}
},
.relax_code_size[BR_RANGE_S16K] = 8,
.relax_branch_isize[BR_RANGE_S16K] = 4,
},
.relax_code_condition[BR_RANGE_S64K] =
{
- {0, 8, 0x7FF, FALSE},
- {0, 20, 0x1F, FALSE},
- {0, 0, 0, FALSE}
+ {0, 8, 0x7FF, false},
+ {0, 20, 0x1F, false},
+ {0, 0, 0, false}
},
.relax_code_size[BR_RANGE_S64K] = 8,
.relax_branch_isize[BR_RANGE_S64K] = 4,
},
.relax_code_condition[BR_RANGE_S16M] =
{
- {0, 8, 0x7FF, FALSE},
- {0, 20, 0x1F, FALSE},
- {0, 0, 0, FALSE}
+ {0, 8, 0x7FF, false},
+ {0, 20, 0x1F, false},
+ {0, 0, 0, false}
},
.relax_code_size[BR_RANGE_S16M] = 8,
.relax_branch_isize[BR_RANGE_S16M] = 4,
},
.relax_code_condition[BR_RANGE_U4G] =
{
- {0, 8, 0x7FF, FALSE},
- {0, 20, 0x1F, FALSE},
- {0, 0, 0, FALSE}
+ {0, 8, 0x7FF, false},
+ {0, 20, 0x1F, false},
+ {0, 0, 0, false}
},
.relax_code_size[BR_RANGE_U4G] = 16,
.relax_branch_isize[BR_RANGE_U4G] = 4,
};
#define PV_DONT_CARE 0
-static struct hash_control *nds32_pseudo_opcode_hash = NULL;
+static htab_t nds32_pseudo_opcode_hash = NULL;
static int
builtin_isreg (const char *s, const char *x ATTRIBUTE_UNUSED)
{
- if (s [0] == '$' && hash_find (nds32_gprs_hash, (s + 1)))
+ if (s [0] == '$' && str_hash_find (nds32_gprs_hash, (s + 1)))
return 1;
return 0;
}
if (*s != '$')
return -1;
s++;
- k = hash_find (nds32_gprs_hash, s);
+ k = str_hash_find (nds32_gprs_hash, s);
if (k == NULL)
return -1;
unsigned int pv ATTRIBUTE_UNUSED)
{
char *arg_label = argv[0];
- relaxing = TRUE;
+ relaxing = true;
/* b label */
if (nds32_pic)
{
{
md_assemblef ("j %s", arg_label);
}
- relaxing = FALSE;
+ relaxing = false;
}
static void
unsigned int pv ATTRIBUTE_UNUSED)
{
char *arg_label = argv[0];
- relaxing = TRUE;
+ relaxing = true;
/* bal|call label */
if (nds32_pic)
{
{
md_assemblef ("jal %s", arg_label);
}
- relaxing = FALSE;
+ relaxing = false;
}
static void
return;
}
- relaxing = TRUE;
+ relaxing = true;
/* rt, label */
if (!nds32_pic && !strstr (arg_label, "@"))
{
}
else
as_bad (_("need PIC qualifier with symbol. '%s'"), line);
- relaxing = FALSE;
+ relaxing = false;
}
static void
}
else if (!nds32_pic)
{
- relaxing = TRUE;
+ relaxing = true;
if (strstr (argv[1], "@TPOFF"))
{
/* ls.w $rt, sym@TPOFF */
md_assemblef ("sethi $ta,hi20(%s)", argv[1]);
md_assemblef ("%c%c%si %s,[$ta+lo12(%s)]", ls, size, sign, argv[0], argv[1]);
}
- relaxing = FALSE;
+ relaxing = false;
}
else
{
- relaxing = TRUE;
+ relaxing = true;
/* PIC code. */
if (strstr (argv[1], "@GOTOFF"))
{
{
as_bad (_("needs @GOT or @GOTOFF. %s"), argv[argc]);
}
- relaxing = FALSE;
+ relaxing = false;
}
}
static void
nds32_init_nds32_pseudo_opcodes (void)
{
- struct nds32_pseudo_opcode *opcode = nds32_pseudo_opcode_table;
+ struct nds32_pseudo_opcode *opcode;
- nds32_pseudo_opcode_hash = hash_new ();
- for ( ; opcode->opcode; opcode++)
- {
- void *op;
-
- op = hash_find (nds32_pseudo_opcode_hash, opcode->opcode);
- if (op != NULL)
- {
- as_warn (_("Duplicated pseudo-opcode %s."), opcode->opcode);
- continue;
- }
- hash_insert (nds32_pseudo_opcode_hash, opcode->opcode, opcode);
- }
+ nds32_pseudo_opcode_hash = str_htab_create ();
+ for (opcode = nds32_pseudo_opcode_table; opcode->opcode; opcode++)
+ if (str_hash_insert (nds32_pseudo_opcode_hash, opcode->opcode, opcode, 0))
+ as_fatal (_("duplicate %s"), opcode->opcode);
}
static struct nds32_pseudo_opcode *
}
op[i] = '\0';
- result = hash_find (nds32_pseudo_opcode_hash, op);
+ result = str_hash_find (nds32_pseudo_opcode_hash, op);
free (op);
return result;
}
}
++s;
} while (s[0] != '\0');
-end:
+ end:
/* Put the origin line for debugging. */
argv[argc] = line;
opcode->proc (argc, argv, opcode->pseudo_val);
int disable = 0;
/* Filter out the Disable option first. */
- if (strncmp (arg, "no-", 3) == 0)
+ if (startswith (arg, "no-"))
{
disable = 1;
arg += 3;
if (label != NULL)
{
symbolS *sym;
- int label_seen = FALSE;
+ int label_seen = false;
struct frag *old_frag;
valueT old_value, new_value;
&& S_GET_VALUE (sym) == old_value)
{
/* Warning HERE! */
- label_seen = TRUE;
+ label_seen = true;
symbol_set_frag (sym, frag_now);
S_SET_VALUE (sym, new_value);
}
abort ();
}
- symbol_p = symbol_new (symbol_name, now_seg, value, frag);
+ symbol_p = symbol_new (symbol_name, now_seg, frag, value);
/* local scope attribute */
symbol_get_bfdsym (symbol_p)->flags |= BSF_NO_FLAGS | BSF_LOCAL;
}
relax_hint_begin = 0;
name = nds_itoa (relax_hint_id_current);
-reordered_id:
+ reordered_id:
/* Find relax hint entry for next instruction, and all member will be
initialized at that time. */
- relocs = hash_find (nds32_hint_hash, name);
+ relocs = str_hash_find (nds32_hint_hash, name);
if (relocs == NULL)
{
relocs = XNEW (struct nds32_relocs_pattern);
memset (relocs, 0, sizeof (struct nds32_relocs_pattern));
- hash_insert (nds32_hint_hash, name, relocs);
+ str_hash_insert (nds32_hint_hash, name, relocs, 0);
}
else
{
group = group->next;
group->next = new;
}
- relaxing = TRUE;
+ relaxing = true;
}
/* Decide the size of vector entries, only accepts 4 or 16 now. */
nds32_asm_init (&asm_desc, flags);
/* Initial general purpose registers hash table. */
- nds32_gprs_hash = hash_new ();
+ nds32_gprs_hash = str_htab_create ();
for (k = keyword_gpr; k->name; k++)
- hash_insert (nds32_gprs_hash, k->name, k);
+ str_hash_insert (nds32_gprs_hash, k->name, k, 0);
/* Initial branch hash table. */
- nds32_relax_info_hash = hash_new ();
+ nds32_relax_info_hash = str_htab_create ();
for (relax_info = relax_table; relax_info->opcode; relax_info++)
- hash_insert (nds32_relax_info_hash, relax_info->opcode, relax_info);
+ str_hash_insert (nds32_relax_info_hash, relax_info->opcode, relax_info, 0);
/* Initial relax hint hash table. */
- nds32_hint_hash = hash_new ();
+ nds32_hint_hash = str_htab_create ();
enable_16bit = nds32_16bit_ext;
}
nds32_elf_build_relax_relation (fixS *fixP, expressionS *pexp, char* out,
struct nds32_asm_insn *insn, fragS *fragP,
const struct nds32_field *fld,
- bfd_boolean pseudo_hint)
+ bool pseudo_hint)
{
struct nds32_relocs_pattern *reloc_ptr;
struct nds32_relocs_group *group;
/* Set relaxing false only for relax_hint trigger it. */
if (!pseudo_opcode)
- relaxing = FALSE;
+ relaxing = false;
}
#define N32_MEM_EXT(insn) ((N32_OP6_MEM << 25) | insn)
not, optimize option, 16 bit instruction is enable. */
#define SET_ADDEND(size, convertible, optimize, insn16_on) \
- (((size) & 0xff) | ((convertible) ? 1 << 31 : 0) \
- | ((optimize) ? 1<< 30 : 0) | (insn16_on ? 1 << 29 : 0))
+ (((size) & 0xff) | ((convertible) ? 1u << 31 : 0) \
+ | ((optimize) ? 1 << 30 : 0) | (insn16_on ? 1 << 29 : 0))
#define MAC_COMBO (E_NDS32_HAS_FPU_MAC_INST|E_NDS32_HAS_MAC_DX_INST)
static void
/* Find the relaxation pattern according to instructions. */
-static bfd_boolean
+static bool
nds32_find_reloc_table (struct nds32_relocs_pattern *relocs_pattern,
struct nds32_relax_hint_table *hint_info)
{
default:
as_warn (_("relax hint unrecognized instruction: line %d."),
pattern->frag->fr_line);
- return FALSE;
+ return false;
}
}
else
if (!nds32_pic)
as_warn (_("Can not find match relax hint. Line: %d"),
relocs_pattern->frag->fr_line);
- return FALSE;
+ return false;
}
/* Get the match table. */
if (opc)
{
/* Branch relax pattern. */
- relax_info = hash_find (nds32_relax_info_hash, opc);
+ relax_info = str_hash_find (nds32_relax_info_hash, opc);
if (!relax_info)
- return FALSE;
+ return false;
fixup_info = relax_info->relax_fixup[range];
code_seq = relax_info->relax_code_seq[range];
seq_size = relax_info->relax_code_size[range];
table_ptr++;
}
if (table_ptr->main_type == 0)
- return FALSE;
+ return false;
}
else
- return FALSE;
+ return false;
hint_fixup = hint_info->relax_fixup;
hint_code = hint_info->relax_code_seq;
memset (hint_fixup, 0, sizeof (nds32_relax_fixup_info_t));
/* Copy code sequence. */
memcpy (hint_code, code_seq, seq_size);
- return TRUE;
+ return true;
}
/* Because there are a lot of variant of load-store, check
#define CLEAN_REG(insn) ((insn) & 0xfe0003ff)
#define GET_OPCODE(insn) ((insn) & 0xfe000000)
-static bfd_boolean
+static bool
nds32_match_hint_insn (struct nds32_opcode *opcode, uint32_t seq)
{
const char *check_insn[] =
insn = CLEAN_REG (opcode->value);
if (insn == seq)
- return TRUE;
+ return true;
switch (seq)
{
|| insn == OP6 (LWI) || insn == OP6 (SWI)
|| insn == OP6 (LWC) || insn == OP6 (SWC)
|| insn == OP6 (LDC) || insn == OP6 (SDC))
- return TRUE;
+ return true;
break;
case OP6 (BR2):
/* This is for LONGCALL5 and LONGCALL6. */
if (insn == OP6 (BR2))
- return TRUE;
+ return true;
break;
case OP6 (BR1):
/* This is for LONGJUMP5 and LONGJUMP6. */
if (opcode->isize == 4
&& (insn == OP6 (BR1) || insn == OP6 (BR2) || insn == OP6 (BR3)))
- return TRUE;
+ return true;
else if (opcode->isize == 2)
{
for (i = 0; i < ARRAY_SIZE (check_insn); i++)
if (strcmp (opcode->opcode, check_insn[i]) == 0)
- return TRUE;
+ return true;
}
break;
case OP6 (MOVI):
/* This is for LONGJUMP7. */
if (opcode->isize == 2 && strcmp (opcode->opcode, "movi55") == 0)
- return TRUE;
+ return true;
break;
case OP6 (MEM):
if (OP6 (MEM) == GET_OPCODE (insn))
- return TRUE;
+ return true;
break;
case OP6 (JREG):
/* bit 24: N32_JI_JAL */ /* feed me! */
if ((insn & ~(N32_BIT (24))) == JREG (JRAL))
- return TRUE;
+ return true;
break;
default:
if (opcode->isize == 2)
{
for (i = 0; i < ARRAY_SIZE (check_insn); i++)
if (strcmp (opcode->opcode, check_insn[i]) == 0)
- return TRUE;
+ return true;
if ((strcmp (opcode->opcode, "add5.pc") == 0) ||
(strcmp (opcode->opcode, "add45") == 0))
- return TRUE;
+ return true;
}
}
- return FALSE;
+ return false;
}
/* Append relax relocation for link time relaxing. */
static void
-nds32_elf_append_relax_relocs (const char *key, void *value)
+nds32_elf_append_relax_relocs (const char *key, const void *value)
{
struct nds32_relocs_pattern *relocs_pattern =
(struct nds32_relocs_pattern *) value;
fixup_size = fixup_now->size;
/* Insert all fixup. */
+ pcrel = 0;
while (fixup_size != 0 && fixup_now->offset == offset)
{
/* Set the real instruction size in element. */
{
ptr_offset =
pattern_temp->where - pattern_temp->frag->fr_literal;
- exp.X_add_symbol = symbol_temp_new (now_seg, ptr_offset,
- pattern_temp->frag);
+ exp.X_add_symbol = symbol_temp_new (now_seg,
+ pattern_temp->frag,
+ ptr_offset);
exp.X_add_number = 0;
fixP =
fix_new_exp (fragP, where - fragP->fr_literal,
{
ptr_offset = next_pattern->where
- next_pattern->frag->fr_literal;
- exp.X_add_symbol = symbol_temp_new (now_seg, ptr_offset,
- next_pattern->frag);
+ exp.X_add_symbol = symbol_temp_new (now_seg,
+ next_pattern->frag,
+ ptr_offset);
exp.X_add_number = 0;
fixP = fix_new_exp (fragP, where - fragP->fr_literal,
fixup_size, &exp, 0,
ptr_offset = next_insn->where
- next_insn->frag->fr_literal;
exp.X_add_symbol = symbol_temp_new (now_seg,
- ptr_offset,
- next_insn->frag);
+ next_insn->frag,
+ ptr_offset);
exp.X_add_number = 0;
fixP = fix_new_exp (fragP,
where - fragP->fr_literal,
pattern_now = pattern_now->next;
}
-restore:
+ restore:
now_seg = seg_bak;
frchain_now = frchain_bak;
}
+static int
+nds32_elf_append_relax_relocs_traverse (void **slot, void *arg ATTRIBUTE_UNUSED)
+{
+ string_tuple_t *tuple = *((string_tuple_t **) slot);
+ nds32_elf_append_relax_relocs (tuple->key, tuple->value);
+ return 1;
+}
+
+
static void
nds32_str_tolower (const char *src, char *dest)
{
/* Check instruction if it can be used for the baseline. */
-static bfd_boolean
+static bool
nds32_check_insn_available (struct nds32_asm_insn insn, const char *str)
{
int attr = insn.attr & ATTR_ALL;
|| (insn.attr & NASM_ATTR_ZOL)))
{
as_bad (_("Not support instruction %s in verbatim."), str);
- return FALSE;
+ return false;
}
free (s);
if (!enable_16bit && insn.opcode->isize == 2)
{
as_bad (_("16-bit instruction is disabled: %s."), str);
- return FALSE;
+ return false;
}
/* No isa setting or all isa can use. */
if (attr == 0 || attr == ATTR_ALL)
- return TRUE;
+ return true;
if (baseline_isa == 0)
{
if ((baseline_isa & attr) == 0)
{
as_bad (_("Instruction %s not supported in the baseline."), str);
- return FALSE;
+ return false;
}
- return TRUE;
+ return true;
}
/* Stub of machine dependent. */
struct nds32_relocs_group *group_temp;
fragS *fragP;
int label = label_exist;
- static bfd_boolean pseudo_hint = FALSE;
+ static bool pseudo_hint = false;
popcode = nds32_lookup_pseudo_opcode (str);
/* Note that we need to check 'verbatim' and
{
/* Pseudo instruction is with relax_hint. */
if (relaxing)
- pseudo_hint = TRUE;
- pseudo_opcode = TRUE;
+ pseudo_hint = true;
+ pseudo_opcode = true;
nds32_pseudo_opcode_wrapper (str, popcode);
- pseudo_opcode = FALSE;
- pseudo_hint = FALSE;
+ pseudo_opcode = false;
+ pseudo_hint = false;
nds32_elf_append_relax_relocs (NULL, relocs_list);
/* Free relax_hint group list. */
return 0;
}
- relax_info = hash_find (nds32_relax_info_hash, opcode->opcode);
+ relax_info = str_hash_find (nds32_relax_info_hash, opcode->opcode);
if (relax_info == NULL)
return adjust;
/* Check the prev_frag is legal. */
static void
-invalid_prev_frag (fragS * fragP, fragS **prev_frag, bfd_boolean relax)
+invalid_prev_frag (fragS * fragP, fragS **prev_frag, bool relax)
{
addressT address;
fragS *frag_start = *prev_frag;
static fragS *prev_frag = NULL;
int adjust = 0;
- invalid_prev_frag (fragP, &prev_frag, TRUE);
+ invalid_prev_frag (fragP, &prev_frag, true);
if (fragP->tc_frag_data.flag & NDS32_FRAG_BRANCH)
adjust = nds32_relax_branch_instructions (segment, fragP, stretch, 0);
static fragS *prev_frag = NULL;
int adjust = 0;
- invalid_prev_frag (fragP, &prev_frag, FALSE);
+ invalid_prev_frag (fragP, &prev_frag, false);
if (fragP->tc_frag_data.flag & NDS32_FRAG_BRANCH)
adjust = nds32_relax_branch_instructions (segment, fragP, 0, 1);
if (fragP->tc_frag_data.flag & NDS32_FRAG_RELAXABLE_BRANCH)
{
- relax_info = hash_find (nds32_relax_info_hash, opcode->opcode);
+ relax_info = str_hash_find (nds32_relax_info_hash, opcode->opcode);
if (relax_info == NULL)
return;
else if (fragP->tc_frag_data.flag & NDS32_FRAG_BRANCH)
{
/* Branch instruction adjust and append relocations. */
- relax_info = hash_find (nds32_relax_info_hash, opcode->opcode);
+ relax_info = str_hash_find (nds32_relax_info_hash, opcode->opcode);
if (relax_info == NULL)
return;
if ((fixup_info[i].ramp & NDS32_CREATE_LABEL) != 0)
{
/* This is a reverse branch. */
- exp.X_add_symbol = symbol_temp_new (sec, 0, fragP->fr_next);
+ exp.X_add_symbol = symbol_temp_new (sec, fragP->fr_next, 0);
exp.X_add_number = 0;
}
else if ((fixup_info[i].ramp & NDS32_PTR) != 0)
{
/* This relocation has to point to another instruction. */
branch_size = fr_where + code_size - 4;
- exp.X_add_symbol = symbol_temp_new (sec, branch_size, fragP);
+ exp.X_add_symbol = symbol_temp_new (sec, fragP, branch_size);
exp.X_add_number = 0;
}
else if ((fixup_info[i].ramp & NDS32_ABS) != 0)
{
}
-static bfd_boolean
+static bool
nds32_relaxable_section (asection *sec)
{
return ((sec->flags & SEC_DEBUGGING) == 0
static void
nds32_elf_analysis_relax_hint (void)
{
- hash_traverse (nds32_hint_hash, nds32_elf_append_relax_relocs);
+ htab_traverse (nds32_hint_hash, nds32_elf_append_relax_relocs_traverse, NULL);
}
static void
/* Implement md_allow_local_subtract. */
-bfd_boolean
+bool
nds32_allow_local_subtract (expressionS *expr_l ATTRIBUTE_UNUSED,
expressionS *expr_r ATTRIBUTE_UNUSED,
segT sec ATTRIBUTE_UNUSED)
{
/* Don't allow any subtraction, because relax may change the code. */
- return FALSE;
+ return false;
}
/* Sort relocation by address.
relocation. */
void
-nds32_set_section_relocs (asection *sec, arelent ** relocs ATTRIBUTE_UNUSED,
- unsigned int n ATTRIBUTE_UNUSED)
+nds32_set_section_relocs (asection *sec ATTRIBUTE_UNUSED,
+ arelent **relocs, unsigned int n)
{
- bfd *abfd ATTRIBUTE_UNUSED = sec->owner;
- if (bfd_section_flags (sec) & (flagword) SEC_RELOC)
- nds32_insertion_sort (sec->orelocation, sec->reloc_count,
- sizeof (arelent**), compar_relent);
+ if (n <= 1)
+ return;
+
+ nds32_insertion_sort (relocs, n, sizeof (*relocs), compar_relent);
}
long
Return whether this symbol (fixup) can be replaced with
section symbols. */
-bfd_boolean
+bool
nds32_fix_adjustable (fixS *fixP)
{
switch (fixP->fx_r_type)
int
tc_nds32_regname_to_dw2regnum (char *regname)
{
- struct nds32_keyword *sym = hash_find (nds32_gprs_hash, regname);
+ struct nds32_keyword *sym = str_hash_find (nds32_gprs_hash, regname);
if (!sym)
return -1;
projects / binutils-gdb.git / blobdiff