/* tc-pdp11.c - pdp11-specific -
- Copyright (C) 2001-2016 Free Software Foundation, Inc.
+ Copyright (C) 2001-2019 Free Software Foundation, Inc.
This file is part of GAS, the GNU Assembler.
arg += 3;
}
- /* Commersial instructions. */
+ /* Commercial instructions. */
if (strcmp (arg, "cis") == 0)
pdp11_extension[PDP11_CIS] = yes;
/* Call supervisor mode. */
{
/* On a PDP-11, 0x1234 is stored as "\x12\x34", and
0x12345678 is stored as "\x56\x78\x12\x34". It's
- anyones guess what 0x123456 would be stored like. */
+ anyone's guess what 0x123456 would be stored like. */
switch (nbytes)
{
switch (fixP->fx_r_type)
{
+ case BFD_RELOC_8:
+ mask = 0xff;
+ shift = 0;
+ break;
case BFD_RELOC_16:
case BFD_RELOC_16_PCREL:
mask = 0xffff;
{
/* On a PDP-11, 0x1234 is stored as "\x12\x34", and
0x12345678 is stored as "\x56\x78\x12\x34". It's
- anyones guess what 0x123456 would be stored like. */
+ anyone's guess what 0x123456 would be stored like. */
switch (nbytes)
{
case 0:
str += 2;
}
else
- {
- operand->error = _("Bad register name");
- return str;
- }
+ operand->error = _("Bad register name");
return str;
}
if (*str == '@' || *str == '*')
{
- str = parse_op_no_deferred (str + 1, operand);
+ /* @(Rn) == @0(Rn): Mode 7, Indexed deferred.
+ Check for auto-increment deferred. */
+ if (str[1] == '('
+ && str[2] != 0
+ && str[3] != 0
+ && str[4] != 0
+ && str[5] != '+')
+ {
+ /* Change implied to explicit index deferred. */
+ *str = '0';
+ str = parse_op_no_deferred (str, operand);
+ }
+ else
+ {
+ /* @Rn == (Rn): Register deferred. */
+ str = parse_reg (str + 1, operand);
+
+ /* Not @Rn */
+ if (operand->error)
+ {
+ operand->error = NULL;
+ str = parse_op_no_deferred (str, operand);
+ }
+ }
+
if (operand->error)
return str;
+
operand->code |= 010;
}
else
\n\
PDP-11 instruction set extensions:\n\
\n\
--m(no-)cis allow (disallow) commersial instruction set\n\
+-m(no-)cis allow (disallow) commercial instruction set\n\
-m(no-)csm allow (disallow) CSM instruction\n\
-m(no-)eis allow (disallow) full extended instruction set\n\
-m(no-)fis allow (disallow) KEV11 floating-point instructions\n\
-m(no-)ucode allow (disallow) microcode instructions\n\
-mall-extensions allow all instruction set extensions\n\
(this is the default)\n\
--mno-extentions disallow all instruction set extensions\n\
--pic generate position-indepenent code\n\
+-mno-extensions disallow all instruction set extensions\n\
+-pic generate position-independent code\n\
\n\
PDP-11 CPU model options:\n\
\n\